1. A process detection method is characterized by comprising the following steps:

providing a substrate, wherein a bottom layer functional structure and a functional layer to be detected positioned above the bottom layer functional structure are formed on the substrate, an opening is formed in the functional layer to be detected, and the opening exposes the bottom layer functional structure;

providing a layout graph of the bottom layer functional structure as a first layout graph, and providing a layout graph of the opening as a second layout graph;

acquiring a contour graph of the opening;

overlapping the outline graph and the second layout graph to obtain an overlapped graph;

and comparing the relative position relationship between the outline graph and the first version graph according to the superimposed graph, and detecting weak points according to the relative position relationship.

2. The process inspection method of claim 1, wherein the step of obtaining the outline pattern of the opening comprises: acquiring a measuring graph of the opening;

and extracting boundary features of the opening from the measurement graph, and converting the boundary features into a contour graph.

3. The process detection method according to claim 1, wherein after the overlay processing is performed on the outline pattern and the second layout pattern, the process detection method further comprises: and measuring the critical dimension of the profile graph at the position to be measured according to the overlay graph.

4. The process detection method according to claim 1, wherein after the outline pattern of the opening is obtained, before the outline pattern and the second layout pattern are subjected to the overlay processing, the process detection method further comprises: and filling the area corresponding to the bottom layer functional structure in the outline graph by using the first layout graph.

5. The process inspection method of claim 4, wherein the step of filling comprises: and implementing logical OR operation on the outline graph and the first edition graph.

6. The process detection method according to claim 3, wherein after the overlay processing is performed on the outline pattern and the second layout pattern, the critical dimension of the outline pattern at the position to be measured is measured according to the overlay pattern before the relative position relationship between the outline pattern and the first layout pattern is compared according to the overlay pattern.

7. The process detection method according to claim 1, wherein in the step of providing the substrate, a plurality of openings are formed in the functional layer to be detected, the plurality of openings extending in a first direction and being arranged in parallel in a second direction, the first direction being perpendicular to the second direction;

the step of comparing the relative positional relationship between the outline graphic and the first layout graphic according to the overlay graphic includes:

setting any bottom layer functional structure as a bottom layer functional structure to be tested;

setting a profile graph corresponding to an opening where the bottom layer functional structure to be detected is located as a first graph to be detected;

setting any side of a first layout graph corresponding to the bottom layer functional structure to be detected in the second direction as a first side to be detected, and setting a side of the first graph to be detected, which is opposite to the first side to be detected in the second direction, as a second side to be detected;

measuring the distance from the first edge to be measured to the second edge to be measured as a first distance;

calculating the proportion of the first distance to the side length of the first layout graph along the second direction;

and judging whether the proportion is smaller than a first preset threshold value or not, and judging that the weak point exists when the proportion is smaller than the first preset threshold value.

8. The process detection method of claim 7, wherein the first predetermined threshold is 50% to 150%.

9. The process detection method according to claim 1, wherein in the step of providing the substrate, a plurality of openings are formed in the functional layer to be detected, the plurality of openings extending in a first direction and being arranged in parallel in a second direction, the first direction being perpendicular to the second direction;

the step of comparing the relative positional relationship between the outline graphic and the first layout graphic according to the overlay graphic includes:

setting any bottom layer functional structure as a bottom layer functional structure to be tested;

setting the outline graph corresponding to the opening where the bottom layer functional structure to be detected is located as a first graph to be detected, and setting the outline graph adjacent to the first graph to be detected in the second direction as a second graph to be detected;

setting any side of a first layout graph corresponding to the bottom layer functional structure to be detected in the second direction as a first side to be detected, and setting a side of a second graph to be detected adjacent to the first side to be detected in the second direction as a third side to be detected;

measuring the distance from the first side to be measured to the third side to be measured as a second distance;

calculating the proportion of the second distance to the interval between the first graph to be tested and the second graph to be tested;

and judging whether the proportion is smaller than a second preset threshold value or not, and judging that the weak point exists when the proportion is smaller than the second preset threshold value.

10. The process detection method of claim 9, wherein the second predetermined threshold is 50% to 150%.

11. The process detection method of claim 1, wherein the step of providing the layout pattern of the opening as the second layout pattern comprises: providing an original layout graph of the opening;

and carrying out round-corner treatment on the outline of the original layout graph.

12. A process detection system is suitable for detecting a substrate, wherein a bottom layer functional structure and a functional layer to be detected positioned above the bottom layer functional structure are formed on the substrate, an opening is formed in the functional layer to be detected, and the opening is exposed out of the bottom layer functional structure, and the process detection system is characterized by comprising:

the first graph obtaining module is used for providing the layout graph of the bottom layer functional structure as a first layout graph and providing the layout graph of the opening as a second layout graph;

the second graph acquisition module is used for acquiring the outline graph of the opening;

the figure stacking module is used for stacking the outline figure and the second layout figure to obtain a stacked figure;

and the judging module is used for comparing the relative position relationship between the outline graph and the first version graph according to the superposed graph and detecting weak points according to the relative position relationship.

13. An apparatus comprising at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the process detection method of any one of claims 1 to 11.

14. A storage medium having stored thereon one or more computer instructions for implementing a process detection method according to any one of claims 1 to 11.

Background

As semiconductor manufacturing technology advances, the minimum feature size of semiconductor devices becomes smaller and smaller, and the pattern density and complexity become higher, resulting in a higher probability of weak spots (weakpoints) occurring after each process step. In order to ensure the performance of a semiconductor device, it is necessary to quickly and accurately find weak points generated after each process step and perform risk assessment in the manufacturing process of the semiconductor device, thereby accelerating the development of technology and improving the yield.

The detection method commonly used at present is to detect the weak point by using a computer automatic detection mode. However, the current detection method can only detect very limited defect pattern types between the patterns on the wafer and the corresponding layout patterns, so as to evaluate the weak point of a certain layer of film. However, for complex patterns, especially for weak points under the common influence of multi-layer structures (such as adjacent two-layer structures), the current detection method has difficulty in obtaining accurate detection results.

Disclosure of Invention

The embodiment of the invention aims to provide a process detection method, a system, equipment and a storage medium, and improve the precision of process detection.

In order to solve the above problem, an embodiment of the present invention provides a process detection method, including: providing a substrate, wherein a bottom layer functional structure and a functional layer to be detected positioned above the bottom layer functional structure are formed on the substrate, an opening is formed in the functional layer to be detected, and the opening exposes the bottom layer functional structure; providing a layout graph of the bottom layer functional structure as a first layout graph, and providing a layout graph of the opening as a second layout graph; acquiring a contour graph of the opening; overlapping the outline graph and the second layout graph to obtain an overlapped graph; and comparing the relative position relationship between the outline graph and the first version graph according to the superimposed graph, and detecting weak points according to the relative position relationship.

Accordingly, an embodiment of the present invention further provides a process detection system, which is adapted to detect a substrate, where a bottom layer functional structure and a functional layer to be detected located above the bottom layer functional structure are formed on the substrate, an opening is formed in the functional layer to be detected, and the opening exposes the bottom layer functional structure, and the process detection system includes: the first graph obtaining module is used for providing the layout graph of the bottom layer functional structure as a first layout graph and providing the layout graph of the opening as a second layout graph; the second graph acquisition module is used for acquiring the outline graph of the opening; the figure stacking module is used for stacking the outline figure and the second layout figure to obtain a stacked figure; and the judging module is used for comparing the relative position relationship between the outline graph and the first version graph according to the superposed graph and detecting weak points according to the relative position relationship.

Accordingly, an embodiment of the present invention further provides an apparatus, which includes at least one memory and at least one processor, where the memory stores one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the foregoing process detection method.

Correspondingly, the embodiment of the invention also provides a storage medium, wherein one or more computer instructions are stored in the storage medium and used for realizing the process detection method.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

the embodiment of the invention provides a process detection method, which is suitable for detecting a substrate, wherein a bottom layer functional structure and a functional layer to be detected positioned above the bottom layer functional structure are formed on the substrate, an opening is formed in the functional layer to be detected, the opening exposes the bottom layer functional structure, a layout graph of the bottom layer functional structure is provided as a first layout graph, the layout graph of the opening is provided as a second layout graph, an outline graph of the opening is obtained, then the outline graph and the second layout graph are subjected to superposition processing to obtain a superposed graph, then the relative position relation between the outline graph and the first layout graph is compared according to the superposed graph, and a weak point is detected according to the relative position relation; the boundary of the first layout graph corresponding to the bottom layer functional structure is clear and complete, so that the judgment result is more accurate by comparing the relative position relationship between the outline graph and the first layout graph, and the precision of process detection is correspondingly improved.

Drawings

FIG. 1 is a corresponding electron micrograph of a semiconductor structure;

FIG. 2 is a flow chart of one embodiment of a process detection method of the present invention;

FIG. 3 is a top view of one embodiment of the underlying functional structure and functional layer to be detected corresponding to step S1 in FIG. 2;

FIG. 4 is a diagram illustrating an embodiment of a first version of the graph corresponding to step S2 in FIG. 2;

FIG. 5 is a diagram of an embodiment of a second layout pattern corresponding to step S2 in FIG. 2;

FIG. 6 is a schematic diagram of an embodiment of the outline graphic corresponding to step S3 in FIG. 2;

FIG. 7 is a diagram illustrating an embodiment of an overlay graphic corresponding to step S4 in FIG. 2;

FIG. 8 is a schematic diagram corresponding to step S5 in FIG. 2;

FIG. 9 is a functional block diagram of an embodiment of a process detection system of the present invention;

fig. 10 is a hardware configuration diagram of an apparatus according to an embodiment of the present invention.

Detailed Description

As known in the background art, the current detection method is difficult to obtain accurate detection results. The reason why the precision of the process detection needs to be improved is analyzed by combining an electron microscope scanning image corresponding to a semiconductor structure.

Referring to fig. 1, a corresponding electron micrograph of a semiconductor structure is shown.

The semiconductor structure comprises a bottom layer functional structure 15 located on a substrate (not shown), and a functional layer 10 to be detected located above the bottom layer functional structure 15, wherein an opening 11 is formed in the functional layer 10 to be detected, and the opening 11 exposes the bottom layer functional structure 15.

When a scanning device is used to obtain the scanning image of the electron microscope (especially when a scanning electron microscope is used for shooting), on one hand, the scanning device adjusts the best focus based on the functional layer 10 to be detected, and on the other hand, if the opening 11 is formed in the functional layer 10 to be detected, the problem of displacement or deformation of the opening 11 occurs, which easily causes that the real shape of the bottom functional structure 15 cannot be clearly seen.

For example, the distance between the opening 11 where the bottom layer functional structure 15 is located and another adjacent opening 11 is too small, or the opening 11 where the bottom layer functional structure 15 is located and another adjacent opening 11 are fused, or the functional layer 10 to be detected covers a part of the bottom layer functional structure 15, the size of the bottom layer functional structure 15 shown in the electron microscope scanning image becomes smaller, and even the bottom layer functional structure 15 disappears.

As shown in fig. 1, the dimensions of the underlying functional structures 15 shown by the dashed circles 12 are all smaller than the dimensions of the other underlying functional structures 15.

Under the influence of the above two factors, it is easy to cause the image of the underlying functional structure 15 to be blurred in the electron microscope scan, so that the outline of the underlying functional structure 15 is difficult to be extracted, or the extracted outline pattern cannot reflect the real situation.

Therefore, when the relative position between the underlying functional structure 15 and the opening 11 shown in the above-mentioned electron microscope scan is used to detect a weak point, the process detection accuracy is low.

In order to solve the technical problem, an embodiment of the present invention provides a process detection method, including: providing a substrate, wherein a bottom layer functional structure and a functional layer to be detected positioned above the bottom layer functional structure are formed on the substrate, an opening is formed in the functional layer to be detected, and the opening exposes the bottom layer functional structure; providing a layout graph of the bottom layer functional structure as a first layout graph, and providing a layout graph of the opening as a second layout graph; acquiring a contour graph of the opening; overlapping the outline graph and the second layout graph to obtain an overlapped graph; and comparing the relative position relationship between the outline graph and the first version graph according to the superimposed graph, and detecting weak points according to the relative position relationship.

In the embodiment of the invention, the boundary of the first layout graph corresponding to the bottom layer functional structure is clear and complete, so that the judgment result is more accurate by comparing the relative position relationship between the outline graph and the first layout graph, and the precision of process detection is correspondingly improved.

Referring to fig. 2, a flow chart of an embodiment of the process detection method of the present invention is shown. The detection method of the embodiment comprises the following basic steps:

step S1: providing a substrate, wherein a bottom layer functional structure and a functional layer to be detected positioned above the bottom layer functional structure are formed on the substrate, an opening is formed in the functional layer to be detected, and the opening exposes the bottom layer functional structure;

step S2: providing a layout graph of the bottom layer functional structure as a first layout graph, and providing a layout graph of the opening as a second layout graph;

step S3: acquiring a contour graph of the opening;

step S4: overlapping the outline graph and the second layout graph to obtain an overlapped graph;

step S5: and comparing the relative position relationship between the outline graph and the first version graph according to the superimposed graph, and detecting weak points according to the relative position relationship.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 3, step S1 is executed to provide a substrate 100, where the substrate 100 has a bottom functional structure 110 and a functional layer 125 to be detected located above the bottom functional structure 110, and an opening 120 is formed in the functional layer 125 to be detected, and the opening 120 exposes the bottom functional structure 110.

The bottom layer functional structure 110 and the functional layer 125 to be detected are formed by a semiconductor process, and the substrate 100 is used for providing a process platform for forming the bottom layer functional structure 110 and the functional layer 125 to be detected.

In this embodiment, the opening 120 in the functional layer 125 to be detected is formed by an etching process.

As an example, the bottom functional structure 110 is a contact hole plug (CT), the functional layer 125 to be detected is an inter-metal dielectric layer (IMD), and the opening 120 is used to form a metal interconnection layer electrically connected to the contact hole plug.

The detection method is used to detect whether the relative position relationship between the opening 120 and the underlying functional structure 110 satisfies the process requirement, so as to detect the weak point to evaluate the process risk.

In this embodiment, a plurality of openings 120 are formed in the functional layer 125 to be detected, and the plurality of openings 120 extend along a first direction (shown as an X direction in fig. 3) and are arranged in parallel along a second direction (shown as a Y direction in fig. 3), and the first direction is perpendicular to the second direction.

With combined reference to fig. 4 and 5, step S2 is performed to provide the layout pattern of the underlying functional structure 110 (shown in fig. 3) as the first layout pattern 200 and provide the layout pattern of the opening 120 (shown in fig. 3) as the second layout pattern 300.

As an example, fig. 4 only illustrates the layout of the underlying functional structure 110 in the area indicated by the dashed box a in fig. 3.

The first layout pattern 200 is used as a reference pattern when determining whether there is a weak point in the relative position relationship between the underlying functional structure 110 and the opening 120 (shown in fig. 3).

Subsequently, when the weak point detection is performed on the opening 120 itself, the second layout pattern 300 is used as a reference pattern.

In this embodiment, the first layout graph and the second layout graph are provided by an original layout file.

The original layout file refers to a layout file which is designed and formed by an EDA tool and contains all layout graph information, and a mask graph corresponding to a mask (mask) can be obtained from the layout graph.

Generally, the original layout file is a layout file that has passed drc (design rule check) verification. As an example, the format of the original layout file is GDS (gerber data stream) format. In other embodiments, the format of the original layout file may also be other formats such as OASIS.

As shown in fig. 5, as an example, the second layout drawing 300 includes a first sub-layout drawing 311 and a second sub-layout drawing 312, the first sub-layout drawing 311 and the second sub-layout drawing 312 are stored in different layers in the original layout file, and the first sub-layout drawing 311 and the second sub-layout drawing 312 can be obtained separately.

The first sub-layout pattern 311 and the second sub-layout pattern 312 are both used for forming the opening 120. In the semiconductor process, two masks (masks) are used, and the functional layer 125 to be detected is formed in a double patterning mode, wherein the first sub-layout pattern 311 and the second sub-layout pattern 312 are respectively used for defining a pattern on each mask.

Specifically, the step of providing the layout pattern of the opening 120 as the second layout pattern 300 includes: providing an original layout pattern of the opening 120; and carrying out round-corner treatment on the outline of the original layout graph.

The process for forming the opening 120 further includes a photolithography process, and after the original layout pattern of the opening 120 is transferred to the photoresist layer by the photolithography process, the pattern is transferred to the functional layer 125 to be detected by the patterned photoresist layer. The pattern formed in the photoresist layer often differs from the original layout pattern, for example, a right angle in the original layout pattern may form a round corner (rounding) after transferring into the photoresist layer. That is, after the outline pattern of the opening 120 is obtained, the corners of the outline pattern of the opening 120 are also rounded.

Therefore, the second layout pattern 300 is obtained by performing the rounding processing on the outline of the original layout pattern of the opening 120, so that the second layout pattern 300 is closer to the outline of the opening 120 in appearance, and the subsequent outline pattern is better overlapped with the second layout pattern 300. In particular, the effect of the rounding process is more pronounced when the pattern complexity is higher and the feature size is smaller.

Specifically, a specific "rounding" operation is applied to the EDA tool, the operation is simple, and the rounding processing does not have a simulation meaning, so that in the process of the rounding processing, each edge of the original layout graph does not need to be divided into a plurality of segments (fragments), and therefore, the operation speed of the rounding processing is high, so that the detection efficiency is not reduced.

Referring to fig. 6, step S3 is executed to obtain the outline pattern 400 of the opening 120 (shown in fig. 3).

By acquiring the outline pattern 400, the method is provided for subsequently determining whether there is a weak point in the relative position relationship between the underlying functional structure 110 (shown in fig. 3) and the opening 120, and is also provided for subsequently performing weak point detection on the opening 120 itself.

Specifically, the step of acquiring the outline pattern 400 includes: obtaining a measurement pattern of the opening 120; boundary features of the opening 120 are extracted from the metrology pattern and converted to a profile pattern.

In the present embodiment, the metrology profile of the opening 120 is acquired via a Critical Dimension Scanning Electron Microscope (CDSEM) image.

In this embodiment, the step of extracting the boundary feature of the opening 120 from the metrology pattern includes: converting the measurement graph into a gray graph; and carrying out edge feature extraction operation on the gray level graph.

With continued reference to fig. 2, after obtaining the outline pattern 400 (as shown in fig. 6), the process inspection method further includes: step S31 is executed to fill the area corresponding to the bottom functional structure 110 in the outline pattern 400 by using the first layout pattern 200 (as shown in fig. 4).

The subsequent steps further include superimposing the outline pattern 400 and the second layout pattern 300 (as shown in fig. 5), wherein the opening 120 exposes the bottom layer functional structure 110, so that after the outline pattern 400 is obtained, the existence of the bottom layer functional structure 110 causes the noise outline 250 (as shown in fig. 6) of the bottom layer functional structure 110 to appear in the area corresponding to the bottom layer functional structure 110 in the outline pattern 400, which causes the outline pattern 400 to be mismatched with the second layout pattern 300, thereby increasing the alignment difficulty, even difficult to align when the outline pattern 400 and the second layout pattern 300 are subsequently overlapped.

Therefore, by performing the filling process, the noise profile 250 of the underlying functional structure 110 is removed.

The padding process is used to implement boolean operations. Specifically, the filling process includes: a logical or operation is implemented on the outline graphic 400 and the first version graphic 200.

Referring to fig. 7, after the filling process, step S4 is executed to perform an overlay process on the outline pattern 400 (shown in fig. 6) and the second layout pattern 300 (shown in fig. 5) to obtain an overlay pattern 500.

The outline pattern 400 herein refers to the outline pattern 400 after the filling process is completed.

By obtaining the overlay 500, it is possible to provide for subsequent vulnerability detection of the opening 120 (shown in fig. 3) itself, and to provide for subsequent determination of whether a vulnerability exists in the relative positional relationship between the underlying functional structure 110 (shown in fig. 3) and the opening 120.

Specifically, the superimposition processing may be performed using graphics superimposition software.

It should be noted that the outline pattern 400 corresponds to the opening 120, and the second layout pattern 300 also corresponds to the opening 120, so that the outline pattern 400 can only be overlapped with the second layout pattern 300. However, the first layout graph 200 and the second layout graph 300 are both provided by original layout files, and the first layout graph 200 and the second layout graph 300 are located in the same coordinate system, so that the effect of overlapping the outline graph 400 and the first layout graph 200 is obtained after the outline graph 400 and the second layout graph 300 are overlapped.

For ease of illustration, the second layout drawing 300 is not illustrated in fig. 7.

With continued reference to fig. 2, the process inspection method further comprises: step S41 is executed to measure the critical dimension of the profile graphics 400 at the position to be measured according to the overlay graphics.

This step is used to determine whether the opening 120 (shown in fig. 3) itself has weak points, for example, whether the pattern corresponding to the opening 120 is deformed or broken, or whether the opening size of the opening 120 along the second direction (shown in the Y direction in fig. 3) meets the process requirements. Wherein, in the judging process, the second layout pattern 300 is used as a reference pattern.

Wherein the critical dimension includes an opening dimension of the opening 120 and a space (space) between adjacent openings 120.

As an example, the opening size of the profile 400 at the position to be measured is measured, and when the measured opening size is zero or greatly differs from an opening size threshold, this position is defined as a weak point position.

Similarly, the spacing of adjacent openings 120 of the profile 400 at the location to be measured is measured, and when the measured spacing is zero or significantly different from the spacing threshold, the location is defined as the location of the weak point.

It should be noted that in this step, the detected weak point is only associated with the opening 120 itself.

In this embodiment, the step of detecting the weak point of the opening 120 itself and the step of detecting the weak point under the influence of the opening 120 and the bottom functional structure 110 are integrated into the same detection flow, so as to improve the integrity and compatibility of the detection process.

Referring to fig. 8, step S5 is executed to compare the relative position relationship between the outline pattern 400 and the first layout pattern 200 according to the overlay pattern 500, and detect a weak point according to the relative position relationship.

The first layout graph 200 and the second layout graph 300 are both provided by original layout files, the first layout graph 200 and the second layout graph 300 are located in the same coordinate system, the effect that the outline graph 400 and the first layout graph 200 are overlapped is obtained after the outline graph 400 and the second layout graph 300 are overlapped, and the outline graph 400 and the first layout graph 200 are both located in the same coordinate system, so that the relative position relationship between the outline graph 400 and the first layout graph 200 can be compared according to the overlapped graph 500 in the embodiment.

The relative positions of the outline pattern 400 and the first layout pattern 200 are determined to meet the process requirements, thereby determining whether a weak spot exists, where the weak spot is affected by the combination of the opening 120 (shown in fig. 3) and the underlying functional structure 110 (shown in fig. 3). For example, if the opening 120 in the functional layer 125 to be detected is displaced, the functional layer 125 to be detected covers a part of the bottom functional structure 110, that is, the opening 120 cannot completely expose the corresponding bottom functional structure 110, or the bottom functional structure 110 is exposed by another opening 120, and the above weak point easily causes the performance of the formed semiconductor structure to be degraded.

The boundary of the first layout pattern 200 corresponding to the bottom layer functional structure 110 is clear and complete, so that the judgment result is more accurate by comparing the relative position relationship between the outline pattern 400 and the first layout pattern 200, and the precision of the process detection is correspondingly improved.

In this embodiment, the step of comparing the relative position relationship between the outline graphic 400 and the first layout graphic 200 according to the overlay graphic 500 includes: setting any one of the bottom layer functional structures 110 as a bottom layer functional structure to be tested (not labeled); setting the outline graph 400 corresponding to the opening 120 where the bottom layer functional structure to be tested is located as a first graph 411 to be tested; setting any edge of the first layout pattern 200 corresponding to the underlying functional structure to be tested in the second direction (as shown in the Y direction in fig. 3) as a first edge to be tested 413, and setting an edge of the first pattern to be tested 411 facing away from the first edge to be tested 413 in the second direction as a second edge to be tested 414; measuring the distance from the first edge to be measured 413 to the second edge to be measured 414 as a first distance d 1; calculating the proportion of the first distance d1 to the side length w of the first layout graph 200 along the second direction; and judging whether the proportion is smaller than a first preset threshold value or not, and judging that the weak point exists when the proportion is larger than the first preset threshold value. The side length w of the first layout graph 200 along the second direction is a preset side length.

That is, when the ratio is smaller than the first preset threshold, it indicates that the displacement of the opening 120 corresponding to the to-be-detected bottom layer functional structure causes the to-be-detected functional layer 125 to cover a part of the bottom layer functional structure 110, that is, the corresponding opening 120 only exposes a part of the bottom layer functional structure 110. The first preset threshold value is not too small or too large. If the first preset threshold is too small, the monitoring capability of the weak point is easily reduced, so that the actual process risk cannot be accurately reflected by the process detection method; if the first preset threshold is too large, the detection structure is not in accordance with the actual process risk, and a weak point false alarm problem is caused in the semiconductor manufacturing process, so that the manufacturing efficiency is reduced. For this reason, in the present embodiment, the first preset threshold is 50% to 150%, for example, 75%, 100%, 125%.

In this embodiment, the step of comparing the relative position relationship between the outline graphic 400 and the first layout graphic 200 according to the overlay graphic 500 further includes: setting any one of the bottom-layer functional structures 110 as a bottom-layer functional structure to be tested, and after setting the outline pattern 400 corresponding to the opening 120 where the bottom-layer functional structure to be tested is located as a first pattern to be tested 411, setting the outline pattern 400 adjacent to the first pattern to be tested 411 in the second direction as a second pattern to be tested 412; setting any side of the first layout graph 200 corresponding to the underlying functional structure to be tested in the second direction as a first side to be tested 416, and setting a side of the second graph 412 to be tested adjacent to the first side to be tested 416 in the second direction as a third side to be tested 415; measuring the distance from the first edge to be measured 416 to the third edge to be measured 415 as a second distance d 2; calculating the ratio of the second distance d2 to the distance s between the first graph 411 to be measured and the second graph 412 to be measured; and judging whether the proportion is smaller than a second preset threshold value or not, and judging that the weak point exists when the proportion is smaller than the second preset threshold value.

That is, when the ratio is smaller than the second preset threshold, it indicates that there is a risk that the bottom layer functional structure 110 is located in another opening 120, or that a part of the bottom layer functional structure 110 is located in another opening 120.

The second preset threshold should not be too small, nor too large. If the second preset threshold is too small, the monitoring capability of the weak point is easily reduced, so that the actual process risk cannot be accurately reflected by the process detection method; if the second preset threshold is too large, the detection structure is not in accordance with the actual process risk, and a weak point false alarm problem is caused in the semiconductor manufacturing process, so that the manufacturing efficiency is reduced. For this reason, in the present embodiment, the second preset threshold is 50% to 150%, for example, 75%, 100%, 125%.

Through the combination of the two comparison methods, it can be determined whether the bottom layer functional structure 110 is located in the corresponding opening 120 and whether the bottom layer functional structure 110 is located in another adjacent opening 120 for the same bottom layer functional structure 110, so as to improve the reliability of the process detection.

It should be noted that, in other embodiments, the detection of the weak point may be performed in one of the two manners according to the process requirement (e.g., the requirement of process risk control).

It should be further noted that, in this embodiment, after the overlay processing is performed on the outline pattern 400 and the second layout pattern 300, before the relative position relationship between the outline pattern 400 and the first layout pattern 200 is compared according to the overlay pattern 500, the critical dimension of the outline pattern 400 at the position to be measured is measured according to the overlay pattern 500. In other embodiments, after the overlay processing is performed on the outline pattern and the second layout pattern, the relative position relationship between the outline pattern and the first layout pattern may be compared according to the overlay pattern, and then the critical dimension of the outline pattern at the position to be measured may be measured according to the overlay pattern, that is, the weak point under the influence of the opening and the bottom layer functional structure is detected first, and then the weak point of the opening to be measured is detected.

Correspondingly, the invention also provides a process detection system. Referring to FIG. 9, a functional block diagram of an embodiment of a process detection system of the present invention is shown.

With reference to fig. 3, fig. 3 is a top view, the process detection system is suitable for detecting a substrate 100, a bottom layer functional structure 110 and a functional layer 125 to be detected located above the bottom layer functional structure 110 are formed on the substrate 100, an opening 120 is formed in the functional layer 125 to be detected, and the opening 120 exposes the bottom layer functional structure 110.

Referring to fig. 9, the layout pattern correction system includes: a first pattern obtaining module 20, configured to provide the layout pattern of the underlying functional structure 110 as a first layout pattern 200 (shown in fig. 4), and further provide the layout pattern of the opening 120 as a second layout pattern 300 (shown in fig. 5); a second pattern obtaining module 30 for obtaining a contour pattern 400 (shown in fig. 6) of the opening 120; a graph stacking module 80, configured to perform stacking processing on the outline graph 400 and the second layout graph 300 to obtain a stacked graph 500 (as shown in fig. 7); the judging module 90 is configured to compare the relative position relationship between the outline graph 400 and the first layout graph 200 according to the overlay graph 500, and detect a weak point according to the relative position relationship.

The boundary of the first layout pattern 200 corresponding to the bottom layer functional structure 110 is clear and complete, so that after the relative position relationship between the outline pattern 400 and the first layout pattern 200 is compared by using the judging module 90, the judgment result is more accurate, correspondingly, the process detection system is used for process detection, and the detection precision is higher.

The bottom functional structure 110 and the functional layer 125 to be detected are formed by a semiconductor process. In this embodiment, the opening 120 in the functional layer 125 to be detected is formed by an etching process. As an example, the bottom functional structure 110 is a contact hole plug, the functional layer 125 to be detected is an inter-metal dielectric layer, and the opening 120 is used to form a metal interconnection layer electrically connected to the contact hole plug

The detection system is used to detect whether the relative position relationship between the opening 120 and the underlying functional structure 110 satisfies the process requirement, so as to detect the weak point and evaluate the process risk.

In this embodiment, a plurality of openings 120 are formed in the functional layer 125 to be detected, and the plurality of openings 120 extend along a first direction (shown as an X direction in fig. 3) and are arranged in parallel along a second direction (shown as a Y direction in fig. 3), and the first direction is perpendicular to the second direction.

The first pattern obtaining module 20 is configured to provide a layout pattern of the bottom layer functional structure 110 as a first layout pattern 200, and further provide a layout pattern of the opening 120 as a second layout pattern 300.

In this embodiment, the first layout pattern 200 and the second layout pattern 300 are provided by an original layout file. Therefore, the first graph obtaining module 20 is integrated into the layout graph reading software, and the first graph obtaining module 20 is configured to read the first layout graph 200 and the second layout graph 300 from the original layout file.

The process detection system is further configured to perform weak point detection on the opening 120 itself, and the second layout pattern 300 is used as a reference pattern when performing weak point detection on the opening 120 itself.

In this embodiment, the first graph obtaining module 20 includes: an original layout providing unit 21 for providing an original layout pattern of the opening 120; and the outline processing unit 22 is used for performing round corner processing on the outline of the original layout graph of the opening 120.

Corners of the original layout pattern are right angles, and the outline of the original layout pattern is rounded by using the outline processing unit 22, so that the second layout pattern 300 is closer to the outline pattern 400 of the opening 120 in appearance, and the subsequent outline pattern 400 is better overlapped with the second layout pattern 300. In particular, the effect of the rounding process is more pronounced when the pattern complexity is higher and the feature size is smaller. In particular, the contour processing unit 22 is integrated in an EDA tool.

The second image obtaining module 30 is used for obtaining the outline image 400 of the opening 120.

By acquiring the outline pattern 400, the method is provided for subsequently judging whether a weak point exists in the relative position relationship between the underlying functional structure 110 and the opening 120, and is also provided for subsequently performing weak point detection on the opening 120 itself.

Specifically, the second image obtaining module 30 includes: a measurement pattern obtaining unit 31 for obtaining a measurement pattern of the opening 120; a feature extraction and format conversion unit 32, configured to extract boundary features of the opening 120 from the metrology pattern, and convert the boundary features into a profile pattern 400.

In this embodiment, the measurement pattern obtaining unit 31 includes a cd-sem, and the feature extracting and format converting unit 32 may be contour extracting software.

In this embodiment, the process detection system further includes: a filling module 50, configured to perform a filling process on an area of the outline pattern 400 corresponding to the bottom functional structure 110 by using the first layout pattern 200.

Since the opening 120 exposes the bottom layer functional structure 110, the existence of the bottom layer functional structure 110 causes the noise contour 250 (as shown in fig. 6) of the bottom layer functional structure 110 to appear in the region of the contour pattern 400 corresponding to the bottom layer functional structure 110, which causes the contour pattern 400 of the functional layer 125 to be detected not to match with the second layout pattern 300, thereby increasing the alignment difficulty when overlapping the contour pattern 400 with the second layout pattern 300, and even making alignment difficult.

Thus, with the filling module 50, the noise profile 250 of the underlying functional structure 110 is removed.

In this embodiment, the filling module 50 is used to implement boolean operations. Specifically, the filling module 50 is configured to implement a logical or operation on the outline graph 400 and the first layout graph 200.

The graph superimposing module 80 is configured to perform superimposing processing on the outline graph 400 and the second layout graph 300 to obtain a superimposed graph 500 (as shown in fig. 7).

Here, the outline pattern 400 refers to the outline pattern 400 after the filling process is completed.

The overlay graphic 500 is obtained by the graphic overlay module 80 to provide for subsequent vulnerability detection of the opening 120 itself and for subsequent determination of whether a vulnerability exists in the relative positional relationship between the underlying functional structure 110 and the opening 120.

Specifically, the graphics overlay module 80 may be graphics overlay software.

It should be noted that the outline pattern 400 corresponds to the opening 120, and the second layout pattern 30 also corresponds to the opening 120, so that the pattern overlay module 80 can only overlay the outline pattern 400 and the second layout pattern 300. However, the first layout graph 200 and the second layout graph 300 are both provided by original layout files, and the first layout graph 200 and the second layout graph 300 are located in the same coordinate system, so that the effect of overlapping the outline graph 400 and the first layout graph 200 is obtained after the outline graph 400 and the second layout graph 300 are overlapped.

In this embodiment, the process detection system can not only detect the weak point of the opening 120, but also detect the weak point under the common influence of the opening 120 and the bottom functional structure 110, and can achieve the effect of automatic detection, so as to improve the usability of the process detection system.

For example, when the process inspection system is used for inspection, the inspection of the weak point under the combined influence of the opening 120 and the underlying functional structure 110 can be automatically started after the detection of the weak point of the opening 120 itself; alternatively, after detecting the weak point under the influence of the opening 120 and the underlying functional structure 110, the detection of the weak point of the opening 120 itself is automatically started.

For ease of illustration, the second layout drawing 300 is not illustrated in fig. 7.

The process detection system further comprises: a dimension measuring module 70 for measuring the critical dimension of the profile graphics 400 at the position to be measured according to the overlay graphics 500. Here, the outline pattern 400 measured by the dimension measurement module 70 is the outline pattern 400 processed by the fill module 50.

Through the dimension measuring module 70, it is determined whether the opening 120 itself has a weak point, for example, whether a pattern corresponding to the opening 120 is deformed or broken, or whether an opening dimension of the opening 120 in the second direction meets a process requirement.

The critical dimensions include the opening size of the opening 120 and also the spacing (space) of adjacent openings 120.

As an example, the dimension measuring module 70 is used for measuring the opening dimension of the outline pattern 400 at the position to be measured. Wherein the location is defined as the weak point location when the measured opening dimension is zero or substantially different from the critical dimension threshold.

Similarly, the CD analysis module 70 is also used to measure the spacing between adjacent openings 120 of the profile 400 at the locations to be measured. Wherein when the measured separation is zero or very different from the separation threshold, the location is defined as the weak point location.

It should be noted that the weak points detected by the critical dimension analysis module 70 are only associated with the opening 120 itself.

The judging module 90 is configured to compare the relative position relationship between the outline graph 400 and the first layout graph 200 according to the overlay graph 500, and detect a weak point according to the relative position relationship.

The determining module 90 is configured to determine whether a relative position between the outline pattern 400 and the first layout pattern 200 meets a process requirement, so as to determine whether a weak spot exists, where the weak spot is affected by the opening 120 and the bottom layer functional structure 110, for example, if the opening 120 in the functional layer 125 to be detected is displaced, the bottom layer functional structure 110 covered by a portion of the functional layer 125 to be detected is caused, that is, the opening 120 cannot completely expose the corresponding bottom layer functional structure 110, or the bottom layer functional structure 110 is exposed by another opening 120, where the weak spot easily causes performance degradation of the formed semiconductor structure.

Therefore, the result of the determination module 90 is utilized to evaluate whether there is a process risk after the opening 120 is formed in the functional layer 125 to be detected.

The boundary of the first layout pattern 200 corresponding to the bottom layer functional structure 110 is clear and complete, so that the judgment result is more accurate by comparing the relative position relationship between the outline pattern 400 and the first layout pattern 200, and the precision of the process detection is correspondingly improved.

In this embodiment, the determining module 90 includes: a first setting unit 91, configured to set any one of the bottom layer functional structures 110 as a bottom layer functional structure (not labeled) to be tested; a second setting unit 92, configured to set the outline pattern 400 corresponding to the opening 120 where the bottom layer functional structure to be tested is located as a first pattern 411 to be tested; a third setting unit 93, configured to set any edge of the first layout pattern 200 corresponding to the underlying functional structure to be tested in the second direction as a first edge to be tested 413 (as shown in fig. 8), and further set an edge of the first image to be tested 411 facing away from the first edge to be tested 413 in the second direction as a second edge to be tested 414 (as shown in fig. 8); a measuring unit 94, configured to measure a distance from the first side to be measured 411 to the second side to be measured 414 as a first distance d1 (shown in fig. 8); a calculating unit 95, configured to calculate a ratio of the first distance d1 to a side length w of the first layout graphic 200 along the second direction; the judging unit 96 is configured to judge whether the ratio is smaller than a first preset threshold, and when the ratio is smaller than the first preset threshold, determine that the ratio has a weak point. The side length w of the first layout graph 200 along the second direction is a preset side length.

That is, when the result that the ratio is smaller than the first preset threshold is obtained by the determining module 90, it indicates that the functional layer 125 to be detected is displaced to cover a part of the bottom functional structure 110, that is, the corresponding opening 120 is exposed only to a part of the bottom functional structure 110.

In this embodiment, the second setting unit 92 is further configured to set the outline graphic 400 adjacent to the first graphic to be measured 411 in the second direction as a second graphic to be measured 412.

Correspondingly, after setting any edge of the first layout pattern 200 corresponding to the underlying functional structure to be tested in the second direction as the first edge to be tested 416 (as shown in fig. 8), the third setting unit 93 is further configured to set an edge of the second pattern to be tested 412 adjacent to the first edge to be tested 416 in the second direction as the third edge to be tested 415 (as shown in fig. 8).

The measuring unit 94 is further configured to measure a distance from the first side to be measured 416 to the third side to be measured 415 as a second distance d 2; the calculation unit 95 is further configured to calculate a ratio of the second distance d2 to the distance s between the first graph 411 to be measured and the second graph 412 to be measured; the determining unit 96 is further configured to determine whether the ratio is smaller than a second preset threshold, and determine that the ratio has a weak point when the ratio is smaller than the second preset threshold.

That is, when the result that the ratio is smaller than the second preset threshold is obtained through the determining module 90, it indicates that there is a risk that the bottom-layer functional structure 110 is located in another opening 120, or a risk that a part of the bottom-layer functional structure 110 is located in another opening 120.

To sum up, the process inspection system of the present embodiment can determine, for the same bottom functional structure 110, whether the bottom functional structure 110 is located in the corresponding opening 120, and whether the bottom functional structure 110 is located in another adjacent opening 120, so as to improve the reliability of the process inspection.

In other embodiments, the process detection system may also be used to implement one of the above-mentioned methods of vulnerability detection, depending on the process requirements (e.g., requirements for process risk management).

The embodiment of the invention also provides equipment which can realize the process detection method provided by the embodiment of the invention by loading the process detection method in a program form.

Referring to fig. 10 in combination, a hardware structure diagram of the device provided by an embodiment of the invention is shown. The device of the embodiment comprises: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.

In this embodiment, the number of the processor 01, the communication interface 02, the memory 03 and the communication bus 04 is at least one, and the processor 01, the communication interface 02 and the memory 03 complete mutual communication through the communication bus 04.

The communication interface 02 may be an interface of a communication module for performing network communication, for example, an interface of a GSM module.

The processor 01 may be a central processing unit CPU, or an application Specific Integrated circuit asic, or one or more Integrated circuits configured to implement the process detection method of the present embodiment.

The memory 03 may comprise a high-speed RAM memory, and may further comprise a non-volatile memory (non-volatile memory), such as at least one disk memory.

Wherein the memory 03 stores one or more computer instructions, which are executed by the processor 01 to implement the process detection method provided by the foregoing embodiments.

It should be noted that the above terminal device may further include other devices (not shown) that may not be necessary for the disclosure of the embodiment of the present invention; these other components may not be necessary to understand the disclosure of embodiments of the present invention, which are not individually described herein.

The embodiment of the present invention further provides a storage medium, where one or more computer instructions are stored in the storage medium, and the one or more computer instructions are used to implement the process detection method provided in the foregoing embodiment.

In the embodiment of the invention, the process detection method is used for detecting a substrate, a bottom layer functional structure and a functional layer to be detected positioned above the bottom layer functional structure are formed on the substrate, an opening is formed in the functional layer to be detected, and the opening exposes the bottom layer functional structure; the process detection method comprises the steps of providing a layout graph of a bottom layer functional structure as a first layout graph and providing a layout graph of an opening as a second layout graph, obtaining an outline graph of the opening, then performing overlapping processing on the outline graph and the second layout graph to obtain an overlapped graph, comparing the relative position relationship between the outline graph and the first layout graph according to the overlapped graph, and detecting weak points according to the relative position relationship; the boundary of the first layout graph corresponding to the bottom layer functional structure is clear and complete, so that the judgment result is more accurate by comparing the relative position relationship between the outline graph and the first layout graph, and the precision of process detection is correspondingly improved.

The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise mentioned, the elements or features may be considered optional. Each element or feature may be practiced without being combined with other elements or features. In addition, the embodiments of the present invention may be configured by combining some elements and/or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any embodiment may be included in another embodiment, and may be replaced with corresponding configurations of the other embodiment. It is obvious to those skilled in the art that claims that are not explicitly cited in each other in the appended claims may be combined into an embodiment of the present invention or may be included as new claims in a modification after the filing of the present application.

Embodiments of the invention may be implemented by various means, such as hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, and the like.

In a firmware or software configuration, embodiments of the present invention may be implemented in the form of modules, procedures, functions, and the like. The software codes may be stored in memory units and executed by processors. The memory unit is located inside or outside the processor, and may transmit and receive data to and from the processor via various known means.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.