1. A method of chip verification, comprising:

compiling a neural network model corresponding to the SDK plug-in of the software development kit through a tool chain to obtain a first executable file;

running an environment model corresponding to the SDK plug-in to obtain first golden data;

running the first executable file through a reference model corresponding to the SDK plug-in to obtain a first execution result, wherein the reference model is used for simulating a hardware executable program of a simulation simulator corresponding to the chip to be tested;

and verifying the reference model corresponding to the SDK plug-in based on the first golden data and the first execution result.

2. The method of claim 1, further comprising:

and the reference model verifies the simulation simulator corresponding to the chip to be tested on the basis of the first golden data and the first executable file provided by the environment model.

3. The method of claim 1 or 2, wherein the number of the SDK plug-ins is one or more, and the neural network model corresponding to each SDK plug-in comprises at least one of the following:

the device comprises a neural network for realizing the function of an SDK plug-in, a first processing module for preprocessing the input of the neural network and a second processing module for post-processing the output of the neural network.

4. The method of any of claims 1-3, wherein the number of SDK plug-ins is multiple, further comprising:

in response to the verification of the reference model corresponding to each SDK plugin, sequentially connecting the SDK plugins, wherein the output of the reference model corresponding to the SDK plugin with the previous connection sequence is used as the input of the reference model corresponding to the next SDK plugin with the subsequent connection sequence;

the pre-extracted target feature information is used as the input of the reference model corresponding to the first SDK plug-in unit, and a second execution result output by the reference model corresponding to the second SDK plug-in unit is obtained; wherein the first SDK plugin is a first SDK plugin in the plurality of sequentially connected SDK plugins, and the second SDK plugin is a last SDK plugin in the plurality of sequentially connected plugins;

and verifying the reference model corresponding to each SDK plug-in again based on the second execution result and the target execution result.

5. The method of claim 4, further comprising:

and taking the target characteristic information as the input of a target neural network model, and operating the target neural network model on a central processing unit to obtain the target execution result, wherein the target neural network is the neural network model obtained after the neural network models corresponding to the plurality of SDK plug-ins are sequentially connected.

6. The method according to claim 4 or 5, wherein the target feature information comprises at least one of face feature information and human body feature information included in a scene image processed by a visual task.

7. The method of any of claims 4-6, further comprising:

after the reference model corresponding to each SDK plug-in unit is verified to be correct again, second golden data corresponding to the plurality of SDK plug-in units connected in sequence are obtained;

and verifying the simulator corresponding to the chip to be tested based on the second golden data.

8. The method according to any one of claims 1 to 7, wherein the neural network model corresponding to the SDK plug-in and the reference model corresponding to the SDK plug-in perform information interaction based on a shared target memory and a socket manner.

9. The method according to any one of claims 1-8, further comprising:

the neural network model corresponding to the SDK plug-in sends the first executable file to the reference model corresponding to the SDK plug-in;

and the reference model corresponding to the SDK plug-in receives the first executable file through a corresponding preset virtual Micro Control Unit (MCU).

10. The method according to any one of claims 1 to 9, wherein a process of the neural network model corresponding to the SDK plug-in has a first mapping address mapped randomly in a shared dynamic random access memory, and the preset virtual MCU process corresponding to the reference model corresponding to the SDK plug-in reads data from a second mapping address in the shared dynamic random access memory; wherein the first mapped address is different from the second mapped address.

11. A chip verification apparatus, comprising:

the compiling module is used for compiling the neural network model corresponding to the SDK plug-in of the software development kit through the tool chain to obtain a first executable file;

the first operation module is used for operating the environment model corresponding to the SDK plug-in unit to obtain first golden data;

the second running module is used for running the first executable file through a reference model corresponding to the SDK plug-in to obtain a first execution result, and the reference model is used for simulating a hardware executable program of a simulation simulator corresponding to the chip to be tested;

and the first verification module is used for verifying the reference model corresponding to the SDK plug-in based on the first golden data and the first execution result.

12. A computer-readable storage medium, characterized in that the storage medium stores a computer program for executing the chip verification method according to any one of claims 1 to 10.

13. A chip verification apparatus, comprising:

a processor;

a memory for storing the processor-executable instructions;

wherein the processor is configured to invoke executable instructions stored in the memory to implement the chip verification method of any one of claims 1-10.

Background

At present, the chip verification process can be divided into several stages, i.e., Unit Test (UT), Integration Test (IT), and System Test (ST). The UT verification stage emphasizes module-level verification, the IT verification stage emphasizes subsystem-level verification, and the ST verification stage emphasizes system-wide verification. In the UT verification phase and the IT verification phase, due to the limited size of the module design, the determination of the global verification result is relatively insensitive in the case of well-defined boundaries. Also, just because of the limited design scale, the algorithm can be easily designed to match bits (bit by bit match), and the traditional way of using fixed-point algorithm as Reference Model (RM) is applicable.

Disclosure of Invention

The disclosure provides a chip verification method and device and a storage medium.

According to a first aspect of embodiments of the present disclosure, there is provided a chip verification method, the method including: compiling a neural network model corresponding to the SDK plug-in of the software development kit through a tool chain to obtain a first executable file; running an environment model corresponding to the SDK plug-in to obtain first golden data; running the first executable file through a reference model corresponding to the SDK plug-in to obtain a first execution result, wherein the reference model is used for simulating a hardware executable program of a simulation simulator corresponding to the chip to be tested; and verifying the reference model corresponding to the SDK plug-in based on the first golden data and the first execution result.

In some optional embodiments, further comprising: and the reference model verifies the simulation simulator corresponding to the chip to be tested on the basis of the first golden data and the first executable file provided by the environment model.

In some optional embodiments, the number of the SDK plug-ins is one or more, and the neural network model corresponding to each SDK plug-in includes at least one of: the device comprises a neural network for realizing the function of an SDK plug-in, a first processing module for preprocessing the input of the neural network and a second processing module for post-processing the output of the neural network.

In some optional embodiments, the number of the SDK plug-ins is plural, and further includes: in response to the verification of the reference model corresponding to each SDK plugin, sequentially connecting the SDK plugins, wherein the output of the reference model corresponding to the SDK plugin with the previous connection sequence is used as the input of the reference model corresponding to the next SDK plugin with the subsequent connection sequence; the pre-extracted target feature information is used as the input of the reference model corresponding to the first SDK plug-in unit, and a second execution result output by the reference model corresponding to the second SDK plug-in unit is obtained; wherein the first SDK plugin is a first SDK plugin in the plurality of sequentially connected SDK plugins, and the second SDK plugin is a last SDK plugin in the plurality of sequentially connected plugins; and verifying the reference model corresponding to each SDK plug-in again based on the second execution result and the target execution result.

In some optional embodiments, further comprising: and taking the target characteristic information as the input of a target neural network model, and operating the target neural network model on a central processing unit to obtain the target execution result, wherein the target neural network is the neural network model obtained after the neural network models corresponding to the plurality of SDK plug-ins are sequentially connected.

In some optional embodiments, the target feature information includes at least one of face feature information and human feature information included in a scene image processed by a visual task.

In some optional embodiments, further comprising: after the reference model corresponding to each SDK plug-in unit is verified to be correct again, second golden data corresponding to the plurality of SDK plug-in units connected in sequence are obtained; and verifying the simulator corresponding to the chip to be tested based on the second golden data.

In some optional embodiments, the neural network model corresponding to the SDK plug-in and the reference model corresponding to the SDK plug-in perform information interaction based on a shared target memory and a socket manner.

In some optional embodiments, further comprising: the neural network model corresponding to the SDK plug-in sends the first executable file to the reference model corresponding to the SDK plug-in; and the reference model corresponding to the SDK plug-in receives the first executable file through a corresponding preset virtual Micro Control Unit (MCU).

In some optional embodiments, a process of the neural network model corresponding to the SDK plug-in has a first mapping address mapped randomly in a shared dynamic random access memory, and the preset virtual MCU process corresponding to the reference model corresponding to the SDK plug-in reads data from a second mapping address in the shared dynamic random access memory; wherein the first mapped address is different from the second mapped address.

According to a second aspect of the embodiments of the present disclosure, there is provided a chip verification apparatus, including: the compiling module is used for compiling the neural network model corresponding to the SDK plug-in of the software development kit through the tool chain to obtain a first executable file; the first operation module is used for operating the environment model corresponding to the SDK plug-in unit to obtain first golden data; the second running module is used for running the first executable file through a reference model corresponding to the SDK plug-in to obtain a first execution result, and the reference model is used for simulating a hardware executable program of a simulation simulator corresponding to the chip to be tested; and the first verification module is used for verifying the reference model corresponding to the SDK plug-in based on the first golden data and the first execution result.

In some optional embodiments, further comprising: and the second verification module is used for verifying the simulation simulator corresponding to the chip to be tested by the reference model based on the first golden data and the first executable file provided by the environment model.

In some optional embodiments, the number of the SDK plug-ins is one or more, and the neural network model corresponding to each SDK plug-in includes at least one of: the device comprises a neural network for realizing the function of an SDK plug-in, a first processing module for preprocessing the input of the neural network and a second processing module for post-processing the output of the neural network.

In some optional embodiments, the apparatus further comprises: the connection module is used for responding to the verification of the reference model corresponding to each SDK plugin correctly and connecting the SDK plugins in sequence, wherein the output of the reference model corresponding to the SDK plugin with the previous connection sequence is used as the input of the reference model corresponding to the next SDK plugin connected in sequence; the third operation module is used for taking the pre-extracted target characteristic information as the input of the reference model corresponding to the first SDK plug-in unit to obtain a second execution result output by the reference model corresponding to the second SDK plug-in unit; wherein the first SDK plugin is a first SDK plugin in the plurality of sequentially connected SDK plugins, and the second SDK plugin is a last SDK plugin in the plurality of sequentially connected plugins; and the third verification module is used for verifying the reference model corresponding to each SDK plug-in again based on the second execution result and the target execution result.

In some optional embodiments, the apparatus further comprises: and the fourth operation module is used for taking the target characteristic information as the input of a target neural network model, operating the target neural network model on a central processing unit and obtaining the target execution result, wherein the target neural network is the neural network model obtained after the neural network models corresponding to the plurality of SDK plug-ins are sequentially connected.

In some optional embodiments, the target feature information includes at least one of face feature information and human feature information included in a scene image processed by a visual task.

In some optional embodiments, the apparatus further comprises: the acquisition module is used for acquiring second golden data corresponding to the plurality of sequentially connected SDK plug-ins after the reference model corresponding to each SDK plug-in is verified to be correct again; and the fourth verification module is used for verifying the simulator corresponding to the chip to be tested based on the second golden data.

In some optional embodiments, the neural network model corresponding to the SDK plug-in and the reference model corresponding to the SDK plug-in perform information interaction based on a shared target memory and a socket manner.

In some optional embodiments, the apparatus further comprises: the sending module is used for sending the first executable file to the reference model corresponding to the SDK plugin by the neural network model corresponding to the SDK plugin; and the receiving module is used for receiving the first executable file by the reference model corresponding to the SDK plug-in unit through a corresponding preset virtual Micro Control Unit (MCU).

In some optional embodiments, a process of the neural network model corresponding to the SDK plug-in has a first mapping address mapped randomly in a shared dynamic random access memory, and the preset virtual MCU process corresponding to the reference model corresponding to the SDK plug-in reads data from a second mapping address in the shared dynamic random access memory; wherein the first mapped address is different from the second mapped address.

According to a third aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium storing a computer program for executing the chip verification method according to any one of the first aspect.

According to a fourth aspect of the embodiments of the present disclosure, there is provided a chip verification apparatus, including: a processor; a memory for storing the processor-executable instructions; wherein the processor is configured to invoke executable instructions stored in the memory to implement the chip verification method of any of the first aspect.

The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:

in the embodiment of the disclosure, the neural network model corresponding to the SDK plug-in may be compiled through a tool chain to obtain a first executable file, then the first executable file is run through the environment model corresponding to the SDK plug-in to obtain first golden data, and the first executable file is run through the reference model corresponding to the SDK plug-in to obtain a first execution result. Thereby verifying the reference model corresponding to the SDK plug-in based on the first golden data and the first execution result. The method and the device introduce the programming capability of the tool chain in the generation process of the gold data, and improve the generation speed of the gold data by combining the verification process, thereby matching the verification speed of chip verification. Meanwhile, the SDK plug-in with high relevance to the scene is introduced, so that missing verification in the verification process of the artificial intelligent AI chip can be reduced, the correctness of chip verification is ensured, and the usability is higher.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a flow diagram illustrating a method for chip verification according to an exemplary embodiment of the present disclosure;

FIG. 2 is a flow diagram illustrating a method for chip verification according to an exemplary embodiment of the present disclosure;

FIG. 3 is a schematic diagram illustrating a chip verification scenario according to an exemplary embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another chip verification scenario illustrated by the present disclosure in accordance with an exemplary embodiment;

FIG. 5 is a flow chart of another method of chip verification shown in accordance with an exemplary embodiment of the present disclosure;

FIG. 6 is a flow diagram illustrating another method of chip verification according to an exemplary embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating a chip verification scenario according to an exemplary embodiment of the present disclosure;

FIG. 8 is a flow chart illustrating another method of chip verification according to an exemplary embodiment of the present disclosure;

FIG. 9 is a block diagram of a chip verification apparatus according to an exemplary embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a chip verification apparatus according to an exemplary embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as operated herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if," as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination," depending on the context.

The embodiment of the disclosure provides a chip verification scheme, which can be used for an artificial intelligence chip, and the chip can perform deep learning through a neural network, so that the chip can be suitable for various scenes needing visual task processing, such as scenes for comparing human faces in smart cities and scenes for detecting intelligent escape behaviors, such as security inspection ports of bus stations or railway stations, and can perform reasoning by combining acquired scene images, thereby obtaining a processing result corresponding to a visual analysis task.

At present, verification is generally not performed by combining a Software Development Kit (SDK) in the verification process of an artificial intelligent chip, and the SDK bears the link between upper-layer services and bottom-layer hardware and contains rich scene information, so that the relevance between the verification and the scene of the current artificial intelligent chip is small, verification leakage is easy to occur in the verification link, and the generation speed of gold (Golden) data in the verification process cannot keep pace with the verification speed of the chip. Golden data is data output by a key node in a chip verification process, and whether the design of an emulator simulator corresponding to a chip to be tested, such as a Register Transfer Level (RTL), is correct or which node has a problem can be determined according to the data, so that the accuracy and the efficiency of chip verification are improved.

In order to solve the above problem, embodiments of the present disclosure provide a chip verification scheme, which can increase the speed of generating gold data, and combine the chip verification process with a scene, thereby reducing or even avoiding the situation of missing verification.

For example, as shown in fig. 1, fig. 1 is a chip verification method according to an exemplary embodiment, which may be used in a chip verification platform, and includes the following steps:

in step 101, a neural network model corresponding to an SDK plug-in of a software development kit is compiled through a tool chain to obtain a first executable file.

In the embodiment of the present disclosure, the chip to be verified may be an AI chip. The SDK includes, but is not limited to, a collection of development tools when creating application software, software packages, software frameworks, hardware platforms, operating systems, and the like. The SDK undertakes the connection between the upper application service and the bottom hardware, including a large amount of application scene information. The SDK may provide different plug-ins, which refer to programs written by the application program interface. The SDK plug-in the disclosure is a program which can realize different scene functions and is provided by the SDK.

In the embodiment of the disclosure, in order to introduce the SDK plug-in the chip verification link, the neural network model corresponding to the SDK plug-in may be compiled to obtain the first executable file. The functions required by the corresponding SDK plug-ins can be realized through the deep learning neural network model. In one example, the neural network model corresponding to the SDK plug-in may be compiled through a tool chain (toolchain), where the toolchain includes, but is not limited to, a set of tools and related libraries used in the whole process, such as an assembly tool, a compiler, and a standard programming function library, and the toolchain may compile and link the neural network model into an executable file, where the executable file is a file that may be directly loaded and run by an operating system.

In the embodiment of the present disclosure, a first executable file may be obtained by compiling the neural network model corresponding to the SDK plug-in through a tool chain, where the first executable file includes, but is not limited to, an executable instruction stream, network parameters of the neural network model, and the like.

In step 102, the environment model corresponding to the SDK plug-in is run to obtain first fund data.

In the embodiment of the present disclosure, the environment model is a model for simulating an algorithm environment of a neural network model corresponding to the SDK plug-in. The algorithm environment refers to a computer program corresponding to an algorithm for implementing the neural network model, and the algorithm environment can be implemented by deploying an algorithm chip (algo _ IC) of the corresponding computer program. And obtaining first golden data by operating the environment model, wherein the first golden data comprises actual result data obtained by operating the neural network model corresponding to the SDK plug-in.

For example, the SDK scene is a subway fare evasion detection scene, wherein a neural network model corresponding to one SDK plug-in is used for matching key parts of a human body with key parts of a human face, and in this scene, the environment model may be a model of an algorithm environment of the neural network model for simulating a matching process of the key parts of the human body with the key parts of the human face, and the first gold data obtained by operating the environment model includes actual matching results of the key parts of the human body and the key parts of the human face, where a human body frame actually belonging to the same human body is identical to a character identifier corresponding to the human face frame.

In step 103, the first executable file is run through the reference model corresponding to the SDK plug-in, so as to obtain a first execution result.

In the embodiment of the present disclosure, the Reference Model (RM) corresponding to the SDK plug-in is an executable program for simulating hardware of the simulator corresponding to the chip to be tested, and may be written in advance through a computer language. And taking the instruction stream included in the first executable file as the input of the reference model, and operating the reference model to obtain a first execution result. The first execution result comprises result data to be verified, which is obtained when the instruction stream included in the first executable file is executed based on the RTL hardware executable program. For example, the method is also a subway fare evasion detection scene, and the first execution result includes a matching result to be verified of a human key part and a human face key part.

In step 104, the reference model corresponding to the SDK plugin is verified based on the first golden data and the first execution result.

In the embodiment of the present disclosure, the first golden data obtained through the environment model is actual result data obtained by operating the neural network model corresponding to the SDK plug-in, and the first execution result obtained by operating the reference model may be verified through the first golden data. If the first golden data is matched with result data to be verified, which is included in the first execution result, verification of the reference model corresponding to the SDK plug-in can be determined to be successful.

In the embodiment, the reference models corresponding to different SDK plug-ins can be verified respectively, and due to the introduction of the SDK plug-in with high relevance to the scene, missing verification in the chip verification process can be reduced, the correctness of chip verification is ensured, and the usability is higher.

In some alternative embodiments, such as shown in fig. 2, the method may further include:

in step 105, the reference model verifies the simulator corresponding to the chip to be tested based on the first golden data and the first executable file provided by the environment model.

In the embodiment of the present disclosure, the final purpose of chip verification is to verify an emulator simulator corresponding to a chip to be tested, where the emulator simulator refers to a simulation device based on a high-speed processor or a field programmable gate array. The functions and timing of the chip described in the register transfer level may be emulated and inserted into the system to replace the chip under development, facilitating debugging and verification of the chip and system. In embodiments of the present disclosure, the reference model may verify the simulation simulator, e.g., the RTL, based on the first golden data and the first executable file provided by the environmental model. Wherein the reference model may input the instruction stream included in the first executable file into the simulator, and if the result data included in the result of the simulator operation matches the first golden data, it may be determined that the simulator is verified correctly.

In the embodiment, the reference model may further verify the simulator based on the first golden data and the first executable file provided by the environment model, and because the SDK plug-in associated with the scene is introduced in the verification process of the reference model, the reliability of verifying the simulator is improved.

In some alternative embodiments, in the case that toolchain is not introduced to compile program code corresponding to the plug-in, the verification manner is as shown in fig. 3.

Comparing the golden data output by the environment model with the data included in the output result of the RTL simulator, and if the golden data and the data are consistent, determining that the RLT simulator is designed correctly. In the whole verification process, whether the golden data output by the environment model is consistent with the data to be verified in the output result of the reference model can be compared to verify the reference model. In the verification process, in the process of verifying the RTL, the relevance between the RTL and the reference model is less, so that the importance of the reference model in the whole chip verification process is relatively lower.

In the embodiment of the present disclosure, in the verification process, for example, as shown in fig. 4, after the neural network model corresponding to the SDK plug-in is compiled by the tool chain, a first executable file is obtained, an instruction stream included in the first executable file is used as an input of the reference model, and the reference model is run to obtain a first execution result. And operating the environment model corresponding to the SDK plug-in to obtain first golden data. And comparing the first golden data with the data to be verified included in the first execution result so as to verify the reference model. In addition, more accurate gold data may also be generated by adjusting the model parameters of the reference model.

Compiling the neural network model corresponding to the SDK plug-in through the tool chain to obtain a first executable file, where the first executable file includes information such as an executable instruction and network parameters of the neural network model, and the first executable file may be used as an input of a reference model and a simulation simulator, for example, an RTL simulator. In addition, the reference model can also provide result data obtained when the simulation simulator runs to the environment model and the tool chain in the process of verifying the reference model and the simulation simulator. Because a closed-loop channel can be formed among the environment model, the tool chain and the reference model, the generation process of the first golden data forms a closed loop.

In addition, the reference model can verify the RTL based on the first golden data provided by the environment model and the first executable file, and the RTL provides the required environment parameters for the reference model again after being adjusted based on the first golden data. And the reference model verifies the RTL again based on the re-determined environmental parameters, so that the closed-loop verification of the RTL is realized.

In the embodiment, a closed loop for generating the gold data and a closed loop for verifying the RTL are formed, and the importance of the reference model in the RLT verification process is highlighted, so that the accuracy of the finally obtained gold data is higher, and the accuracy of RTL design is improved.

In some optional embodiments, the number of SDK plug-ins is one or more, and the neural network model corresponding to each SDK may include, but is not limited to, at least one of: the device comprises a neural network for realizing the function of an SDK plug-in, a first processing module for preprocessing the input of the neural network and a second processing module for post-processing the output of the neural network.

Each SDK plug-in may consist of at least one independent neural Network that may employ, but is not limited to, google Network (google net), Visual Geometry Group Network (VGG) Network, or residual error Network (resource) as a backbone Network.

Each SDK plug-in may also include a first processing module that preprocesses inputs to the at least one neural network, where the preprocessing includes, but is not limited to, cropping, resizing (resize), etc. of the image.

Each plug-in may further comprise a second processing module for post-processing the output of the at least one neural network, wherein the post-processing includes, but is not limited to, filtering of the output results to obtain desired task processing results, and the like.

In the embodiment, through carrying out preprocessing and/or post-processing on the neural network, missing verification is avoided, and the accuracy of chip verification is improved.

In some optional embodiments, if the number of included plug-ins of the SDK is multiple, accordingly, for example, as shown in fig. 5, the method may further include:

in step 106, in response to the reference model corresponding to each SDK plug-in verifying correctly, a plurality of SDK plug-ins are connected sequentially.

In the embodiment of the present disclosure, it may be verified whether the reference model corresponding to each plugin is correct or not in the manner of the previous steps 101 to 104, and in a case that the reference model corresponding to each SDK plugin is correct, a plurality of SDK plugins may be sequentially connected.

In one example, a plurality of plug-ins connected in sequence constitute a pipeline (pipeline). And connecting the output of the reference model corresponding to the SDK plug-in the front of the sequence as the input of the reference model corresponding to the SDK plug-in the back of the sequence connection.

In step 107, the pre-extracted target feature information is used as the input of the reference model corresponding to the first SDK plugin, and a second execution result output by the reference model corresponding to the second SDK plugin is obtained.

In an embodiment of the present disclosure, the first SDK plug-in is a first SDK plug-in of a plurality of sequentially connected SDK plug-ins, and the second plug-in is a last SDK plug-in of the plurality of sequentially connected SDK plug-ins. And finally, obtaining a second execution result output by the reference model corresponding to the last second SDK plug-in unit through pipeline.

The target feature information is determined based on the application scene corresponding to the SDK, and includes but is not limited to at least one of face feature information and human body feature information included in a scene image corresponding to the at least one visual processing task. For example, in a subway ticket evasion detection scene, the target feature information includes face feature information and human key point feature information.

In step 108, the reference model corresponding to each SDK plugin is verified again based on the second execution result and the target execution result.

In the disclosed embodiment, the target execution result is a final execution result that is expected when the sequentially connected plurality of SDK plug-ins execute the visual processing task. If the second execution result output by the reference model corresponding to the second SDK plugin matches the target execution result, the verification result of verifying the reference model corresponding to each SDK plugin can be determined to be correct again.

In the above embodiment, the plurality of SDK plug-ins may be sequentially connected, and any second execution result and target execution result output based on the reference model corresponding to the last second SDK plug-in the plurality of sequentially connected SDK plug-ins may be re-verified for the reference model corresponding to each SDK plug-in, thereby further avoiding missing verification and achieving system-level chip verification.

In some alternative embodiments, such as shown in fig. 6, the method may further include:

in step 100, the target feature information is used as an input of a target neural network model, and the target neural network model is run on a central processing unit to obtain the target execution result.

In the embodiment of the present disclosure, the target feature information may be used as an input of a target neural network model, and the target neural network model is run on a Central Processing Unit (CPU), so as to obtain a target execution result output by the target neural network model. The CPU is a hardware device, may be a CPU of the chip verification platform, or may be a CPU of another device, which is not limited in this disclosure. The target neural network model is obtained by sequentially connecting the neural network models respectively corresponding to the plurality of SDK plug-ins. The target execution result is a final execution result that is desired when running multiple SDK plug-ins that are sequentially connected to perform the visual processing task.

In an example, the process of obtaining the target execution result further includes preprocessing an input of the neural network corresponding to each SDK plug-in, and/or post-processing an output of the neural network included in each SDK plug-in. The preprocessing includes, but is not limited to, cropping, resize, etc. of the image, and the post-processing includes, but is not limited to, filtering the output result to obtain the required task processing result, etc.

In the above embodiment, the target neural network model may be run on the central processing unit to obtain the target execution result, so that the reference model corresponding to each SDK plug-in is verified again in the following process, and the reliability is high. When the hardware environment of the chip is changed, the actual hardware environment does not need to be changed, the chip verification can be quickly completed by adjusting the reference model, the cost of the chip verification is reduced, and the efficiency of the chip verification is improved.

In one example, second Golden data corresponding to the plurality of sequentially connected SDK plug-ins can be obtained when the reference model corresponding to each SDK plug-in is verified again and the verification result is correct, and the second Golden data is Golden data in a full scene. In this disclosure, the second golden data is data obtained from a key point of the full scene after the reference model corresponding to each SDK plugin is re-verified based on the second execution result and the target execution result, and may include intermediate result data obtained by a part of the computer program specified in the reference model when the reference models corresponding to a plurality of sequentially connected SDK plugins are run, and may further include final result data output by the reference model corresponding to the last SDK plugin connected in sequence, where the final result data output by the reference model corresponding to the last SDK plugin should match with the result data included in the target execution result.

Further, the design of the RTL can be re-verified based on the second golden data for the full scene.

In the embodiment, Golden data required by the whole scene can be obtained, and the RTL design is verified again based on the Golden data of the whole scene, so that the accuracy of the RTL design is improved.

In some alternative embodiments, the chip verification process introduced in the above scheme is explained again as follows:

for example, as shown in fig. 7, only 6 SDK plug-ins are exemplified in fig. 7, and the number of SDK plug-ins in actual application may be set as needed. The chip verification process provided by the present disclosure may include the following several stages:

in the first stage, target characteristic information is used as the input of a target neural network model, and the target neural network model is operated on a central processing unit to obtain a target execution result.

The CPU is a hardware device, including but not limited to the CPU of the chip verification platform. The target characteristic information may be used as an input of a target neural network model, and the target neural network is obtained by sequentially connecting the neural network models corresponding to the plurality of SDK plug-ins.

For example, the face feature information included in the scene image processed by the visual task is used as input, and the target execution result is obtained. Wherein the neural network model corresponding to each SDK plug-in comprises at least one of the following items: the device comprises a neural network for realizing the function of an SDK plug-in, a first processing module for preprocessing the input of the neural network and a second processing module for post-processing the output of the neural network.

Taking an intelligent escape behavior detection scene of a subway station as an example, the target characteristic information is a subway station scene image included in a video stream acquired by at least one camera in the subway station, a target neural network model is operated on a CPU (central processing unit) to obtain a target execution result, and whether the design of the SDK plug-in meets the design requirement or not can be determined according to the target execution result. In one example, the SDK plugin may be determined to meet design requirements if the accuracy of the target execution result exceeds a preset value. For example, the SDK scene is a subway ticket evasion detection scene, and the multiple SDK plug-ins are designed for face key point detection, human body key point detection, matching of the face key points and the human body key points, distance detection between any two living bodies, ticket evasion action detection, ticket evasion result verification and the like. And under the condition that the ticket evasion result verification success rate exceeds a preset value, determining that the SDK plug-in meets the design requirement.

And in the second stage, the CPU operation process in the first stage can be replaced by the environment model, the reference model and the toolchain, the reference model corresponding to each SDK plug-in unit is verified, and the simulation simulator corresponding to the chip to be tested is verified by the reference model based on the first golden data and the first executable file provided by the environment model.

And compiling the neural network model corresponding to each SDK plug-in by toolchain to obtain a first executable file. And inputting the instruction stream included in the first executable file into the reference model corresponding to the SDK plug-in to obtain a first execution result, and operating the environment model corresponding to the SDK plug-in to obtain first golden data.

And if the first golden data is matched with the data included in the first execution result, determining that the verification result of the reference model corresponding to the single SDK plug-in unit for verification is correct.

At this stage, the design of the simulation simulator may also be verified by the reference model based on the first golden data provided by the environmental model and the first executable file described above. The verification process is consistent with the verification process provided in the above embodiments, and is not described herein again.

And in the third stage, after the plurality of SDK plug-ins are connected in sequence, verifying the reference model corresponding to each SDK plug-in again.

In the embodiment of the disclosure, a plurality of sequentially connected SDK plug-ins form pipeline, and the target feature information is used as an input of a reference model corresponding to a first SDK plug-in, that is, a first SDK plug-in, of the plurality of SDK plug-ins, and finally a second execution result output by a reference model corresponding to a last SDK plug-in, that is, a second SDK plug-in, of the plurality of SDK plug-ins is obtained.

If the second execution result output by the second SDK plug-in unit is matched with the target execution result obtained in the first stage, for example, the second execution result also realizes the detection of the fare evasion behavior, and the content of the detection result is consistent with that of the target execution result, the verification result of verifying the reference model corresponding to each SDK plug-in unit again is correct.

At this stage, time monitoring may also be added, for example, a clock is set in a reference model corresponding to the at least one SDK plug-in, and a finally obtained second execution result may provide corresponding time information when the at least one SDK plug-in operates, so as to perform better chip verification.

And a fourth stage of acquiring second golden data and verifying the simulator again based on the second golden data.

In the embodiment of the disclosure, second Golden data can be printed, wherein the second Golden data is extracted based on key positions of a plurality of sequentially connected SDK plug-ins after the reference model corresponding to each SDK plug-in is verified to be correct again, that is, the second Golden data is Golden data of a whole scene. The key location may be determined according to a specific scenario, including but not limited to a designated file location of an executable file corresponding to the target neural network model.

The reference model may again be validated against the simulator based on the second golden data. If the result data included in the simulation simulator operation result matches the second golden data, it can be determined that the simulation simulator is correctly verified.

In the embodiment, the Golden data generation speed in the chip verification process is increased, the Golden data based on bit matching can be obtained, the chip verification link can be combined with a scene, the missing verification is avoided, and the accuracy of the chip verification is improved.

In some alternative embodiments, the current AI chip verification process, since it does not involve verification related to the SDK, there is no interaction of the SDK with the reference model. In the embodiment of the disclosure, because the SDK is introduced in the AI chip verification process, the interaction between the neural network model corresponding to the SDK plug-in and the reference model is also involved.

In the embodiment of the present disclosure, because the neural network model corresponding to the SDK plug-in needs to send the first executable file to the reference model corresponding to the SDK plug-in, the neural network model and the reference model may interact in a shared memory and/or a socket manner, the shared memory is a target memory, and the sent first executable file includes, but is not limited to, a network parameter in the neural network model corresponding to the SDK plug-in, an executable instruction stream, and the like, where the instruction stream includes at least one control instruction, and can control the reference model to execute a corresponding operation. In one example, the SDK plug-in may perform memory allocation on the shared target memory through a memory management mechanism.

In the above embodiment, the neural network model corresponding to the SDK plug-in and the reference model corresponding to the SDK plug-in may perform information interaction in a manner of sharing a memory and a Socket, and have high usability.

In some alternative embodiments, such as shown in fig. 8, the method may further include:

in step 109, the neural network model corresponding to the SDK plug-in sends a first executable file to the reference model corresponding to the SDK plug-in.

After the neural network model corresponding to the SDK plug-in is compiled by the tool chain to obtain the first executable file, the obtained first executable file may be sent to the reference model corresponding to the SDK plug-in by the neural network model corresponding to the SDK plug-in. Wherein the first executable file includes, but is not limited to, at least one of: network parameters of the neural network model, executable instruction streams. The at least one network parameter includes, but is not limited to, a character lookup (instr) field, an instr field instruction length, a parameter tensor, and other parameters in the neural network model. The executable instruction stream comprises at least one control instruction, and the control instruction at least comprises an exit control instruction, namely the neural network model corresponding to the SDK plug-in can send the exit control instruction to the reference model after the execution of the reference model is finished to obtain a corresponding execution result. In one example, the neural network model corresponding to the SDK plug-in may send the first executable file to the reference model through a Socket and a shared memory.

In step 110, the reference model receives the first executable file through a corresponding default virtual micro control unit MCU.

In the embodiment of the present disclosure, a corresponding preset virtual Micro Control Unit (MCU) may be configured for a reference model, and the reference model performs instruction distribution and/or reception through the preset virtual MCU. The preset virtual MCU may be a micro control unit written by a computer program of software for implementing a hardware MCU function. The reference model receives a first executable file through the preset virtual MCU.

In one example, the shared target memory may be called by the pre-virtual MCU, and the first executable file sent by the neural network model corresponding to the SDK plug-in may be received.

In the case where the control instruction includes an exit control instruction, the reference model may perform an exit operation.

In the above embodiment, the neural network model corresponding to the SDK plug-in may send the first executable file to the reference model, and the reference model is received through the preset virtual MCU, so that the usability is high.

In some optional embodiments, the neural network model corresponding to the SDK plug-in and the corresponding reference model may perform inter-process communication by using a socket (socket), which includes but is not limited to unix socket. The specific data structure can take each neural network in at least one neural network included in the neural network model corresponding to the SDK plug-in as an independent task, and divide each task into a plurality of steps according to the execution sequence of the neural network, so that the preset virtual MCU executes the plurality of steps sequentially.

In some optional embodiments, the neural network model corresponding to the SDK plug-in and the reference model corresponding to the SDK plug-in may perform information interaction in a manner of a shared dynamic random access memory (DDR), where the dynamic random access memory includes, but is not limited to, a Double Data Rate (DDR).

In view of the fact that it is easy for a process of the neural network model corresponding to the SDK plug-in and a process of the preset virtual MCU corresponding to the reference model to map the shared memory to the same virtual address to fail, in the embodiment of the present disclosure, a random mapping manner may be adopted to map the process of the neural network model corresponding to the SDK and the process of the preset virtual MCU corresponding to the reference model to the local process address space. For example, when the process of the neural network model corresponding to the SDK plug-in maps the shared memory address to a first mapping address of the local process, and the process of the preset virtual MCU corresponding to the reference model maps the shared memory address to a second mapping address of the local process, the first mapping address may be different from the second mapping address, and when the process of the neural network model corresponding to the SDK plug-in and the process of the preset virtual MCU transfer the shared memory address, correspondingly, the process of the reference model corresponding to the SDK plug-in cannot provide a generated Direct Memory Access (DMA) mapping instruction, and the process of the MCU process needs to be preset to generate a mapping instruction for the reference model corresponding to the SDK plug-in according to the offset and the related information corresponding to the SDK plug-in, so that the reference model can read data from the second mapping address.

In the above embodiment, when the SDK plug-in and the corresponding reference model perform information interaction in a shared memory manner, a first mapping address randomly mapped exists in a target memory in a process of the neural network model corresponding to the SDK plug-in, a second mapping address in the target memory is read by a process of the preset virtual MCU corresponding to the reference model, where the first mapping address is different from the second mapping address, and a mapping instruction can be generated by the process of the preset MCU, so that a problem that the SDK plug-in and the reference model cannot interact due to the fact that the SDK plug-in and the reference model cannot be mapped to the same mapping address is avoided.

Corresponding to the foregoing method embodiments, the present disclosure also provides embodiments of an apparatus.

As shown in fig. 9, fig. 9 is a block diagram of a chip verification apparatus according to an exemplary embodiment of the present disclosure, the apparatus including:

the compiling module 210 is configured to compile a neural network model corresponding to the software development kit SDK plug-in through a tool chain to obtain a first executable file;

the first running module 220 is configured to run the environment model corresponding to the SDK plug-in to obtain first golden data;

a second running module 230, configured to run the first executable file through a reference model corresponding to the SDK plug-in to obtain a first execution result, where the reference model is used to simulate a hardware executable program of a simulation simulator corresponding to the chip to be tested;

a first verification module 240, configured to verify the reference model corresponding to the SDK plugin based on the first golden data and the first execution result.

In some optional embodiments, further comprising: and the second verification module is used for verifying the simulation simulator corresponding to the chip to be tested by the reference model based on the first golden data and the first executable file provided by the environment model.

In some optional embodiments, the number of the SDK plug-ins is one or more, and the neural network model corresponding to each SDK plug-in includes at least one of: the device comprises a neural network for realizing the function of an SDK plug-in, a first processing module for preprocessing the input of the neural network and a second processing module for post-processing the output of the neural network.

In some optional embodiments, the apparatus further comprises: the connection module is used for responding to the verification of the reference model corresponding to each SDK plugin correctly and connecting the SDK plugins in sequence, wherein the output of the reference model corresponding to the SDK plugin with the previous connection sequence is used as the input of the reference model corresponding to the next SDK plugin connected in sequence; the third operation module is used for taking the pre-extracted target characteristic information as the input of the reference model corresponding to the first SDK plug-in unit to obtain a second execution result output by the reference model corresponding to the second SDK plug-in unit; wherein the first SDK plugin is a first SDK plugin in the plurality of sequentially connected SDK plugins, and the second SDK plugin is a last SDK plugin in the plurality of sequentially connected plugins; and the third verification module is used for verifying the reference model corresponding to each SDK plug-in again based on the second execution result and the target execution result.

In some optional embodiments, the apparatus further comprises: and the fourth operation module is used for taking the target characteristic information as the input of a target neural network model, operating the target neural network model on a central processing unit and obtaining the target execution result, wherein the target neural network is the neural network model obtained after the neural network models corresponding to the plurality of SDK plug-ins are sequentially connected.

In some optional embodiments, the target feature information includes at least one of face feature information and human feature information included in a scene image processed by a visual task.

In some optional embodiments, the apparatus further comprises: the acquisition module is used for acquiring second golden data corresponding to the plurality of sequentially connected SDK plug-ins after the reference model corresponding to each SDK plug-in is verified to be correct again; and the fourth verification module is used for verifying the simulator corresponding to the chip to be tested based on the second golden data.

In some optional embodiments, the neural network model corresponding to the SDK plug-in and the reference model corresponding to the SDK plug-in perform information interaction based on a shared target memory and a socket manner.

In some optional embodiments, the apparatus further comprises: the sending module is used for sending the first executable file to the reference model corresponding to the SDK plugin by the neural network model corresponding to the SDK plugin; and the receiving module is used for receiving the first executable file by the reference model corresponding to the SDK plug-in unit through a corresponding preset virtual Micro Control Unit (MCU).

In some optional embodiments, a process of the neural network model corresponding to the SDK plug-in has a first mapping address mapped randomly in a shared dynamic random access memory, and the preset virtual MCU process corresponding to the reference model corresponding to the SDK plug-in reads data from a second mapping address in the shared dynamic random access memory; wherein the first mapped address is different from the second mapped address.

For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the disclosed solution. One of ordinary skill in the art can understand and implement it without inventive effort.

An embodiment of the present disclosure further provides a computer-readable storage medium, where a computer program is stored, and the computer program is used to execute any one of the chip verification methods described above.

In some optional embodiments, the disclosed embodiments provide a computer program product comprising computer readable code which, when run on a device, a processor in the device executes instructions for implementing a chip verification method as provided in any of the above embodiments.

In some optional embodiments, the present disclosure further provides another computer program product for storing computer readable instructions, which when executed, cause a computer to execute the chip verification method provided in any one of the above embodiments.

The computer program product may be embodied in hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK), or the like.

The embodiment of the present disclosure further provides a chip verification apparatus, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to call executable instructions stored in the memory to implement any one of the above chip verification methods.

Fig. 10 is a schematic diagram of a hardware structure of a chip verification apparatus according to an embodiment of the present disclosure. The object detection device 310 includes a processor 311 and may further include an input device 312, an output device 313, and a memory 314. The input device 312, the output device 313, the memory 314, and the processor 311 are connected to each other via a bus.

The memory includes, but is not limited to, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a portable read-only memory (CD-ROM), which is used for storing instructions and data.

The input means are for inputting data and/or signals and the output means are for outputting data and/or signals. The output means and the input means may be separate devices or may be an integral device.

The processor may include one or more processors, for example, one or more Central Processing Units (CPUs), and in the case of one CPU, the CPU may be a single-core CPU or a multi-core CPU.

The memory is used to store program codes and data of the network device.

The processor is used for calling the program codes and data in the memory and executing the steps in the method embodiment. Specifically, reference may be made to the description of the method embodiment, which is not repeated herein.

It will be appreciated that fig. 10 shows only a simplified design of a chip verification device. In practical applications, the chip verification apparatuses may further include other necessary components, including but not limited to any number of input/output apparatuses, processors, controllers, memories, etc., and all chip verification apparatuses that can implement the embodiments of the disclosure are within the scope of the disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

The above description is only exemplary of the present disclosure and should not be taken as limiting the disclosure, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.