1. The simulation method for simulating the quantum logic gate by using the analog circuit is characterized in that the simulation method is realized based on the quantum logic gate consisting of the analog circuit, and the realization mode of the simulation method is as follows:

will signalSum signalAs two input signals of a quantum logic gate, a pair of signals through the quantum logic gateSum signalPerforming unitary transformation in two-dimensional Hilbert space to simulate two output signals of the quantum logic gateAndwherein the content of the first and second substances,representing a qubit |0>Probability amplitude phasor of the state before conversion;representing a qubit |1>Probability amplitude phasor of the state before conversion;representing a qubit |0>The probability amplitude phasor of the state after transformation,representing a qubit |1>Probability amplitude phasor of the state after transformation;

two output signals of the quantum logic gateAndrespectively with input signalsSum signalCorresponding; and satisfies the following relationship:

wherein the content of the first and second substances,and satisfies the following conditions:rho is a constant;

ω is the angular frequency, t is time,is a sinusoidal voltage x₀The initial phase of (a) is determined,is a sinusoidal voltage x₁Initial phase of (X)₀Is a sinusoidal voltage x₀Amplitude of (A), X₁Is a sinusoidal voltage x₁The amplitude of (c).

2. Method for simulating a quantum logic gate by an analog circuit according to claim 1, wherein the quantum logic gate formed by the analog circuit comprises a gamma phase shift circuit (1), a 90 ° + sigma phase shift circuit (2), a 90 ° -sigma phase shift circuit (3), -a phase shift circuit (4), a first phase shift circuit (4)A voltage divider circuit (5) and a firstA voltage divider circuit (6) and a secondA voltage divider circuit (7) and a secondA voltage division circuit (8), a first signal synthesis circuit (9), a second signal synthesis circuit (10), a first delta phase shift circuit (11) and a second delta phase shift circuit (12);

both the gamma phase shift circuit (1) and the 90-sigma phase shift circuit (3) are used for receiving signals

Both the 90 DEG + sigma phase shift circuit (2) and the-gamma phase shift circuit (4) are used for receiving signals

The output terminal of the gamma phase shift circuit (1) and the firstThe input end of the voltage division circuit (5) is connected with the firstThe output end of the voltage division circuit (5) is connected with the first input end of the first signal synthesis circuit (9);

the output terminal of the 90 DEG + sigma phase shift circuit (2) and the firstThe input end of the voltage division circuit (6) is connected with the firstThe output end of the voltage division circuit (6) is connected with the second input end of the first signal synthesis circuit (9);

the output end of the first signal synthesis circuit (9) is connected with the input end of a first delta phase shift circuit (11), and the output end of the first delta phase shift circuit (11) is used for outputting signals

The output end of the 90-sigma phase shift circuit (3) and the secondThe input end of the voltage division circuit (7) is connected with the secondThe output end of the voltage division circuit (7) is connected with the first input end of the second signal synthesis circuit (10);

-the output of the gamma phase shift circuit (4) and a secondThe input end of the voltage division circuit (8) is connected with the secondThe output of the voltage division circuit (8)The output end of the first signal synthesis circuit is connected with a first input end of a first signal synthesis circuit (10);

the output end of the second signal synthesis circuit (10) is connected with the input end of a second delta phase shift circuit (12), and the output end of the second delta phase shift circuit (12) is used for outputting signals

Wherein, gamma, sigma, theta and delta are all angle variables.

3. The method of claim 1, wherein the signals are simulated by a quantum logic gateSum signalPerforming unitary transformation in two-dimensional Hilbert space to simulate two output signals of the quantum logic gateAndthe implementation mode of the method is as follows:

step one, a gamma phase shift circuit (1) and a 90-sigma phase shift circuit (3) receive signals simultaneouslyThe 90 DEG + sigma phase shift circuit (2) and the-gamma phase shift circuit (4) simultaneously receive signals

Step two, the gamma phase shift circuit (1) is used for receiving the signalsAfter phase shifting by gamma angle, obtainAnd will beIs sent to the firstA voltage dividing circuit (5);

90 DEG + sigma phase shift circuit (2) for receiving signalAfter phase shifting by 90 degrees plus sigma degrees, obtainingAnd will beIs sent to the firstA voltage dividing circuit (6);

90-sigma phase shift circuit (3) for receiving the signalAfter phase shifting by 90-sigma degrees, obtainingAnd will beIs sent to the secondA voltage dividing circuit (7);

-a gamma phase shift circuit (4) for the received signalAfter phase shifting by-gamma angle, obtainAnd will beIs sent to the secondA voltage dividing circuit (8);

step three, firstA voltage divider circuit (5) for outputting to the gamma phase shift circuit (1)Carrying out partial pressure to obtainAnd will beTo a first signal synthesis circuit (9);

first of allA voltage divider circuit (6) for outputting a 90 DEG + sigma phase shift circuit (2)Carrying out partial pressure to obtainAnd will beTo a first signal synthesis circuit (9);

second oneA voltage divider circuit (7) for outputting a 90 DEG-sigma phase shift circuit (3)Carrying out partial pressure to obtainAnd will beTo a second signal synthesis circuit (10);

second oneA voltage divider circuit (8) for outputting to the gamma phase shift circuit (4)Carrying out partial pressure to obtainAnd will beTo a second signal synthesis circuit (10);

step four, a first signal synthesis circuit (9) for receivingAndperforming summation operation to obtainThe result of the summationAnd summing the resultsTo a first delta phase shift circuit (11);

a second signal synthesis circuit (10) for synthesizing the received signalAndsumming to obtain the sum resultAnd summing the resultsTo a second delta phase shift circuit (12);

step five, the first delta phase shift circuit (11) sums the received summation resultsAfter phase shifting by delta angle, obtaining signal

A second delta phase shift circuit (12) sums the received resultsAfter phase shifting by delta angle, obtaining signal

4. The simulation method for simulating a quantum logic gate by using an analog circuit according to claim 2, wherein the gamma phase shift circuit (1), the 90 ° + sigma phase shift circuit (2), the 90 ° -sigma phase shift circuit (3), -the gamma phase shift circuit (4), the first delta phase shift circuit (11) and the second delta phase shift circuit (12) are implemented by using angle phase shift circuits;

the angle phase shift circuit comprises resistors R1-R6, RC phase shift elements Z1-Z4, operational amplifiers U1, U2 and U5;

one end of the RC phase-shifting element Z1 is connected with one end of the resistor R1 and then serves as the input end of the angle phase-shifting circuit;

the other end of the RC phase-shifting element Z1 is connected with the RC phase-shifting element Z2 and the positive input end of an operational amplifier U1, and the other end of the RC phase-shifting element Z2 is connected with the power ground;

the inverting input end of the operational amplifier U1 is simultaneously connected with the other end of the resistor R1 and one end of the resistor R2, the other end of the resistor R2 is connected with the output end of the operational amplifier U1 and then is connected with one end of the RC phase shift element Z3 and one end of the resistor R3, the other end of the RC phase shift element Z3 is simultaneously connected with the RC phase shift element Z4 and the positive input end of the operational amplifier U2, and the other end of the RC phase shift element Z4 is connected with the power ground;

the inverting input end of the operational amplifier U2 is simultaneously connected with the other end of the resistor R3 and one end of the resistor R4, and the other end of the resistor R4 is connected with the output end of the operational amplifier U2 and then connected with the positive input end of the operational amplifier U5; the inverting input end of the operational amplifier U5 is connected with one end of a resistor R5 and one end of a resistor R6 at the same time, the other end of the resistor R5 is connected with a power ground, and the other end of the resistor R6 is connected with the output end of the operational amplifier U5 to serve as the output end of the angle phase shifting circuit;

when Z1 and Z3 are both resistors and Z2 and Z4 are both capacitors, the angle phase-shift circuit can realize negative angle phase shift; when Z1 and Z3 are both capacitors and Z2 and Z4 are both resistors, the angle phase-shift circuit can realize positive angle phase shift;

the resistance values of all resistors in the gamma phase shift circuits (1), 90 degrees + sigma phase shift circuits (2), 90 degrees-sigma phase shift circuits (3) and-gamma phase shift circuits (4) respectively adopted by the gamma phase shift circuits are different, and the capacitance values of all capacitors in the gamma phase shift circuits (1), 90 degrees + sigma phase shift circuits (2), 90 degrees-sigma phase shift circuits (3) and-gamma phase shift circuits (4) respectively adopted by the gamma phase shift circuits (1), 90 degrees + sigma phase shift circuits (2), 90 degrees-sigma phase shift circuits (3) and-gamma phase shift circuits (4) are different;

the first delta phase shift circuit (11) and the second delta phase shift circuit (12) respectively adopt angle phase shift circuits with the same resistance value of the resistor and the same capacitance value of the capacitor.

5. The method of claim 2, wherein the first step comprises simulating a quantum logic gate with the simulation circuitA voltage divider circuit (5) and a firstA voltage divider circuit (6) and a secondA voltage divider circuit (7) and a secondThe voltage division circuits (8) are all realized by adopting voltage division circuit units;

the voltage division circuit unit comprises a resistor R7, a resistor R8 and an operational amplifier U3;

one end of the resistor R7 is used as the input end of the voltage division circuit unit, the other end of the resistor R7 is connected with one end of the resistor R8 and the positive input end of the operational amplifier U3, and the other end of the resistor R8 is connected with the power ground;

the inverting input end of the operational amplifier U3 is connected with the output end of the operational amplifier U3 and then serves as the output end of the voltage division circuit unit;

wherein the content of the first and second substances,

the first isA voltage divider circuit (5) and a secondVoltage divider circuit(8) In (1),

first of allA voltage divider circuit (6) and a secondIn the voltage division circuit (7), the voltage of the power supply is divided,

6. the simulation method for simulating a quantum logic gate by using an analog circuit according to claim 2, wherein the first signal synthesizing circuit (9) and the second signal synthesizing circuit (10) are implemented by using a summing circuit;

the summing circuit comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13 and an operational amplifier U4; one end of the resistor R9 is used as a first input end of the summing circuit, and one end of the resistor R10 is used as a second input end of the summing circuit;

the other end of the resistor R9 is connected with the other end of the resistor R10, one end of the resistor R11 and the positive input end of the operational amplifier U4, and the other end of the resistor R11 is connected with the power ground;

the inverting input end of the operational amplifier U4 is simultaneously connected with one end of the resistor R12 and one end of the resistor R13, and the other end of the resistor R12 is connected with the power ground;

the other end of the resistor R13 is connected to the output of the operational amplifier U4 and serves as the output of the summing circuit.

Background

The quantum logic gate is a model for quantum logic operation, is realized by the quantum effect of microscopic particles, and is different from a classical logic gate. The existing methods for simulating the quantum logic gate are all realized by computer software, and no method for simulating the quantum logic gate by a hardware circuit exists, so that the problems need to be solved urgently.

Disclosure of Invention

The invention aims to solve the problem that a method for simulating a quantum logic gate through a hardware circuit is lacked in the prior art, and provides a simulation method for simulating the quantum logic gate by using an analog circuit.

The simulation method for simulating the quantum logic gate by using the analog circuit is realized on the basis of the quantum logic gate consisting of the analog circuit, and the realization mode of the simulation method is as follows:

will signalSum signalAs two input signals of a quantum logic gate, a pair of signals through the quantum logic gateSum signalPerforming unitary transformation in two-dimensional Hilbert space to simulate two output signals of the quantum logic gateAndwherein the content of the first and second substances,representing a qubit |0>Probability amplitude phasor of the state before conversion;representing a qubit |1>Probability amplitude phasor of the state before conversion;representing a qubit |0>The probability amplitude phasor of the state after transformation,representing a qubit |1>Probability amplitude phasor of the state after transformation;

two output signals of the quantum logic gateAndrespectively with input signalsSum signalCorresponding; and satisfies the following relationship:

wherein the content of the first and second substances,and satisfies the following conditions:rho is a constant;

ω is the angular frequency, t is time,is a sinusoidal voltage x₀The initial phase of (a) is determined,is a sinusoidal voltage x₁Initial phase of (X)₀Is a sinusoidal voltage x₀Amplitude of (A), X₁Is a sinusoidal voltage x₁The amplitude of (c).

Preferably, the quantum logic gate formed by the analog circuit comprises a gamma phase shift circuit, a 90 degrees + sigma phase shift circuit, a 90 degrees-sigma phase shift circuit and a-gamma phase shift circuitFirst, aVoltage dividing circuit, firstVoltage divider circuit, secondVoltage divider circuit, secondThe differential-voltage converter comprises a voltage division circuit, a first signal synthesis circuit, a second signal synthesis circuit, a first delta phase-shifting circuit and a second delta phase-shifting circuit;

the gamma phase shift circuit and the 90-sigma phase shift circuit are used for receiving signals

Both the 90 DEG + sigma phase shift circuit and the-gamma phase shift circuit are used for receiving signals

The output terminal of the gamma phase shift circuit and the firstThe input end of the voltage division circuit is connected with the firstThe output end of the voltage division circuit is connected with the first input end of the first signal synthesis circuit;

output terminal and first terminal of 90 DEG + sigma phase shift circuitThe input end of the voltage division circuit is connected with the firstOutput end of voltage division circuit and first signal synthesis circuitIs connected with the second input end;

the output end of the first signal synthesis circuit is connected with the input end of the first delta phase shift circuit, and the output end of the first delta phase shift circuit is used for outputting signals

Output terminal and second terminal of 90-sigma phase shift circuitInput terminals of the voltage divider circuit are connected to each other, secondThe output end of the voltage division circuit is connected with the first input end of the second signal synthesis circuit;

-the output of the gamma phase shift circuit and the secondInput terminals of the voltage divider circuit are connected to each other, secondThe output end of the voltage division circuit is connected with the second input end of the second signal synthesis circuit;

the output end of the second signal synthesis circuit is connected with the input end of the second delta phase shift circuit, and the output end of the second delta phase shift circuit is used for outputting signals

Wherein, gamma, sigma, theta and delta are all angle variables.

Preferably, the signals are paired by quantum logic gatesSum signalPerforming unitary transformation of two-dimensional Hilbert space to simulate quantum logic gateTwo output signalsAndthe implementation mode of the method is as follows:

step one, enabling a gamma phase shift circuit and a 90-sigma phase shift circuit to simultaneously receive signalsThe 90 DEG + sigma phase shift circuit and the-gamma phase shift circuit simultaneously receive signals

Step two, gamma phase shift circuit is used for receiving signalsAfter phase shifting by gamma angle, obtainAnd will beIs sent to the firstA voltage dividing circuit;

90 DEG + sigma phase shift circuit for receiving signalAfter phase shifting by 90 degrees plus sigma degrees, obtainingAnd will beIs sent to the firstA voltage dividing circuit;

90-sigma phase shift circuit for receiving signalAfter phase shift is carried out for 90 degrees to one sigma angle, obtainingAnd will beIs sent to the secondA voltage dividing circuit;

-gamma phase shift circuit for receiving the signalAfter phase shifting by-gamma angle, obtainAnd will beIs sent to the secondA voltage dividing circuit;

step three, firstVoltage divider circuit for outputting to gamma phase shift circuitCarrying out partial pressure to obtainAnd will beTo the firstA signal synthesizing circuit;

first of allVoltage divider circuit for outputting to 90 ° + sigma phase shift circuitCarrying out partial pressure to obtainAnd will beSending the signal to a first signal synthesis circuit;

second oneVoltage divider circuit for outputting to 90-sigma phase shift circuitCarrying out partial pressure to obtainAnd will beSending the signal to a second signal synthesis circuit;

second oneVoltage divider circuit for output of para-gamma phase shift circuitCarrying out partial pressure to obtainAnd will beTo a second signal synthesizing circuit;

step four, the first signal synthesis circuit is used for receivingAndperforming summation operation to obtain summation resultAnd summing the resultsSending to a first delta phase shift circuit;

second signal synthesizing circuit for receivingAndsumming to obtain the sum resultAnd summing the resultsSending the signal to a second delta phase shift circuit;

step five, the summation result of the first delta phase shift circuit on the receivingAfter phase shifting by delta angle, obtaining signal

Second delta phase shift circuit for summing the received resultsAfter phase shifting by delta angle, obtaining signal

Preferably, the gamma phase shift circuit, the 90 DEG + sigma phase shift circuit, the 90 DEG-sigma phase shift circuit, the-gamma phase shift circuit, the first delta phase shift circuit and the second delta phase shift circuit are all realized by adopting angle phase shift circuits;

the angle phase shift circuit comprises resistors R1-R6, RC phase shift elements Z1-Z4, operational amplifiers U1, U2 and U5;

one end of the RC phase-shifting element Z1 is connected with one end of the resistor R1 and then serves as the input end of the angle phase-shifting circuit;

the other end of the RC phase-shifting element Z1 is connected with the RC phase-shifting element Z2 and the positive input end of an operational amplifier U1, and the other end of the RC phase-shifting element Z2 is connected with the power ground;

the inverting input end of the operational amplifier U1 is simultaneously connected with the other end of the resistor R1 and one end of the resistor R2, the other end of the resistor R2 is connected with the output end of the operational amplifier U1 and then is connected with one end of the RC phase shift element Z3 and one end of the resistor R3, the other end of the RC phase shift element Z3 is simultaneously connected with the RC phase shift element Z4 and the positive input end of the operational amplifier U2, and the other end of the RC phase shift element Z4 is connected with the power ground;

the inverting input end of the operational amplifier U2 is simultaneously connected with the other end of the resistor R3 and one end of the resistor R4, and the other end of the resistor R4 is connected with the output end of the operational amplifier U2 and then connected with the positive input end of the operational amplifier U5; the inverting input end of the operational amplifier U5 is connected with one end of a resistor R5 and one end of a resistor R6 at the same time, the other end of the resistor R5 is connected with a power ground, and the other end of the resistor R6 is connected with the output end of the operational amplifier U5 to serve as the output end of the angle phase shifting circuit;

when Z1 and Z3 are both resistors and Z2 and Z4 are both capacitors, the angle phase-shift circuit can realize negative angle phase shift; when Z1 and Z3 are both capacitors and Z2 and Z4 are both resistors, the angle phase-shift circuit can realize positive angle phase shift;

the resistance values of all resistors in the angle phase-shifting circuits adopted by the gamma phase-shifting circuit, the 90 degrees + sigma phase-shifting circuit, the 90 degrees-sigma phase-shifting circuit and the-gamma phase-shifting circuit are different, and the capacitance values of all capacitors in the angle phase-shifting circuits adopted by the y phase-shifting circuit, the 90 degrees + sigma phase-shifting circuit, the 90 degrees-sigma phase-shifting circuit and the-gamma phase-shifting circuit are different;

the resistance values of the resistors in the angle phase shift circuits adopted by the first delta phase shift circuit and the second delta phase shift circuit are the same, and the capacitance values of the capacitors are the same.

Preferably, the firstVoltage dividing circuit, firstVoltage divider circuit, secondVoltage divider circuit and secondThe voltage division circuits are all realized by adopting voltage division circuit units;

the voltage division circuit unit comprises a resistor R7, a resistor R8 and an operational amplifier U3;

one end of the resistor R7 is used as the input end of the voltage division circuit unit, the other end of the resistor R7 is connected with one end of the resistor R8 and the positive input end of the operational amplifier U3, and the other end of the resistor R8 is connected with the power ground;

the inverting input end of the operational amplifier U3 is connected with the output end of the operational amplifier U3 and then serves as the output end of the voltage division circuit unit;

wherein the content of the first and second substances,

the first isVoltage divider circuit and secondIn the voltage-dividing circuit,

first of allVoltage divider circuit and secondIn the voltage-dividing circuit,

preferably, the first signal synthesizing circuit and the second signal synthesizing circuit are both implemented by a summing circuit;

the summing circuit comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13 and an operational amplifier U4; one end of the resistor R9 is used as a first input end of the summing circuit, and one end of the resistor R10 is used as a second input end of the summing circuit;

the other end of the resistor R9 is connected with the other end of the resistor R10, one end of the resistor R11 and the positive input end of the operational amplifier U4, and the other end of the resistor R11 is connected with the power ground;

the inverting input end of the operational amplifier U4 is simultaneously connected with one end of the resistor R12 and one end of the resistor R13, and the other end of the resistor R12 is connected with the power ground;

the other end of the resistor R13 is connected to the output of the operational amplifier U4 and serves as the output of the summing circuit.

The invention has the following beneficial effects:

the invention uses two sinusoidal voltage signals x₀And x₁Separately characterizing qubits |0>Sum of states |1>Time-domain form of probability amplitude of state before transformation, x₀And x₁In the form of phasors ofAndandas two input signals of a single-quantum-bit logic gate, and constructing an analog quantum logic gate consisting of an analog circuit to realize the quantum bit |0>State input signalAnd qubit |1>State input signalPerforming unitary transformation of two-dimensional Hilbert space to give two output signals of the quantum logic gateAndusing two sinusoidal voltage signals x₀And x₁Respectively represent qubits |0>Sum of states |1>Time-domain form of probability amplitude of state before transformation, x₀And x₁Phasor form ofAndrespectively having a number x₀And x₁Represents |0>Sum of states |1>A plurality of probability magnitudes before state transformation; the transformed | 0' containing sinusoidal voltage signals can be known>Sum of states |1>Probability magnitude vector of stateAndobtaining the superposition state before and after quantum bit transformation; therefore, the quantum logic gate is simulated by a hardware circuit.

Further expanding, the invention can simulate the combinational logic state of the quantum formed by the multiple quantum bits.

The invention simulates the unitary conversion of quantum signals by the way of sinusoidal signal phase shift, voltage division and synthesis operation, and constructs a circuit based on the unitary conversion.

The simulation method for simulating the quantum logic gate by using the simulation circuit is mainly applied to the aspects of teaching demonstration and the like of the quantum logic gate.

Drawings

FIG. 1 is a schematic diagram of a quantum logic gate formed from analog circuitry;

FIG. 2 is a schematic diagram of an angle phase shift circuit;

FIG. 3 is a schematic diagram of a voltage divider circuit unit;

fig. 4 is a schematic diagram of the structure of the summing circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

Referring to fig. 1, a description will be given of an embodiment of the present invention, in which the simulation method for simulating a quantum logic gate by using an analog circuit is realized based on a quantum logic gate formed by an analog circuit, and the simulation method is realized by:

will signalSum signalAs two input signals of a quantum logic gate, a pair of signals through the quantum logic gateSum signalPerforming unitary transformation in two-dimensional Hilbert space to simulate two output signals of the quantum logic gateAndwherein the content of the first and second substances,representing a qubit |0>Probability amplitude phasor of the state before conversion;representing a qubit |1>Probability amplitude phasor of the state before conversion;representing a qubit |0>The probability amplitude phasor of the state after transformation,representing a qubit |1>Probability amplitude phasor of the state after transformation;

two output signals of the quantum logic gateAndrespectively with input signalsSum signalCorresponding; and satisfies the following relationship:

wherein the content of the first and second substances,and satisfies the following conditions:rho is a constant;

ω is the angular frequency, t is time,is a sinusoidal voltage x₀The initial phase of (a) is determined,is a sinusoidal voltage x₁Initial phase of (X)₀Is a sinusoidal voltage x₀Amplitude of (A), X₁Is a sinusoidal voltage x₁The amplitude of (c).

In this embodiment, the qubit is represented by |0>Sum of states |1>The superposition state of the states is specifically |0>State and |1>State according to formulaSuperposing; the square of the modulus of the probability amplitude, i.e. |0>Sum of states |1>The probability of a state occurrence, ψ, is a 1 unit vector of 1 qubit, describing a two-dimensional Hilbert space.

This implementationBy means of two sinusoidal voltage signals x₀Sum signal x₁Representing quantum logic |0>Sum of states |1>The time-domain form of the probability magnitude of the state before transformation,is a qubit |0>Probability amplitude phasor of state before conversion, i.e. using sinusoidal voltage x₀Voltage phasor form ofTo characterize the qubit |0>The probability amplitude of the state is obtained,is a qubit |1>Probability amplitude phasor of state before conversion, i.e. using sinusoidal voltage x₁Voltage phasor form ofTo characterize a qubit |1>The probability amplitude of the state is obtained,andas two input signals of the quantum logic gate, and constructing the quantum logic gate composed of analog circuits to realize the pair signalAndperforming unitary transformation on the two-dimensional Hilbert space rotating gate to give two output signals of the quantum logic gateAndrepresenting a qubit |0>Probability amplitude of state before conversionPhasor;representing the probability amplitude phasor of a qubit |1} state before transformation;representing a qubit |0>The probability amplitude phasor of the state after transformation,representing a qubit |1>Probability amplitude phasor of the state after transformation; since the transformed quantum bit |0 is known>State probability phasor and qubit |1>The state probability amplitude phasor can obtain the superposed state before and after the conversion of the quantum bit; therefore, the quantum logic gate is simulated by a hardware circuit, and the quantum logic gate applying the simulation can output the current state of the quantum bit.

Further, referring specifically to fig. 1, the quantum logic gate formed by analog circuits includes a gamma phase shift circuit 1, a 90 ° + sigma phase shift circuit 2, a 90 ° -sigma phase shift circuit 3, a-gamma phase shift circuit 4, and a firstVoltage divider circuit 5, firstVoltage divider circuit 6, secondVoltage divider circuit 7, secondA voltage dividing circuit 8, a first signal synthesizing circuit 9, a second signal synthesizing circuit 10, a first delta phase shift circuit 11 and a second delta phase shift circuit 12;

the gamma phase shift circuit 1 and the 90-sigma phase shift circuit 3 are both used for receiving signals

90 + sigma shiftBoth the phase circuit 2 and the-gamma phase shift circuit 4 are used for receiving signals

The output terminal of the gamma phase shift circuit 1 and the firstThe input terminal of the voltage dividing circuit 5 is connected with the firstThe output end of the voltage division circuit 5 is connected with the first input end of the first signal synthesis circuit 9;

the output terminal of the 90 DEG + sigma phase shift circuit 2 and the firstThe input terminal of the voltage divider circuit 6 is connected to the firstThe output end of the voltage division circuit 6 is connected with the second input end of the first signal synthesis circuit 9;

the output terminal of the first signal synthesizing circuit 9 is connected with the input terminal of a first delta phase shift circuit 11, and the output terminal of the first delta phase shift circuit 11 is used for outputting signals

The output terminal and the second of the 90-sigma phase shift circuit 3Input terminals of the voltage dividing circuit 7 are connected, secondThe output end of the voltage division circuit 7 is connected with the first input end of the second signal synthesis circuit 10;

-the output of the gamma phase shift circuit 4 and the secondInput terminals of the voltage dividing circuit 8 are connected, secondThe output end of the voltage division circuit 8 is connected with the second input end of the second signal synthesis circuit 10;

the output terminal of the second signal synthesizing circuit 10 is connected to the input terminal of the second delta phase shift circuit 12, and the output terminal of the second delta phase shift circuit 12 is used for outputting signals

Wherein, gamma, sigma, theta and delta are all angle variables.

In the preferred embodiment, through the construction of a simple analog circuit, the construction of an analog quantum logic gate is realized, and the unitary transformation of a quantum bit is realized, so that the superposition state of a quantum is simulated.

1 qubit can be described as 1 unit vector in two-dimensional Hilbert space, which can be expressed as:

ψ ═ H |0> + V |1> (formula five);

wherein { |0>, |1> } are pure basis vectors, H, V are complex numbers, and | H |2+ | V |2 ═ 1 is satisfied; H. v can be continuously valued, H represents the probability amplitude of |0> state, and V represents the probability amplitude of |1> state. The case corresponding to classical binary digital logic is that the |0> state corresponds to classical logic "0", and the |1> state corresponds to classical logic "1", but unlike classical binary logic, the quantum state logic corresponding to each qubit is a superposition of |0> and |1> states as represented by equation five; and the conversion between the classical logic values is the conversion between high and low levels, namely the conversion between '1' and '0', and is not '0' or '1', and has no superposition state of intermediate states. This is the difference between classical logic gates and quantum logic gates.

The method can be realized by performing unitary conversion on the qubits and utilizing the quantum logic gate simulated by the circuit for realizing the unitary conversion in various ways, wherein:

the general form of a unitary transform of 1 qubit in two-dimensional Hilbert space is:

δ, α, β, θ are all real numbers.

According to circuit theory, the initial phase can be used mathematically asAmplitude of X₀Sinusoidal voltage with angular frequency of omega and time t as variableRepresents |0 in formula one>State probability amplitude H, x₀Representing a qubit |0>Time-domain form of the probability magnitude before state transformation. With an initial phase ofAmplitude of X₁Sine voltage ofRepresents |1 in formula one>Magnitude of state probability V, x₁Represents a qubit |1>The state is in the time-domain form of the probability magnitude before transformation, so that the following relationship exists:

wherein the content of the first and second substances,andis x₀And x₁In the form of a phasor of (a),and satisfies the following conditions:ρ is a constant.

The way of performing the unitary transformation U (δ, α, β, θ) of the two-dimensional Hilbert space on a single qubit is:

is provided withAfter U (delta, alpha, beta, theta) conversion, respectivelyAccording to the formula five, the following steps are provided:

solving formula seven can result in:

let γ ═ α + β)/2, σ ═ α - β)/2; and both gamma and sigma are angle variables, and the formula I and the formula II are put into the formula eight to obtain:

wherein in the formula nine, ei δ andthe terms may be implemented with an angular phase shift circuit,andthe term may be implemented with a voltage divider circuit.

Further, referring specifically to FIG. 1, the signals are paired by quantum logic gatesSum signalPerforming unitary transformation in two-dimensional Hilbert space to simulate two output signals of the quantum logic gateAndthe implementation mode of the method is as follows:

step one, the gamma phase shift circuit 1 and the 90-sigma phase shift circuit 3 receive signals simultaneouslyThe 90 DEG + sigma phase shift circuit 2 and the-gamma phase shift circuit 4 simultaneously receive signals

Step two, the gamma phase shift circuit 1 is used for receiving the signalsAfter phase shifting by gamma angle, obtainAnd will beIs sent to the firstA voltage dividing circuit 5;

90 DEG + sigma phase shift circuit 2 for receiving the signalAfter phase shifting by 90 degrees plus sigma degrees, obtainingAnd will beIs sent to the firstA voltage dividing circuit 6;

90-sigma phase shift circuit 3 pairs received signalsAfter phase shifting by 90-sigma degrees, obtainingAnd will beIs sent to the secondA voltage dividing circuit 7;

-gamma phase shift circuit 4 for the received signalAfter phase shifting by-gamma angle, obtainAnd will beIs sent to the secondA voltage dividing circuit 8;

step three, firstThe voltage-dividing circuit 5 is used for outputting to the gamma phase-shifting circuit 1Carrying out partial pressure to obtainAnd will beTo the first signal synthesizing circuit 9;

first of allA voltage divider circuit 6 for outputting to the 90 ° + sigma phase shift circuit 2Carrying out partial pressure to obtainAnd will beSent to the first signal synthesizing circuit 9;

second oneA voltage divider circuit 7 for outputting to the 90-sigma phase shift circuit 3Carrying out partial pressure to obtainAnd will beTo the second signal synthesizing circuit 10;

second oneA voltage divider circuit 8 for outputting to the gamma phase shift circuit 4Carrying out partial pressure to obtainAnd will beTo the second signal synthesizing circuit 10;

step four, the first signal synthesis circuit 9 is used for receivingAndperforming summation operation to obtain summation resultAnd summing the resultsSent to the first delta phase shift circuit 11;

second signal synthesis circuit 10 for receivingAndsumming to obtain the sum resultAnd summing the resultsSent to the second delta phase shift circuit 12;

step five, the first delta phase shift circuit 11 sums the received summation resultAfter phase shifting by delta angle, obtaining signal

The second delta phase shift circuit 12 sums the received resultsAfter phase shifting by delta angle, obtaining signal

In the preferred embodiment, the signal pair is provided by utilizing the constructed analog quantum logic gateAndthe specific implementation mode of the unitary transformation of the two-dimensional Hilbert space revolving door is simple in hardware circuit structure and convenient to implement.

Further, referring specifically to fig. 2, the γ phase shift circuit 1, the 90 ° + σ phase shift circuit 2, the 90 ° - σ phase shift circuit 3, the- γ phase shift circuit 4, the first δ phase shift circuit 11, and the second δ phase shift circuit 12 are all implemented by angle phase shift circuits;

the angle phase shift circuit comprises resistors R1-R6, RC phase shift elements Z1-Z4, operational amplifiers U1, U2 and U5;

one end of the RC phase-shifting element Z1 is connected with one end of the resistor R1 and then serves as the input end of the angle phase-shifting circuit;

the other end of the RC phase-shifting element Z1 is connected with the RC phase-shifting element Z2 and the positive input end of an operational amplifier U1, and the other end of the RC phase-shifting element Z2 is connected with the power ground;

the inverting input end of the operational amplifier U1 is simultaneously connected with the other end of the resistor R1 and one end of the resistor R2, the other end of the resistor R2 is connected with the output end of the operational amplifier U1 and then is connected with one end of the RC phase shift element Z3 and one end of the resistor R3, the other end of the RC phase shift element Z3 is simultaneously connected with the RC phase shift element Z4 and the positive input end of the operational amplifier U2, and the other end of the RC phase shift element Z4 is connected with the power ground;

the inverting input end of the operational amplifier U2 is simultaneously connected with the other end of the resistor R3 and one end of the resistor R4, and the other end of the resistor R4 is connected with the output end of the operational amplifier U2 and then connected with the positive input end of the operational amplifier U5; the inverting input end of the operational amplifier U5 is connected with one end of a resistor R5 and one end of a resistor R6 at the same time, the other end of the resistor R5 is connected with a power ground, and the other end of the resistor R6 is connected with the output end of the operational amplifier U5 to serve as the output end of the angle phase shifting circuit;

when Z1 and Z3 are both resistors and Z2 and Z4 are both capacitors, the angle phase-shift circuit can realize negative angle phase shift; when Z1 and Z3 are both capacitors and Z2 and Z4 are both resistors, the angle phase-shift circuit can realize positive angle phase shift;

the resistance values of all resistors in the angle phase shift circuits adopted by the gamma phase shift circuit 1, the 90 degrees + sigma phase shift circuit 2, the 90 degrees-sigma phase shift circuit 3 and the gamma phase shift circuit 4 are different, and the capacitance values of all capacitors in the angle phase shift circuits adopted by the gamma phase shift circuit 1, the 90 degrees + sigma phase shift circuit 2, the 90 degrees-sigma phase shift circuit 3 and the gamma phase shift circuit 4 are different;

the first delta phase shift circuit 11 and the second delta phase shift circuit 12 respectively adopt angle phase shift circuits in which the resistance values of resistors are the same and the capacitance values of capacitors are the same.

In the preferred embodiment, specific structures of the gamma phase-shifting circuit 1, the 90 ° + sigma phase-shifting circuit 2, the 90 ° -sigma phase-shifting circuit 3, the-gamma phase-shifting circuit 4, the first delta phase-shifting circuit 11 and the second delta phase-shifting circuit 12 are given, the structures of the gamma phase-shifting circuit 1, the 90 ° + sigma phase-shifting circuit 2, the 90 ° -sigma phase-shifting circuit 3, the-gamma phase-shifting circuit 4, the first delta phase-shifting circuit 11 and the second delta phase-shifting circuit 12 are the same, when the gamma phase-shifting circuit 1, the 90 ° + sigma phase-shifting circuit 2, the 90 ° -sigma phase-shifting circuit 3, the-gamma phase-shifting circuit 4, the first delta phase-shifting circuit 11 and the second delta-sigma phase-shifting circuit 12 are respectively corresponding to one angle phase-shifting circuit, and the respective functions are realized by changing the resistance values and the capacitance values of the respective phase-shifting circuits, the realization mode is simple and convenient to realize.

Further, with particular reference to FIG. 3, the firstVoltage divider circuit 5, firstVoltage divider circuit 6, secondVoltage dividing circuit 7 and secondThe voltage division circuits 8 are all realized by adopting voltage division circuit units;

the voltage division circuit unit comprises a resistor R7, a resistor R8 and an operational amplifier U3;

one end of the resistor R7 is used as the input end of the voltage division circuit unit, the other end of the resistor R7 is connected with one end of the resistor R8 and the positive input end of the operational amplifier U3, and the other end of the resistor R8 is connected with the power ground;

the inverting input end of the operational amplifier U3 is connected with the output end of the operational amplifier U3 and then serves as the output end of the voltage division circuit unit;

wherein the content of the first and second substances,

the first isVoltage divider circuit 5 and secondIn the voltage-dividing circuit 8, a voltage-dividing circuit,

first of allVoltage dividing circuit 6 and secondIn the voltage-dividing circuit 7, a voltage-dividing circuit,

in the present embodiment, the firstVoltage divider circuit 5, firstVoltage divider circuit 6, secondVoltage dividing circuit 7 and secondThe specific structure of the voltage divider circuit 8 is the same as that of the voltage divider circuit 8In time, cos theta times of partial pressure can be realized; when in useIn time, sin and theta times of voltage division can be realized, and the circuit is simple in structure and convenient to realize.

Further, referring specifically to fig. 4, the first signal synthesizing circuit 9 and the second signal synthesizing circuit 10 are implemented by summing circuits;

the summing circuit comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13 and an operational amplifier U4; one end of the resistor R9 is used as a first input end of the summing circuit, and one end of the resistor R10 is used as a second input end of the summing circuit;

the other end of the resistor R9 is connected with the other end of the resistor R10, one end of the resistor R11 and the positive input end of the operational amplifier U4, and the other end of the resistor R11 is connected with the power ground;

the inverting input end of the operational amplifier U4 is simultaneously connected with one end of the resistor R12 and one end of the resistor R13, and the other end of the resistor R12 is connected with the power ground;

the other end of the resistor R13 is connected to the output of the operational amplifier U4 and serves as the output of the summing circuit.

In the preferred embodiment, specific structures of the first signal synthesizing circuit 9 and the second signal synthesizing circuit 10 are given, both of which are implemented by using a summing circuit, and the structures of both of which are completely the same.

In a specific application, the first signal synthesizing circuit 9 and the second signal synthesizing circuit 10 correspond to a summing circuit respectively.

The first input end of the summation circuit corresponding to the first signal synthesis circuit 9 is used as the first input end of the first signal synthesis circuit 9, the second input end of the summation circuit is used as the second input end of the first signal synthesis circuit 9, and the output end of the summation circuit is used as the output end of the first signal synthesis circuit 9.

The first input end of the summing circuit corresponding to the second signal synthesizing circuit 10 is used as the first input end of the second signal synthesizing circuit 10, the second input end of the summing circuit is used as the second input end of the second signal synthesizing circuit 10, and the output end of the summing circuit is used as the output end of the second signal synthesizing circuit 10.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements of phase gates and the like may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.