1. A degradation simulation model building method is characterized by comprising the following steps:

providing a p-type MOSFET, wherein the p-type MOSFET has a source and a drain;

measuring first reliability degradation data for the p-type MOSFET;

selecting a model for a p-type MOSFET, the model having a plurality of modeling parameters related to hot carrier induced punch-through, wherein the plurality of modeling parameters include hot carrier injection parameters for modifying a simulated current between the source and the drain;

constructing the plurality of modeling parameters by multiplying a plurality of degradation parameters by a corresponding plurality of control condition parameters;

performing a simulation of the p-type MOSFET with the model to obtain second reliability degradation data;

if the first reliability data does not match the second reliability data, updating the plurality of degradation parameters and re-performing the simulation of the p-type MOSFET with the model; and

when the first reliability data matches the second reliability data, collecting the plurality of degradation parameters to build a degradation simulation model for the p-type MOSFET.

2. The degradation modeling method of claim 1, wherein an equivalent channel length of the p-type MOSFET is less than 100 nanometers.

3. The degradation simulation modeling method of claim 1, further comprising:

the p-type MOSFET is surrounded by a shallow trench isolation region having a linear nitride.

4. The degradation simulation modeling method of claim 1, wherein the step of measuring the first reliability degradation data for the p-type MOSFET further comprises:

measuring a current between the source and the drain of the p-type MOSFET, wherein the first reliability data is the measured current versus time,

wherein a voltage between the source and the drain is greater than a voltage of the source and a gate of the p-type MOSFET.

5. The degradation simulation model building method of claim 1, wherein the model comprises a MOS modeling and reliability analysis modeling scheme model.

6. The method according to claim 1, wherein the hot carrier injection parameters are related to temperature, driving voltage and equivalent channel length of the p-type MOSFET, respectively.

7. The degradation simulation modeling method of claim 1, wherein each condition parameter is one or zero, and the plurality of control condition parameters are configured to perform an on/off logic function.

8. A degradation simulation model building method is characterized by comprising the following steps:

providing a p-type MOSFET, wherein the p-type MOSFET has a source and a drain;

measuring first reliability degradation data for the p-type MOSFET;

selecting a model for a p-type MOSFET, the model having an additional plurality of modeling parameters for reliability;

performing a simulation of the p-type MOSFET with the model to obtain simulated reliability degradation data;

constructing a fitting function having a plurality of degradation parameters related to hot carrier induced punch-through, wherein the plurality of degradation parameters are used to modify the simulated current between the source and the drain;

constructing second reliability degradation data by adding the simulated reliability degradation data to the fitting function;

if the first reliability data is not matched with the second reliability data, updating the plurality of degradation parameters and recalculating the fitting function to obtain improved second reliability data; and

when the first reliability data matches the second reliability data, collecting the fitting function and the plurality of degradation parameters to build a degradation simulation model for the p-type MOSFET.

9. The degradation modeling method of claim 8, wherein an equivalent channel length of the p-type MOSFET is less than 100 nanometers.

10. The degradation simulation modeling method of claim 8, further comprising:

the p-type MOSFET is surrounded by a shallow trench isolation region having a linear nitride.

11. The degradation modeling method of claim 8, wherein the step of measuring the first reliability degradation data for the p-type MOSFET further comprises:

measuring a current between the source and the drain of the p-type MOSFET, wherein the first reliability data is the measured current versus time,

wherein a voltage between the source and the drain is greater than a voltage of the source and a gate of the p-type MOSFET.

12. The method of claim 8, wherein the model comprises a berkeley short channel insulated gate field effect transistor model 4 model.

13. The degradation simulation modeling method of claim 8, wherein the step of performing the simulation of the p-type MOSFET with the model to obtain the simulated reliability degradation data further comprises:

and setting a reliability period for the simulation.

14. The degradation simulation modeling method of claim 8, wherein the fitting function includes a control condition parameter, the control condition parameter is one or zero, and the control condition parameter is configured to perform an on/off logic function.

Background

In the design of integrated circuits, designers must simulate the behavior of the integrated circuit being designed. The designer can predict the performance of the designed integrated circuit under real conditions according to the electrical results simulated by the computer. For example, for integrated circuit simulation, degraded performance of devices is an important issue.

For conventional p-type metal oxide semiconductor field effect transistor (p-type MOSFET) simulations, Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) were considered to predict device degradation performance in integrated circuits. However, for p-type MOSFETs with short channel lengths, in addition to the model of NBTI and HCI phenomena, additional hot electron induced punch-through (HEIP) phenomena can lead to undesired electrical behavior of short channel p-type MOSFETs.

Therefore, it is one of the problems to be solved by those skilled in the art to improve the conventional simulation method to obtain a simulation result that matches the measurement result of the short channel p-type MOSFET.

Disclosure of Invention

An aspect of the present invention relates to a degradation simulation model building method that can provide more accurate simulation results.

According to an embodiment of the present invention, a degradation simulation model building method includes the following procedures. A p-type metal oxide semiconductor field effect transistor (p-type MOSFET) is provided, wherein the p-type MOSFET has a source and a drain. First reliability degradation data for the p-type MOSFET is measured. A model for a p-type MOSFET is selected, the model having a plurality of modeling parameters related to hot carrier induced punch-through (HEIP), wherein the modeling parameters include a Hot Carrier Injection (HCI) parameter for modifying an analog current between a source and a drain. The modeling parameters are constructed by multiplying a plurality of degradation parameters by a corresponding plurality of control condition parameters. Simulation of the p-type MOSFET is performed with the model to obtain second reliability degradation data. If the first reliability data does not match the second reliability data, the degradation parameter is updated and the model is used to perform the p-type MOSFET simulation again. When the first reliability data matches the second reliability data, the degradation parameters are collected to build a degradation simulation model for the p-type MOSFET.

In one or more embodiments of the present invention, the equivalent channel length of the p-type MOSFET is less than 100 nanometers.

In one or more embodiments of the present invention, the method for building a degradation simulation model further includes the following steps. The p-type MOSFET is surrounded by a shallow trench isolation region having a linear nitride.

In one or more embodiments of the present invention, the step of measuring the first reliability degradation data of the p-type MOSFET further comprises the following process. The current between the source and drain of the p-type MOSFET is measured. The first reliability data is a measured current versus time. At this time, the voltage between the source and the drain is greater than the voltage between the source and the gate of the p-type MOSFET.

In one or more embodiments of the present invention, the model includes a MOS modeling and reliability analysis modeling solution (MOSRA) model.

In one or more embodiments of the present invention, the hot carrier injection parameter is respectively related to the temperature, the driving voltage and the equivalent channel length of the p-type MOSFET.

In one or more embodiments of the present invention, each of the control condition parameters is one or zero, and the control condition parameters are configured to perform an on/off logic function.

Another aspect of the invention relates to a degradation simulation model building method.

According to an embodiment of the present invention, a degradation simulation model building method includes the following procedures. A p-type metal oxide semiconductor field effect transistor (p-type MOSFET) is provided, wherein the p-type MOSFET has a source and a drain. First reliability degradation data for the p-type MOSFET is measured. A model for the p-type MOSFET is selected, the model having an additional plurality of modeling parameters for reliability. Simulation of the p-type MOSFET is performed in a model to obtain simulated reliability degradation data. A fitting function is constructed with a plurality of degradation parameters that are related to hot carrier induced punch-through (HEIP). These degradation parameters are used to correct the analog current between the source and drain. Second reliability degradation data is constructed by adding the simulated reliability degradation data to a fitting function. If the first reliability data is not matched with the second reliability data, the degradation parameters are updated and the fitting function is recalculated to obtain the improved second reliability data. When the first reliability data is matched with the second reliability data, a fitting function and degradation parameters are collected to establish a degradation simulation model for the p-type MOSFET.

In one or more embodiments of the present invention, the equivalent channel length of the p-type MOSFET is less than 100 nanometers.

In one or more embodiments of the present invention, the degradation simulation modeling method further includes the following steps. The p-type MOSFET is surrounded by a shallow trench isolation region having a linear nitride.

In one or more embodiments of the present invention, the step of measuring the first reliability degradation data of the p-type MOSFET further comprises the following process. Measuring a current between a source and a drain of the p-type MOSFET, wherein the first reliability data is the measured current versus time. At this time, the voltage between the source and the drain is greater than the voltage between the source and the gate of the p-type MOSFET.

In one or more embodiments of the invention, the model comprises the berkeley short-channel IGFET model 4 (BSIM 4) model.

In some embodiments, the step of performing a simulation of the p-type MOSFET in a model to obtain simulated reliability degradation data further comprises the following process. The reliability period is set for the simulation.

In one or more embodiments of the invention, the fitting function includes control condition parameters. The control condition parameter is one or zero, configured to perform an on/off logic function.

In summary, for the two degradation simulation modeling methods of the present invention, hot carrier induced punch-through in short channel p-type MOSFETs is taken into account, such simulation is based on conventional simulation models, and the results of the simulation can be compared with the measured results.

It is to be understood that both the foregoing general description and the following detailed description are further explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

The advantages of the invention, together with the accompanying drawings, will be best understood from the following description taken in connection with the accompanying drawings. The description of the figures is for illustrative embodiments only and is not intended to limit individual embodiments or the scope of the appended claims.

FIG. 1 illustrates a schematic top view of a short channel p-type MOSFET, according to one embodiment of the present invention;

FIG. 2 illustrates a degradation performance measured from the short channel p-type MOSFET of FIG. 1;

FIG. 3 depicts simulated degradation behavior and corresponding fitting points for the short channel p-type MOSFET of FIG. 1;

FIG. 4 is a flow chart illustrating a method of building a degradation simulation model according to one embodiment of the present invention;

FIG. 5 depicts a degradation performance measured from the short channel p-type MOSFET of FIG. 1 and the corresponding simulation curve generated by the degradation simulation modeling method of FIG. 4; and

FIG. 6 is a flow chart of another method for building a degradation simulation model according to an embodiment of the invention.

Description of the main reference numerals:

the method comprises the steps of 100-p type MOSFET, 110-source terminal, 120-grid terminal, 130-drain terminal, 140-shallow trench isolation region, 200-degradation simulation model establishing method, 210-245-process, 300-degradation simulation model establishing method, 310-350-process, C1, C2, C3-curve, F-curve and Leff-channel length.

Detailed Description

The following detailed description of the embodiments with reference to the drawings is provided for purposes of illustration, and is not intended to limit the scope of the invention, which is defined by the claims, as well as the appended drawings. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be described with the same reference numerals in the following description.

Unless defined otherwise, all words (including technical and scientific terms) used herein have their ordinary meaning as is understood by those skilled in the art. Furthermore, the definitions of the above-mentioned words in commonly used dictionaries should be interpreted as having a meaning consistent with the context of the present invention. Unless specifically defined otherwise, these terms are not to be interpreted in an idealized or overly formal sense.

As used herein, the terms "first," "second," …, etc., are not intended to be limited to the exact order or sequence presented, nor are they intended to be limiting, but rather are intended to distinguish one element from another or from another element or operation described by the same technical term.

Furthermore, as used herein, the terms "comprising," "including," "having," "containing," and the like are open-ended terms that mean including, but not limited to.

In this document, the articles "a" and "an" may mean "one or more" unless the context specifically states otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and similar language, when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 illustrates a schematic top view of a short channel p-type MOSFET100 according to an embodiment of the present invention. In this embodiment, the p-type MOSFET100 is a planar p-type MOSFET. In some embodiments, the p-type MOSFET100 is part of a planar CMOS.

In this embodiment, the p-type MOSFET100 is a p-type MOSFET made of silicon, but this is not intended to limit the present invention.

As shown in fig. 1, the planar p-type MOSFET100 includes a source terminal 110, a gate terminal 120, and a drain terminal 130. The gate terminal 120 is located above the portion of the channel between the source terminal 110 and the drain terminal 130. Since the gate terminal 120 is located above the channel portion, the corresponding channel portion has an equivalent channel length Leff as indicated in the drawing.

In this embodiment, the planar p-type MOSFET100 further includes a Shallow Trench Isolation (STI) 140. As shown in fig. 1, shallow trench isolation region 140 surrounds p-type MOSFET 100. Specifically, the shallow trench isolation region 140 surrounds the source terminal 110, the drain terminal 130, and a portion of the channel between the source terminal 110 and the drain terminal 130. The sti region 140 is used to electrically isolate the p-type MOSFET100 from other devices.

For a p-type MOSFET, the dominant carriers are holes. One electrokinetic corresponds to the absence of one electron in the semiconductor). For the p-type MOSFET100, a void may be formed not only within the p-type MOSFET100, but also between the p-type MOSFET100 and the shallow trench isolation region 140 and at the interface between the channel portion and the gate terminal 120.

In the present embodiment, the p-type MOSFET100 has a channel portion with a channel length Leff less than 100 nanometers. Therefore, the height difference between the p-type MOSFET100 and the shallow trench isolation region 140, and the height difference between the channel portion and the gate terminal 120 are main causes of the generation of the void. Equivalently, holes in p-type MOSFET100 may be localized to the void at the interface of sti region 140 or to the oxide near drain terminal 130. The oxide near the drain terminal 130 is the interface between the channel portion and the gate terminal 120. This results in an undesirable electrical behavior for a short channel p-type MOSFET100 that is beyond the scope of conventional simulations. The undesired electrical behavior of holes in the short channel p-type MOSFET100 is referred to as hot electron induced punch-through (HEIP), and this causes the current to increase and decrease from the source terminal 110 to the drain terminal 130.

Fig. 2 shows a degradation performance measured from the short channel p-type MOSFET100 of fig. 1. The degradation behavior is measured by a reliability test to show the degradation change of the current under the reliability test.

In order to obtain the electrical performance of the short channel p-type MOSFET100, it is necessary to understand how the p-type MOSFET100 degrades during the operation of the p-type MOSFET100 through reliability tests. In this embodiment, the voltage difference between the source terminal 110 and the drain terminal 130 is greater than the voltage difference between the source terminal 110 and the gate terminal 120. This corresponds to the horizontal electric field strength from the source terminal 110 to the drain terminal 130 being greater than the vertical electric field from the gate terminal 120 to the source terminal 110. Thus, current flows from the source terminal 110 to the drain terminal 130. For p-type MOSFET100, it is the movement of holes that causes the generation of current flow.

The holes from the source terminal 110 to the drain terminal 130 may damage the p-type MOSFET100, and the degradation behavior is as illustrated in fig. 2, the damage of the p-type MOSFET100 causes the current to change. For example, in the present embodiment, since the p-type MOSFET100 is a short channel p-type MOSFET100, holes can be localized and accumulated at the interface between the sti region 140 and the oxide of the gate terminal 120 near the drain terminal 130. The accumulation of holes in this way damages the drain terminal 130, which causes the current flow to the drain terminal 130 to change.

In fig. 2, the abscissa axis is related to the stress time of the reliability test, and the ordinate axis is the degradation degree of the current from the source terminal 110 to the drain terminal 130. When the reliability test begins, a "0" in the vertical axis degradation is defined by the initial current. The degradation degree of fig. 2 is defined as a ratio of a current change to a starting current to represent a ratio of a current change amount compared to the starting current. As shown in fig. 2, the degree of degradation of the vertical axis decreases from slightly more than zero to less than zero over time, which corresponds to an increase and then decrease in current from the source terminal 110 to the drain terminal 130.

However, fig. 3 illustrates the simulated degradation behavior of the short channel p-type MOSFET100 of fig. 1, and the corresponding fitting point. The current from the source terminal 110 to the drain terminal 130 does not increase and then decreases from the corresponding fitting point of the corresponding current. The horizontal axis of fig. 3 relates to the application time, and the vertical axis is the degree of current degradation and is expressed in percentage (%).

In this embodiment, the three sets of simulation results shown in fig. 3 are obtained by performing a simulation using a berkeley short-channel IGFET model 4 (BSIM 4) model and considering a MOS modeling and reliability analysis modeling scheme (MOS modeling and reliability analysis solution) model. The use of the model of the present invention is not limited to the above-described models.

The BSIM4 model is one of the berkeley short channel insulated gate field effect transistor models (BSIMs). The BSIM model may be used as a series of MOSFETs for integrated circuit design. In some embodiments, the BSIM4 simulation may be implemented by including programs such as an integrated circuit simulation program with integrated circuit (SPICE).

MOSRA is a simulation program for simulating the degradation of MOSFET elements. Degradation is caused by, for example, Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI). MOSRA may be a post-handler of the BSIM4 model. However, since the short channel p-type MOSFET does not take into account the HEIP effect of MORSA, its unexpected electrical behavior cannot be reproduced. In some embodiments, the MORSA comprises MORSA level 1 and MORSA level 3. MORSA level 1 is established based on a physics-based process, while MORSA level 3 is established based on an empirical model. The modeling parameters of MORSA are related to the temperature, drive voltage, and channel length of the analog p-type MOSFET of MORSA level 1 and MORSA level 3, respectively.

As shown in fig. 3, three different fitting curves C1, C2 and C3 are transformed from three different sets of analog data points, respectively, and all the analog data points show that the current from the source terminal 110 to the drain terminal 130 decreases with the application time. The simulation results of fig. 3 are different from the degradation behavior measured as shown in fig. 2. Thus, in correspondence with the conventional model, in the case of the BSIM4 model and taking MOSRA into consideration, it is also necessary to have the HEIP phenomenon reflected thereto.

To improve simulation results, in one embodiment of the present invention, a degradation simulation model building method 200 is provided.

FIG. 4 is a flow chart of a degradation simulation model building method 200 according to an embodiment of the invention. The degradation simulation model building method 200 comprises processes 210-245.

In flow 210, a planar p-type MOSFET100 as shown in fig. 1 is provided. In the present embodiment, the p-type MOSFET100 has a channel length Leff less than 100 nanometers, and the p-type MOSFET100 is surrounded by a shallow trench isolation region 140 having a linear nitride.

In flow 215, p-type MOSFET100 is measured to obtain first reliability degradation data. Specifically, in the present embodiment, the voltage between the source terminal 110 and the drain terminal 130 is greater than the voltage between the source terminal 110 and the gate terminal 120 of the p-type MOSFET 100. That is, the horizontal electric field from the source terminal 110 to the drain terminal 130 is greater than the vertical electric field from the gate terminal 120 to the source terminal 110. The first reliability degradation data is a relation with respect to a change in current with time, i.e., a current degradation as described above. Accordingly, the current from the source terminal 110 to the drain terminal 130 is measured to obtain the first reliability degradation data.

After measurement, first reliability degradation data is provided as shown in fig. 2.

Continuing with process 215, in process 220, a simulation model for the p-type MOSFET100 is selected to simulate the current degradation of the p-type MOSFET100, the selected model having modeling parameters related to the HEIP phenomenon. As a result of the simulation of the p-type MOSFET100, there will be modeling parameters for the selected model. The modeling parameters of the selected model are parameters that need to be input to control the simulation results of the selected model. In this embodiment, the simulation model selected is the BSIM4 model and takes into account the MOSRA, which may be MOSRA level 1 or MOSRA level 3.

Some of the modeling parameters of the selected model are physically related to the HEIP phenomenon. For example, in the present embodiment, the modeling parameters of the selected model include six HCI parameters, HCIN, HCID, HCIG, HCIEA, HCIM and HCIAP, but the parameters selected by the present invention are not limited thereto. In general, the HCI parameter used for degradation simulation of p-type MOSFETs is typically used to correct current in MOSRA.

Specifically, in the present embodiment, the HCI parameter HCIN is related to the application time, the HCI parameter HCID is related to the current trend, the HCI parameter HCIG is related to the voltage of the gate terminal 120, the HCI parameter HCIEA HCI is related to the thermal energy (e.g., the temperature of the p-type MOSFET 100), the parameter HCIM is related to the effective channel length of the p-type MOSFET100, and the HCI parameter HCIAP is related to the total magnitude of the current flowing from the source terminal 110 to the drain terminal 130 of the p-type MOSFET 100.

Proceed to flow 225. The HCI parameters HCIN, HCID, HCIG, HCIEA, HCIAP, and HCIAP of the modeling parameters that need to be input in the model are constructed by multiplying the degradation parameters (imaging parameters) by the control condition parameters (flags).

In particular, the entered HCI parameters HCIN, HCID, HCIG, HCIEA, HCIAP and HCIAP can be presented in the form of:

HCIN＝N1*flg1+N2*flg2+N3*flg3+N4*flg4

HCID＝D1*flg1+D2*flg2+D3*flg3+D4*flg4

HCIG＝G1*flg1+G2*flg2+G3*flg3+G4*flg4

HCIEA＝EA1*flg1+EA2*flg2+EA3*flg3+EA4*flg4

HCIM＝M1*flg1+M2*flg2+M3*flg3+M4*flg4

HCIAP＝AP1*flg1+AP2*flg2+AP3*flg3+AP4*flg4

as shown above, the degradation parameters include N1, N2, N3, N4, D1, D2, D3, D4, G1, G2, G3, G4, EA1, EA2, EA3, EA4, M1, M2, M3, M4, AP1, AP2, AP3, and AP4, and the control condition parameters include flg1, flg2, flg3, and flg 4. Although the six HCI parameters HCIN, HCID, HCIG, HCIEA, HCIM and HCIAP are modeling parameters in the conventional BSIM4 model considering MOSRA, the simulation results can be controlled by the degradation parameters.

Each of the control condition parameters flg1, flg2, flg3, and flg4 corresponds to a specific condition related to the operation of the p-type MOSFET100 in the event of the HEIP phenomenon. In the present embodiment, the control condition parameters flg1, flg2, flg3 and flg4 may be "1" or "0" to implement an on/off logic function.

For example, when the path length Leff is less than a selected length L1, the control condition parameter flg1 will be "1" to indicate that the control condition parameter flg1 is open. This corresponds to the p-type MOSFET100 to be simulated being a short channel p-type MOSFET. Conversely, when the path length Leff is greater than a selected length L1, the control condition parameter flg1 will be "0" to indicate shut-off.

Similarly, in the present embodiment, the control condition parameter flg2 is "1" when the voltage between the gate terminal 120 and the source terminal 110 is less than the specific voltage V1 and the voltage between the drain terminal 130 and the source terminal 110 is greater than the specific voltage V2. Otherwise, the control condition parameter flg2 is "0".

In contrast to the control condition parameter flg1, in this embodiment, the flag flg3 is "1" when the channel length Leff is greater than the selected length L1, otherwise the control condition parameter flg3 is "0". Similarly, when the voltage between the gate terminal 120 and the source terminal 110 is greater than or equal to the specific voltage V1 and the voltage difference between the drain terminal 130 and the source terminal 110 is less than or equal to the specific voltage V2, the control condition parameter flg4 is "1".

By controlling the setting of the condition parameters flg1 and flg2, when the simulated p-type MOSFET is a short channel p-type MOSFET and is operating when the HEIP phenomenon occurs, the HEIP phenomenon can be further considered in the simulation model by a set of degeneration parameters N1, N2, D1, D2, and so on. If the simulated p-type MOSFET is not a short channel p-type MOSFET, then the control condition parameters flg1 and flg2 are "0" and the control condition parameters flg3 and flg4 are set to "1" to enable to include another set of degeneration parameters N3, N4, D3, D4, etc. in the modeling parameters of the selected model.

The number of degradation parameters forming the HCI parameter among the modeling parameters of the selected model depends on the number of control condition parameters. In some embodiments, the number of control condition parameters is two, and the modeling parameter of each selected model includes two degradation parameters multiplied by the corresponding two control condition parameters.

After the simulation model is selected and the modeling parameters are constructed by multiplying the degradation parameters (e.g., N1, N2, N3, N4.. et al) by the control condition parameters (e.g., flg1, flg2, flg3, and flg4), flow 230 is entered. In flow 230, a simulation of p-type MOSFET100 is performed and each modeled parameter is composed of a portion of the degradation parameter multiplied by a conditional control parameter and used to control the degradation mechanism in the simulation of the selected model. When the simulation is complete, a second reliability degradation data may be provided corresponding to the current from the source terminal 110 to the drain terminal 130.

Continuing with process 230, in process 235, the first reliability degradation data and the second reliability degradation data are compared to determine whether the first reliability degradation data and the second reliability degradation data match. The first reliability degradation data and the second reliability degradation data are two curves relating to a change in current with time, respectively. In some embodiments, the difference between the first reliability degradation data and the second reliability degradation data at each application time point may be calculated, and the sum of the differences between the first reliability degradation data and the second reliability degradation data at each application time point may be used as a condition for determining whether there is a match.

In some embodiments, if the first reliability degradation data and the second reliability degradation data do not match, the sum of the differences corresponding to the first reliability degradation data and the second reliability degradation data at each time point is less than a predetermined value, and the process proceeds to the flow 240.

In process 240, the degradation parameters are updated, and then the process returns to process 225 and process 230 to perform a simulation of a new p-type MOSFET 100. Therefore, proceeding to block 235, in the case of new second reliability degradation data, the first reliability degradation data and the second reliability degradation data are compared again for a match. The process 235 is repeated until the first reliability degradation data and the second reliability degradation data match each other.

And under the condition that the first reliability degradation data and the second reliability degradation data are matched, the selected degradation parameters can show the HEIP phenomenon in the simulation. Accordingly, at block 245, a degradation simulation model may be created by collecting the degradation parameters. That is, for a specific condition where an HEIP phenomenon occurs, the HCI modeling parameters of the conventional simulation model can be directly replaced by the collected degradation parameters.

Specifically, when an integrated circuit including a short-channel p-type MOSFET needs to be simulated, the modeling parameters for the short-channel p-type MOSFET can be replaced by the collected degradation parameters multiplied by the control condition parameters, and the HEIP degradation phenomenon can be correctly expressed on the short channel in the integrated circuit.

In some embodiments, the collected degradation parameters may be the driving voltages for the source terminal 110, the gate terminal 120, and the drain terminal 130, the temperature of the p-type MOSFET, the channel length Leff, and the application time for the reliability test.

Fig. 5 shows a degradation performance measured from the short channel p-type MOSFET of fig. 1 and a corresponding simulation curve F generated by the degradation simulation modeling method of fig. 4. As shown in fig. 5, the curve F shows the degree of current degradation caused by the HEIP phenomenon, and the curve F matches the measured data points rather for the case where the current change from the source terminal 110 to the drain terminal 130 is first increased and then decreased.

FIG. 6 is a flow chart of another degradation simulation model building method 300 according to an embodiment of the invention.

The difference between the degradation simulation modeling method 300 of fig. 6 and the degradation simulation modeling method 200 of fig. 4 is that the HEIP behavior of the p-type MOSFET100 is provided by an additional fitting function rather than being input into the modeling parameters of a conventional simulation model.

Similar to the degradation modeling method 200, in a flow 310 of the degradation modeling method 300, a short channel planar p-type MOSFET100 for metrology is provided as shown in fig. 1. In the present embodiment, the p-type MOSFET100 has a channel length Leff less than 100 nanometers, and the p-type MOSFET100 is surrounded by a shallow trench isolation region 140 having a linear nitride. Proceeding to flow 315, p-type MOSFET100 is measured to obtain first reliability degradation data for the comparison.

In some embodiments, the first reliability degradation data is a change in current over time. Thus, the current from the source terminal 110 to the drain terminal 130 is measured to obtain the first reliability degradation data.

Proceeding to flow 320, a simulation model is selected for p-type MOSFET100 with additional modeling parameters for the degree of degradation. In some embodiments, the selected simulation model is the BSIM4 model.

Continuing to flow 325, a simulation of the p-type MOSFET100 is performed with the selected simulation model to obtain a simulated reliability degradation data. In general, the simulated reliability degradation data and the simulated first reliability degradation data do not match, and thus an additional function is required to correct the reliability degradation data. In some embodiments, the simulated degradation time period may be further set so that the first reliability degradation data can be fit for a specific time period, targeting a time period. Such a time period is referred to as a reliability period. For example, if the reliability period may be set to 1 second, then the fitting of the first reliability degradation data to the additional fitting function may be performed for time segments of application time of 0 to 1 second, 1 to 2 seconds, 2 to 3 seconds, and so on. In other words, this can also be considered as a local optimization fit of the fitting function for different time segments.

In flow 330, a fitting function is constructed with the degradation parameters related to the HEIP phenomenon. The fitting function is a trend for correcting the simulated reliability degradation data. The degradation parameter used to adjust the fitting function is related to the HEIP phenomenon of the short channel p-type MOSFET 100.

In particular, in some embodiments, the simulated reliability degradation data relates to current flow from the source terminal 110 to the drain terminal 130 over time. Thus, the fitting function may be, for example, a current variation function i (t) corresponding to the relationship of the current over time, thereby enabling to use the difference between the first reliability degradation data and the simulated reliability degradation data.

In some embodiments, the fitting function is the current change function i (t). The current variation function i (t) is a function that varies with time and can be presented in the following mathematical form:

the degradation parameter is set in the current variation function i (t). The degradation parameter includes A_pG, Ea, n and D.

The "switch" term in the current variation function I (t) is a control condition parameter configured to perform an on/off logic function to turn on or off the function of the current variation function I (t). The "switch" entry may be the number "0" or "1". If the HEIP phenomenon does not occur on the simulated element, the "switch" term can be configured to be "0", thereby disabling the current variation function i (t) by vanishing to 0.

The "type" term in the current variation function i (t) is a number related to the MOSFET type. V in the current variation function I (t)_GSThe "term is the voltage between the gate terminal 120 and the source terminal 110. The term "kT" in the current variation function i (T) is the energy term related to temperature in the p-type MOSFET, corresponding to the Boltzmann constant "k" multiplied by the temperature "T". The term "t" in the current variation function i (t) is the stress time of the reliability test. "V" in the current variation function I (t)_DSThe "term is the voltage between the source terminal 110 and the drain terminal 130. The term "Leff" in the current variation function i (t) is the channel length of the p-type MOSFET 100. In this embodiment, the channel length Leff is less than 100 nanometers.

Similarly, the degradation parameter A_pThe degradation parameter G is related to the voltage of the gate terminal 120, the degradation parameter Ea is related to the term "kT" with respect to temperature, the degradation parameter n is related to the stress time "t", and the degradation parameter D is related to the voltage between the source terminal 110 and the drain terminal 130, in relation to the overall magnitude of the current variation. The current variation function i (t) is controllable by the degradation parameters Ap, G, Ea and D.

By adjusting the degradation parameter, the current variation function i (t) can be controlled to modify the simulated reliability degradation data.

After the current change function i (t) is constructed as a fitting function, flow proceeds to block 335 for constructing second reliability degradation data by directly adding the simulated reliability degradation data to the current change function i (t) as a fitting function.

In this embodiment, the simulated reliability degradation data is the current degradation relative to the initial current measured for p-type MOSFET100 in flow 315. The degradation change function is formed by dividing the current change function i (t) by the initial current measured in flow 315. The second reliability degradation data is the simulated reliability degradation data directly added with a degradation change function converted from a current change function I (t).

In other words, the degradation parameter is used to modify the analog current relationship between the source and drain terminals of the p-type MOSFET100 by the current variation function i (t).

Continuing with flow 335, in flow 340, the first reliability degradation data is compared with the second reliability degradation data to determine whether the first reliability degradation data matches the second reliability degradation data. The first reliability degradation data and the second reliability degradation data are two curves related to the current change with time. Thus, for each point in time, a difference between the first reliability degradation data and the second reliability degradation data may be calculated.

If the first reliability degradation data does not match the second reliability degradation data, which may correspond to the sum of the differences between the first reliability degradation data and the second reliability degradation data at different time points not being less than a predetermined value, then flow 345 is entered.

In flow 345, the degradation parameters are updated and only the current change function i (t) as a fitting function is modified accordingly, but without re-providing new simulated reliability degradation data for p-type MOSFET 100. Then, the flow 330, 335 and 340 are proceeded again to reconstruct the second reliability degradation data and compare the first reliability degradation data with the new second reliability degradation data. As such, process 340 is repeated until the first reliability degradation data and the second reliability degradation data sufficiently match.

And under the condition that the first reliability degradation data and the second reliability degradation data are matched, the selected degradation parameters can show the HEIP phenomenon in the simulation. Accordingly, at flow 350, a degradation simulation model may be created by collecting degradation parameters. That is, for a specific condition where the HEIP phenomenon occurs, the simulation result obtained according to the conventional simulation model can be corrected by using the additional current variation function i (t). The current variation function i (t) may be controlled by a degeneration parameter.

In particular, when it is desired to simulate an integrated circuit comprising a short channel p-type MOSFET, the current of the short channel p-type MOSFET from the source terminal to the drain terminal can be obtained by simulating an additional fitting function of the current with a degradation parameter. Additional fitting functions such as the current change function i (t) described above.

In summary, the present invention provides two degradation model establishment methods, which take into account the HEIP phenomenon in two ways. In one of the degradation model building methods, included in the modeling parameters under a conventional simulation tool. And building the modeling parameters required and input by the original simulation by multiplying the degradation parameters by the corresponding control condition parameters. In another degradation modeling approach, the HEIP phenomenon is taken into account by an additional fitting function. Since the HEIP phenomenon can be taken into account in the degradation model building method disclosed by the present invention, the behavior of the semiconductor element can be simulated more accurately than in the conventional simulation model.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the embodiments of the invention without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the appended claims.