1. A method for observing signals inside an FPGA based on an observation hardware circuit is characterized by comprising the following steps:

determining a user circuit running on an FPGA chip, wherein the FPGA chip internally comprises programmable logic resources and an observation hardware circuit, the observation hardware circuit comprises an observation point and an observation pin, the observation point is connected to the observation pin through an observation line, and the observation point in the observation hardware circuit is an output port of the programmable logic resources in the FPGA chip;

taking the circuit structure layout of the signal to be observed generated in the user circuit at the observation point as a constraint condition, generating a configuration code stream corresponding to the user circuit based on the programmable logic resource in the FPGA chip under the constraint condition, and loading the configuration code stream onto the FPGA chip;

the FPGA chip forms the user circuit based on the configuration code stream, and the observation pin is used for observing a signal to be observed at the observation point in the operation process of the user circuit.

2. The method of claim 1, wherein the observation hardware circuit comprises a plurality of observation points, and then the observation hardware circuit further comprises a path gating circuit and a multi-bit register, each observation point is connected to the observation pin through a different path inside the path gating circuit, the multi-bit register is connected to the debug pin, and the multi-bit register is connected to and controls the on/off of the different paths in the path gating circuit;

when generating a configuration code stream corresponding to a user circuit, laying out a circuit structure of the signal to be observed of the user circuit at one observation point as a constraint condition; in the operation process of the user circuit, the multi-bit register outputs a corresponding gating signal according to a debugging instruction acquired from the debugging pin, controls the path gating circuit to gate a path between an observation point corresponding to the signal to be observed and the observation pin, and observes the selected alternative signal to be observed, wherein each signal bit of the gating signal corresponds to one observation point.

3. The method of claim 2,

the path gating circuit comprises a multiplexer, wherein the input end of the multiplexer is respectively connected with each observation point, and the output end of the multiplexer is connected with the observation pin;

or, the path gating circuit comprises a plurality of sequentially cascaded multiplexers, the input end of each first-stage multiplexer is connected with each corresponding observation point, and the output end of the last-stage multiplexer is connected with the observation pin.

4. A method according to claim 3, wherein when the path gating circuitry comprises a plurality of cascaded multiplexers, each multiplexer of the first stage and its respective observation point of the corresponding connection are within a predetermined area.

5. The method according to claim 3, wherein when all observation points are arranged in a row-column structure inside the FPGA chip, the first-level multiplexers are arranged to form a row-column structure, and each observation point correspondingly connected to each first-level multiplexer is located in the same row-column structure or in a plurality of continuous row-column structures.

6. The method of claim 5, wherein when all observation points are arranged in a row-column structure inside the FPGA chip, a plurality of programmable logic resources are spaced between every two adjacent observation points.

7. The method of claim 2, wherein the path gating circuit is a two-dimensional switch array formed by a plurality of switch tubes, the two-dimensional switch array comprises a plurality of input terminals and an output terminal, each input terminal of the two-dimensional switch array is connected to an observation point, and each output terminal of the two-dimensional switch array is connected to the observation pin.

8. The method according to claim 3 or 7, wherein when the path gating circuit comprises a plurality of multiplexers or a plurality of switch tubes, the observation hardware circuit comprises a multi-bit register respectively connected to each controlled device, or comprises a plurality of multi-bit registers, each multi-bit register respectively connected to a corresponding plurality of controlled devices, and the controlled devices are multiplexers or switch tubes.

9. The method of any one of claims 2-7, wherein the debug pin is a dynamically reconfigurable port of the FPGA chip or a boundary scan port of a boundary scan chain.

10. The method according to any one of claims 2 to 7, wherein the programmable logic resources inside the FPGA chip at least comprise a programmable module and an interconnection resource module, and the observation point in the observation hardware circuit comprises an output port of the programmable module and/or an output port of a winding box in the interconnection resource module.

11. The method of claim 10,

part of output ports of all programmable modules in the FPGA chip are used as the observation points, or part of output ports of part of programmable modules in the FPGA chip are used as the observation points;

and partial output ports of all winding boxes in the FPGA chip are used as the observation points, or partial output ports of partial winding boxes in the FPGA chip are used as the observation points.

12. The method according to any one of claims 2 to 7,

and the observation line from each observation point to the observation pin has preset observation time delay.

13. The method of claim 12,

the difference between the observed time delays of any two observed lines is less than a predetermined threshold.

Background

When a user circuit is implemented on an FPGA and normally operates on the FPGA, in order to determine that an operation process of the user circuit on the FPGA is correct and conforms to a design concept, it is generally required to observe behaviors or waveforms of certain specific signals inside the user circuit.

At present, a user circuit is implemented on an FPGA and layout and routing are completed, and at this time, part of resources inside the FPGA are occupied by the user circuit, but part of the resources are still left unused. And then selecting a signal to be observed of the user circuit, wherein the signal to be observed corresponds to the internal layout wiring resource of the FPGA, and connecting the signal to be observed to an unoccupied pin as an observation pin through the unoccupied winding resource in the FPGA. And adding the selected winding path of the signal to be observed and the observation pin into the layout wiring of the user circuit to form new layout wiring, downloading a code stream generated by the new layout wiring to the FPGA for normal operation, and observing the signal to be observed by the observation pin at the moment.

However, in this method, if there is no unoccupied pin available after the FPGA implements the user circuit, or the signal to be observed cannot be connected to the corresponding pin by using the unoccupied winding resources, the above-mentioned functions cannot be implemented, so that the existing method is limited, and it cannot be guaranteed that the signal to be observed is successfully observed each time.

Disclosure of Invention

The invention provides a method for observing signals in an FPGA (field programmable gate array) based on an observation hardware circuit aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

a method for observing FPGA internal signals based on an observation hardware circuit comprises the following steps:

determining a user circuit running on an FPGA chip, wherein the FPGA chip internally comprises programmable logic resources and an observation hardware circuit, the observation hardware circuit comprises an observation point and an observation pin, the observation point is connected to the observation pin through an observation line, and the observation point in the observation hardware circuit is an output port of the programmable logic resources in the FPGA chip;

taking the circuit structure layout of a signal to be observed generated in a user circuit at an observation point as a constraint condition, generating a configuration code stream corresponding to the user circuit based on programmable logic resources in an FPGA chip under the constraint condition, and loading the configuration code stream onto the FPGA chip;

the FPGA chip forms a user circuit based on the configuration code stream, and the signal to be observed at the observation point is observed through the observation pin in the operation process of the user circuit.

The observation hardware circuit also comprises a path gating circuit and a multi-bit register, wherein each observation point is connected to an observation pin through different paths in the path gating circuit, the multi-bit register is connected with a debugging pin, and the multi-bit register is connected with the debugging pin and controls the connection and disconnection of different paths in the path gating circuit;

when generating the configuration code stream corresponding to the user circuit, laying out the circuit structure of the signal to be observed of the user circuit at one observation point as a constraint condition; in the operation process of the user circuit, the multi-bit register outputs a corresponding gating signal according to a debugging instruction acquired from a debugging pin, controls a path gating circuit to gate a path between an observation point corresponding to a signal to be observed and the observation pin, and observes a selected alternative signal to be observed, wherein each signal bit of the gating signal corresponds to one observation point.

The path gating circuit comprises a multiplexer, wherein the input end of the multiplexer is respectively connected with each observation point, and the output end of the multiplexer is connected with an observation pin;

or the path gating circuit comprises a plurality of sequentially cascaded multiplexers, the input end of each first-stage multiplexer is respectively connected with each corresponding observation point, and the output end of the last-stage multiplexer is connected with the observation pin.

According to a further technical scheme, when the path gating circuit comprises a plurality of cascaded multiplexers, each first-level multiplexer and each observation point correspondingly connected with the first-level multiplexer are located in a preset area range.

According to a further technical scheme, when all observation points are arranged in a row-column structure in an FPGA chip, the multi-path selectors of all the first levels are arranged to form a row-column structure, and the observation points correspondingly connected with the multi-path selectors of all the first levels are located in the same row-column structure or in a plurality of continuous row-column structures.

According to a further technical scheme, when all observation points are arranged in a row-column structure in an FPGA chip, a plurality of programmable logic resources are arranged between every two adjacent observation points.

The path gating circuit is a two-dimensional switch array formed by a plurality of switch tubes, the two-dimensional switch array comprises a plurality of input ends and an output end, each input end of the two-dimensional switch array is respectively connected with an observation point, and the output end of the two-dimensional switch array is connected with an observation pin.

According to a further technical scheme, when the path selection circuit comprises a plurality of multiplexers or a plurality of switching tubes, the observation hardware circuit comprises a multi-bit register which is respectively connected to each controlled device, or the observation hardware circuit comprises a plurality of multi-bit registers, each multi-bit register is respectively connected to a corresponding plurality of controlled devices, and the controlled devices are the multiplexers or the switching tubes.

The further technical scheme is that the debugging pin is a dynamic reconfigurable port of an FPGA chip or a boundary scanning port of a boundary scanning chain.

The technical scheme is that the programmable logic resources in the FPGA chip at least comprise a programmable module and an interconnection resource module, and the observation point in the observation hardware circuit comprises an output port of the programmable module and/or an output port of a winding box in the interconnection resource module.

The method has the further technical scheme that partial output ports of all programmable modules in the FPGA chip are used as observation points, or partial output ports of partial programmable modules in the FPGA chip are used as observation points;

and partial output ports of all winding boxes in the FPGA chip are used as observation points, or partial output ports of partial winding boxes in the FPGA chip are used as observation points.

The further technical scheme is that an observation line from each observation point to an observation pin has preset observation time delay.

The further technical scheme is that the difference value between the observation time delays of any two observation lines is smaller than a preset threshold value.

The beneficial technical effects of the invention are as follows:

the method is realized by carrying out hardware improvement design on an FPGA chip and combining with corresponding software function configuration, an independent observation hardware circuit is added into the FPGA chip, and the position of an observation point in the observation hardware circuit is taken as a constraint condition of the layout position of a signal to be observed to generate a configuration code stream.

Drawings

Fig. 1 is a schematic structural diagram of an observation hardware circuit in one embodiment of the present application.

Fig. 2 is a schematic structural diagram of an observation hardware circuit in another embodiment of the present application.

Fig. 3 is a schematic structural diagram of an observation hardware circuit in another embodiment of the present application.

Fig. 4 is a schematic structural diagram of an observation hardware circuit in another embodiment of the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses a method for observing FPGA internal signals based on an observation hardware circuit, which is realized based on hardware improvement design of an FPGA chip and corresponding software function configuration, and is divided into two parts to be respectively introduced:

firstly, improving and designing the hardware of an FPGA chip.

Besides conventional programmable logic resources, the FPGA chip in the application also designs a special observation hardware circuit, namely, additionally adds hardware resources. The observation hardware circuit comprises an observation point, an observation pin and an observation line, wherein the observation point is connected to the observation pin through the special observation line, and the observation point in the observation hardware circuit is an output port of the programmable logic resource in the FPGA chip. The observation hardware circuit is a hardware resource manufactured and realized based on a conventional circuit component, so that the observation hardware circuit can be realized by adopting a conventional FPGA manufacturing process.

The programmable logic resources in the FPGA chip at least comprise a programmable module and an interconnection resource module, wherein the programmable module comprises a CLB (basic logic unit), a BRAM (branch-tree-based memory), an IOB (input/output bus), a DSP (digital signal processor), a PC (personal computer) and the like, the interconnection resource module comprises a winding box and an interconnection line, and an observation point in an observation hardware circuit is an output port of the programmable module or an output port of the winding box in the interconnection resource module. As shown in fig. 1, the existing FPGA chip generally adopts a Column-Based architecture, and the programmable logic resources 1 are arranged in the FPGA chip according to a determinant structure, so that an observation point 2 for setting a hardware resource at an output port of any programmable logic resource 1 can be selected as required, and is connected to an observation pin 4 through a special observation line 3.

The observation line 3 from the observation point 2 to the observation pin 4 has a preset observation time delay, and the observation time delay can be adjusted by adjusting the arrangement position of the observation point and/or the observation pin and/or adjusting the winding mode of the observation line, so that the observation time delay meets the preset requirement.

And secondly, correspondingly configuring software.

Based on the FPGA chip with the built-in special observation hardware circuit, the user circuit running on the FPGA chip is determined, and the user circuit is a circuit structure which needs to be realized by utilizing programmable logic resources in the FPGA chip and is used for realizing user design functions. And laying out a circuit structure of a signal to be observed, which is generated in the user circuit, at an observation point as a constraint condition, and carrying out layout and wiring based on programmable logic resources in the FPGA chip under the constraint condition so as to generate a configuration code stream corresponding to the user circuit. For example, in fig. 1, a circuit structure of a signal to be observed generated in a user circuit is laid out at observation point 2, and is implemented by programmable logic resource a at observation point 2. And after the configuration code stream is obtained, loading the configuration code stream onto an FPGA chip, wherein the FPGA chip forms a corresponding user circuit based on the configuration code stream, and a signal to be observed in the user circuit is realized by a programmable logic resource at an observation point, so that the signal to be observed is transmitted to the outside of the FPGA chip for observation through the observation point at the output port of the programmable logic resource where the signal to be observed is located and a special observation line connected to an observation pin. Therefore, the observation hardware circuit is used for observing the signal to be observed at the observation point in the operation process of the user circuit, the phenomenon that no idle programmable logic resource is available for realizing the observation function can be effectively avoided, and the continuous and stable realization of the online observation function is ensured.

In another embodiment, the observation hardware circuit added in the FPGA chip comprises a plurality of observation points, and in the embodiment, the observation points in the observation hardware circuit comprise an output port of the programmable module and/or an output port of a winding box in the interconnection resource module. Specifically, part of the output ports of all the programmable modules in the FPGA chip may be used as observation points, or part of the output ports of part of the programmable modules in the FPGA chip may be used as observation points. Correspondingly, partial output ports of all winding boxes in the FPGA chip can be used as observation points, or partial output ports of partial winding boxes in the FPGA chip can be used as observation points. In a special case, all the output ports of all the programmable modules and all the output ports of all the wire winding boxes can be used as observation points, and all the output ports of all the programmable logic resources are used as observation points, so that when a configuration code stream corresponding to a user circuit is generated, a signal to be observed is randomly laid at any position and can meet the condition of laying at the observation points, and then, a constraint condition of laying and wiring is not needed to be set, but the problems of too many observation points, too much complexity of the circuit, repeated coverage and no need of such operation are caused.

Optionally, under the condition that there are multiple observation points, there are multiple distribution modes of all observation points inside the FPGA chip, including random distribution, or distribution in several areas according to areas, or arrangement according to a row-column structure. When all observation points are arranged in a row-column structure in the FPGA chip, a plurality of programmable logic resources are arranged between every two adjacent observation points, and the intervals between different observation points can be the same or different. As shown in fig. 2, taking the observation points distributed in regions on the FPGA chip as an example, the observation points are distributed in 4 regions, and each region includes 4 observation points. Fig. 3 illustrates an example in which observation points are arranged in a row-column structure in an FPGA chip, two programmable logic resources are spaced between two adjacent observation points in the same row, and one programmable logic resource is spaced between two adjacent observation points in the same column.

In this embodiment, the observation hardware circuit further includes a path gating circuit and a multi-bit register, each observation point is connected to the observation pin through a different path inside the path gating circuit, the multi-bit register is connected to the debug pin 5, and the multi-bit register is connected to the path gating circuit and controls on/off of different paths in the path gating circuit according to a debug instruction input by the debug pin.

In this embodiment, based on such a hardware structure, when generating a configuration code stream corresponding to a user circuit, a circuit structure layout of a signal to be observed of the user circuit is used as a constraint condition at one of the observation points. In the operation process of the user circuit, the multi-bit register outputs a corresponding gating signal according to a debugging instruction acquired from a debugging pin, controls a path gating circuit to gate a path between an observation point corresponding to a signal to be observed and the observation pin, and observes a selected alternative signal to be observed, wherein each signal bit of the gating signal corresponds to one observation point.

The embodiment is very suitable for the condition that a plurality of alternative signals to be observed possibly need to be observed exist in the user circuit, the circuit structures of the alternative signals to be observed possibly in the user circuit are respectively distributed at each observation point to be used as constraint conditions to generate configuration code streams, in the operation process of the user circuit, one of all the alternative signals to be observed is selected to be used as the signal to be observed actually and generates a corresponding debugging instruction to be input through a debugging pin, the multi-bit register outputs a corresponding gating signal according to the debugging instruction acquired from the debugging pin, and the path gating circuit is controlled to gate the path between the observation point corresponding to the signal to be observed actually need to be observed and the observation pin. When other alternative signals to be observed need to be replaced as the actual signals to be observed, a new debugging instruction is generated, the content of the multi-bit register is updated, and the path gating circuit is controlled to gate the corresponding path. However, since the number of observation points is large, the bit width of the multi-bit register is usually large, and in order to increase the data update speed of the multi-bit register, a scan chain or a multi-bit wide bus is generally used to read and write the multi-bit register, but even this is true, in this embodiment, the content update speed of the multi-bit register is difficult to achieve the real-time requirement, and a certain time delay exists during switching, so it is difficult to rapidly control the path gating circuit to switch the path.

In this embodiment, each observation line from each observation point to the observation pin has a respective predetermined observation time delay, and optionally, a difference between the observation time delays of any two observation lines is smaller than a predetermined threshold.

In this embodiment, the debug pin may be a dedicated pin that is set separately, like the observation pin, or may multiplex an existing pin on the FPGA chip. When the debug pin multiplexes the existing pin on the FPGA chip, the debug pin is a Dynamic Reconfiguration Port (DRP) of the FPGA chip or a boundary scan Port of a boundary scan chain.

In this embodiment, the path gating circuit has a plurality of different implementations, which are respectively described as follows:

implementation mode 1: in one embodiment, the path gating circuit comprises a multiplexer, wherein the input end of the multiplexer is respectively connected with each observation point, the output end of the multiplexer is connected with the observation pin, and the multi-bit register is connected with the selection control end of the multiplexer.

Implementation mode 2: in another embodiment, the path gating circuit includes a plurality of multiplexers that are sequentially cascaded, an input terminal of each first-stage multiplexer is connected to each corresponding observation point, an output terminal of each first-stage multiplexer is connected to an input terminal of a next-stage multiplexer, and sequentially connected to an input terminal of a last-stage multiplexer, an output terminal of the last-stage multiplexer is connected to the observation pin, and the multi-bit register is connected to the selection control terminals of the multiplexers at each stage. As shown in both fig. 2 and 3, the path gating circuit includes multiplexers cascaded in two stages.

When the path gating circuit includes a plurality of cascaded multiplexers, the arrangement positions of the multiplexers at each level may be distributed as desired, for example, it is common that the first-stage multiplexer directly connected to each observation point is arranged near the connected observation point, and the last-stage multiplexer is arranged near the observation pin. In one embodiment, the observation points are distributed in the FPGA chip according to regions, that is, the observation points are distributed in a plurality of different regions, so that the observation points in each predetermined region range can be configured to be correspondingly connected to the same first-level multiplexer, and each first-level multiplexer and each observation point correspondingly connected thereto are located in the predetermined region range, as shown in fig. 2. In another embodiment, the observation points are arranged in a row-column structure inside the FPGA chip, the first-level multiplexers are arranged to form a row-column structure, and the observation points correspondingly connected to each first-level multiplexer are located in the same row-column structure or in a plurality of continuous row-column structures, as shown in fig. 3. Except the first-stage and last-stage multiplexers, the middle-stage multiplexers can be arranged at corresponding positions according to actual needs.

Implementation mode 3: in another embodiment, the path gating circuit is a two-dimensional switch array formed by a plurality of switch tubes, the two-dimensional switch array comprises a plurality of input ends and an output end, each input end of the two-dimensional switch array is respectively connected with an observation point, the output end of the two-dimensional switch array is connected with an observation pin, and the multi-bit register is connected with and controls the on-off of each switch tube so as to enable different input ends to be communicated with the output end. The switching tubes may be implemented by MOS tubes, the two-dimensional switch array includes a plurality of first gating MOS tubes and second gating MOS tubes, a source of each first gating MOS tube is connected to an observation point as an input end of the two-dimensional switch array, a drain of each first gating MOS tube is connected to a source of a corresponding second gating MOS tube, a drain of each second gating MOS tube is connected to the observation pin, and the multi-bit register is connected to gates of each first gating MOS tube and each second gating MOS tube, as shown in fig. 4.

In the foregoing implementation mode 2 or implementation mode 3, when the path selection circuit includes a plurality of multiplexers or a plurality of switching tubes, the observation hardware circuit includes a multi-bit register respectively connected to each controlled device, or the observation hardware circuit includes a plurality of multi-bit registers, each multi-bit register is respectively connected to a corresponding plurality of controlled devices, and each controlled device is a multiplexer or a switching tube. For example, as shown in fig. 2, the observation hardware circuit includes a multi-bit register connected to each controlled device, and the multi-bit selector is connected to all 5 multiplexers to provide SEL. As an example of the observation hardware circuit shown in fig. 3 including the multi-bit register 1 and the multi-bit register 2, the multi-bit register 1 is connected to three multiplexers of the first stage and supplies SEL1, and the multi-bit register 2 is connected to a multiplexer of the second stage, that is, the last stage and supplies SEL 2. As shown in fig. 4, taking an example that the observation hardware circuit includes a multi-bit register 1 and a multi-bit register 2, the multi-bit register 1 is connected to each first gate MOS transistor and provides SEL1, and the multi-bit register 2 is connected to each second gate MOS transistor and provides SEL 2. It should be noted that when there are a plurality of multi-bit registers, the corresponding multi-bit registers may be divided according to the function of the controlled device or the cascade hierarchy where the controlled device is located according to the above example, or may not be arranged in this way.