1. A method for observing different signals in an FPGA in a time-sharing manner based on a shared pin is characterized by comprising the following steps:

determining a user circuit running on an FPGA chip, wherein the FPGA chip internally comprises programmable logic resources and an observation hardware circuit, the observation hardware circuit comprises a plurality of observation points, an output multiplexer and observation pins, each observation point is respectively a different output port of the programmable logic resources in the FPGA chip, and each observation point is connected to the observation pins through a different path in the output multiplexer;

respectively laying out circuit structures of a plurality of signals to be observed, which are generated in the user circuit, at each observation point as constraint conditions, generating configuration code streams corresponding to the user circuit based on programmable logic resources in the FPGA chip under the constraint conditions, and loading the configuration code streams onto the FPGA chip;

the FPGA forms the user circuit based on the configuration code stream, the output multiplexer acquires a switching signal and switches on a path between an observation point corresponding to a corresponding signal to be observed and the observation pin according to the switching signal, so that the observation pin switches and outputs observation results of different signals to be observed, time-sharing output observation of N signals to be observed at the input end of the output multiplexer is realized, and N is more than or equal to 2.

2. The method of claim 1,

the observation hardware circuit also comprises a switching pin which is connected with the control signal end of the output multiplexer and provides a switching signal input from the exterior of the FPGA chip in real time.

3. The method of claim 2,

and when the output multiplexer outputs different signals to be observed according to different switching signals, the output multiplexer switches and outputs each signal to be observed for multiple times according to the same switching sequence, or switches and outputs each signal to be observed for multiple times according to at least two different switching sequences.

4. The method of claim 1,

the output multiplexer adopts a one-hot coding mode, the observation hardware circuit further comprises a shift register pre-stored with a plurality of different switching signals with a preset cyclic sequence, and the output end of the shift register is connected with the control signal end of the output multiplexer and sequentially switches and outputs different switching signals to the output multiplexer according to a shift clock and the preset cyclic sequence.

5. The method of claim 4, further comprising:

and decomposing the output signals of the observation pins according to time intervals by taking the switching signals as a time sequence basis, and respectively restoring to obtain the observation results of the signals to be observed.

6. The method of claim 5,

and the shift clock used by the shift register is N times of the system clock of the signal to be observed, and the frequency of each observation result obtained by decomposition is the same as the frequency of the signal to be observed.

7. The method of claim 1,

the output observation time lengths of the signals to be observed are equal, or the output observation time lengths of at least two signals to be observed are unequal.

8. The method of claim 1,

and the observation line from each observation point to the observation pin has preset observation time delay.

9. The method of claim 8,

the difference between the observed time delays of any two observed lines is less than a predetermined threshold.

10. The method according to any one of claims 1 to 9, wherein the observation hardware circuit includes a number of observation points M > N, and then the observation hardware circuit further includes an intermediate gating circuit, a multi-bit register, and a debug pin, wherein M observation points are connected to N inputs of the output multiplexer through different conduction paths of the intermediate gating circuit, and the multi-bit register controls the conduction paths of the intermediate gating circuit to transmit signals at N observation points of the M observation points to the inputs of the output multiplexer as the N signals to be observed according to a debug instruction obtained from the debug pin.

11. The method of claim 10,

the debugging pin is a dynamic reconfigurable port of the FPGA chip or a boundary scanning port of a boundary scanning chain.

12. The method of claim 10,

the intermediate gating circuit comprises a plurality of multiplexers, the multi-bit register is connected with the control signal end of each multiplexer, each first-stage multiplexer is correspondingly connected with a plurality of observation points, and each first-stage multiplexer is directly connected with or connected to the input end of the output multiplexer through a plurality of other multiplexers forming a cascade structure; each first-level multiplexer and each observation point correspondingly connected with the first-level multiplexer are located in a preset area range, or all the observation points are arranged in the FPGA chip according to a row-column structure, each first-level multiplexer is arranged to form the row-column structure, and each observation point correspondingly connected with each first-level multiplexer is located in the same row-column structure or a plurality of continuous row-column structures.

13. The method of claim 10,

the middle gating circuit comprises a plurality of MOS tubes, the source electrode of each MOS tube is correspondingly connected with an observation point, each input end of the output multiplexer is connected with the drain electrodes of the MOS tubes, and the multi-position register is connected with the grid electrode of each MOS tube to control the on-off of the MOS tube.

Background

When a user circuit is implemented on an FPGA and normally operates on the FPGA, in order to determine that an operation process of the user circuit on the FPGA is correct and conforms to a design concept, it is generally required to observe behaviors or waveforms of certain specific signals inside the user circuit.

At present, a user circuit is implemented on an FPGA and layout and routing are completed, and at this time, part of resources inside the FPGA are occupied by the user circuit, but part of the resources are still left unused. And then selecting a signal to be observed of the user circuit, wherein the signal to be observed corresponds to the internal layout wiring resource of the FPGA, and connecting the signal to be observed to an unoccupied pin as an observation pin through the unoccupied winding resource in the FPGA. And adding the selected winding path of the signal to be observed and the observation pin into the layout wiring of the user circuit to form new layout wiring, downloading a code stream generated by the new layout wiring to the FPGA for normal operation, and observing the signal to be observed by the observation pin at the moment.

However, in this method, if there is no unoccupied pin available after the FPGA implements the user circuit, or the signal to be observed cannot be connected to the corresponding pin by using the unoccupied winding resources, the above-mentioned functions cannot be implemented, so that the existing method is limited, and it cannot be guaranteed that the signal to be observed is successfully observed each time.

Disclosure of Invention

The invention provides a method for observing different signals in an FPGA (field programmable gate array) in a time-sharing manner based on a shared pin aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

a method for observing different signals in an FPGA (field programmable gate array) in a time-sharing manner based on a shared pin comprises the following steps:

determining a user circuit running on an FPGA chip, wherein the FPGA chip internally comprises programmable logic resources and an observation hardware circuit, the observation hardware circuit comprises a plurality of observation points, an output multiplexer and observation pins, each observation point is respectively a different output port of the programmable logic resources in the FPGA chip, and each observation point is connected to the observation pins through a different path in the output multiplexer;

respectively laying out circuit structures of a plurality of signals to be observed, which are generated in a user circuit, at each observation point as constraint conditions, generating configuration code streams corresponding to the user circuit based on programmable logic resources in an FPGA chip under the constraint conditions, and loading the configuration code streams onto the FPGA chip;

the FPGA forms a user circuit based on the configuration code stream, the output multiplexer acquires the switching signal and switches on a path between an observation point corresponding to the corresponding signal to be observed and an observation pin according to the switching signal, so that the observation pin switches and outputs different observation results of the signal to be observed, time-sharing output observation of N signals to be observed at the input end of the output multiplexer is realized, and N is more than or equal to 2.

The further technical scheme is that the observation hardware circuit further comprises a switching pin, and the switching pin is connected with a control signal end of the output multiplexer and provides a switching signal input from the exterior of the FPGA chip in real time.

The further technical scheme is that when the output multiplexer outputs different signals to be observed according to different switching signals, the output multiplexer switches and outputs each signal to be observed for multiple times according to the same switching sequence, or switches and outputs each signal to be observed for multiple times according to at least two different switching sequences.

The output multiplexer adopts a one-hot coding mode, the observation hardware circuit also comprises a shift register pre-stored with a plurality of different switching signals with preset cyclic sequence, and the output end of the shift register is connected with the control signal end of the output multiplexer and sequentially switches and outputs different switching signals to the output multiplexer according to the shift clock and the preset cyclic sequence.

The further technical scheme is that the method also comprises the following steps:

and decomposing the output signals of the observation pins according to time intervals by taking the switching signals as a time sequence basis, and respectively restoring to obtain the observation results of the signals to be observed.

The further technical scheme is that a shift clock used by the shift register is N times of a system clock of the signal to be observed, and the frequency of each observation result obtained by decomposition is the same as the frequency of the signal to be observed.

The further technical scheme is that the output observation time lengths of the signals to be observed are equal, or the output observation time lengths of at least two signals to be observed are unequal.

The further technical scheme is that an observation line from each observation point to an observation pin has preset observation time delay.

The further technical scheme is that the difference value between the observation time delays of any two observation lines is smaller than a preset threshold value.

The further technical scheme is that the observation hardware circuit comprises observation points, wherein the number M of the observation points is larger than N, the observation hardware circuit further comprises an intermediate gating circuit, a multi-bit register and a debugging pin, the M observation points are connected to N input ends of the output multiplexer through different conduction paths of the intermediate gating circuit, and the multi-bit register controls the conduction paths of the intermediate gating circuit according to a debugging instruction acquired from the debugging pin to transmit signals at the N observation points in the M observation points to the input end of the output multiplexer to serve as N signals to be observed.

The further technical scheme is that the debugging pin is a dynamic reconfigurable port of an FPGA chip or a boundary scanning port of a boundary scanning chain.

The intermediate gating circuit comprises a plurality of multiplexers, a multi-bit register is connected with the control signal end of each multiplexer, each first-stage multiplexer is correspondingly connected with a plurality of observation points, and each first-stage multiplexer is directly connected or connected to the input end of an output multiplexer through a plurality of other multiplexers forming a cascade structure; each first-level multiplexer and each observation point correspondingly connected with the first-level multiplexer are located in a preset area range, or all the observation points are arranged in the FPGA chip according to a row-column structure, each first-level multiplexer is arranged to form the row-column structure, and each observation point correspondingly connected with each first-level multiplexer is located in the same row-column structure or located in a plurality of continuous row-column structures.

The intermediate gating circuit comprises a plurality of MOS tubes, the source electrode of each MOS tube is correspondingly connected with an observation point, each input end of the output multiplexer is connected with the drain electrodes of the plurality of MOS tubes, and the multi-bit register is connected with the grid electrodes of the MOS tubes to control the on-off of the MOS tubes.

The beneficial technical effects of the invention are as follows:

the application discloses a method for observing different signals in an FPGA (field programmable gate array) at different times based on a shared pin, which is realized by carrying out hardware improvement design on an FPGA chip and combining with corresponding software function configuration together, an independent observation hardware circuit is added in the FPGA chip, and a configuration code stream is generated by taking the position of an observation point in the observation hardware circuit as a constraint condition of the layout position of a signal to be observed, in the operation process of a user circuit, a multiplexer is output to switch and observe the signal to be observed at different observation points according to a switching signal, so that the function of observing different signals at different times based on one observation pin can be realized, the observation has stability, and the real-time performance of the switching process is better.

Drawings

FIG. 1 is a circuit diagram of observation hardware circuitry in one embodiment.

Fig. 2 is a circuit diagram of an observation hardware circuit in another embodiment.

Fig. 3 is a circuit diagram of the observation hardware circuit in another embodiment based on fig. 2.

Fig. 4 is a circuit diagram of the observation hardware circuit in another embodiment based on fig. 2.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses a method for observing different signals in an FPGA (field programmable gate array) at different times based on a shared pin, which is realized based on hardware improvement design of an FPGA chip and corresponding software function configuration, and is divided into two parts to be introduced respectively:

firstly, improving and designing the hardware of an FPGA chip.

Besides conventional programmable logic resources, the FPGA chip in the application also designs a special observation hardware circuit, namely, additionally adds hardware resources. The observation hardware circuit comprises a plurality of observation points, an output multiplexer and observation pins, wherein each observation point is respectively a different output port of the programmable logic resource in the FPGA chip, and each observation point is connected to the observation pins through different paths in the output multiplexer. The observation hardware circuit is a hardware resource manufactured and realized based on a conventional circuit component, so that the observation hardware circuit can be realized by adopting a conventional FPGA manufacturing process.

Optionally, the observation point in the observation hardware circuit includes an output port of the programmable module and/or an output port of the winding box in the interconnection resource module. Specifically, part of the output ports of all the programmable modules in the FPGA chip may be used as observation points, or part of the output ports of part of the programmable modules in the FPGA chip may be used as observation points. Correspondingly, partial output ports of all winding boxes in the FPGA chip can be used as observation points, or partial output ports of partial winding boxes in the FPGA chip can be used as observation points. In a special case, all outlets of all programmable modules and all outlets of all winding boxes can be taken as observation points, and all outlets of all programmable logic resources can be taken as observation points, but this results in too many observation points, too complicated circuits, and problems of repeated coverage, which are not necessary and therefore usually not done so.

Optionally, under the condition that there are multiple observation points, there are multiple distribution modes of all observation points inside the FPGA chip, including random distribution, or distribution in several areas according to areas, or arrangement according to a row-column structure. When all observation points are arranged in a row-column structure in the FPGA chip, a plurality of programmable logic resources are arranged between every two adjacent observation points, and the intervals between different observation points can be the same or different. Taking a Column-Based architecture commonly adopted by an existing FPGA chip as an example, the programmable logic resources 1 are arranged in the FPGA chip according to a determinant structure, and as shown in fig. 1, the observation points 2 are distributed in two regions, each of which includes 4 observation points 2, by taking the example that the observation points 2 are distributed in the FPGA chip according to the regions. Fig. 2 illustrates that observation points 2 are arranged in a row-column structure on an FPGA chip, two programmable logic resources 1 are spaced between two adjacent observation points 2 in the same row, and one programmable logic resource 1 is spaced between two adjacent observation points 2 in the same column.

The observation points 2 share one observation pin 4 and form different observation lines through different paths in the output multiplexer 3, and each observation point 2 to observation pin 4 observation line has a predetermined observation time delay. Optionally, a difference between the observed time delays of any two observed lines is smaller than a predetermined threshold.

And secondly, correspondingly configuring software.

Based on the FPGA chip with the built-in special observation hardware circuit, the user circuit running on the FPGA chip is determined, the user circuit is a circuit structure which needs to be realized by utilizing programmable logic resources in the FPGA chip and is used for realizing user design functions, the user circuit comprises a plurality of signals to be observed, and the application can realize time-sharing observation of the plurality of signals to be observed by utilizing one observation pin.

When the method is realized, circuit structures of a plurality of signals to be observed, which are generated in a user circuit, are respectively distributed at each observation point to serve as constraint conditions, and configuration code streams corresponding to the user circuit are generated based on programmable logic resources in the FPGA chip under the constraint conditions and are loaded on the FPGA chip. And after the configuration code stream is obtained, loading the configuration code stream onto an FPGA chip, forming a corresponding user circuit by the FPGA chip based on the configuration code stream, and realizing a signal to be observed in the user circuit by a programmable logic resource at an observation point. It should be noted that, under a special condition, if all the output ports of all the programmable logic resources are taken as observation points, when a configuration code stream corresponding to the user circuit is generated, the signal to be observed is randomly laid out at any position and can meet the condition of laying out at the observation points, which is equivalent to that a constraint condition of laying out and routing is not required to be set at this time.

In the operation process of the user circuit, the output multiplexer acquires the switching signal and switches on a path between the observation point corresponding to the corresponding signal to be observed and the observation pin according to the switching signal, so that the observation pin switches to output different observation results of the signal to be observed, and the time-sharing output observation of the N signals to be observed at the input end of the output multiplexer is realized.

In this application, output multiplexer can acquire switching signal in real time and switch different signal of waiting to observe in real time, and in order to satisfy this real-time requirement, this application provides two kinds of different implementation, and these two kinds of different implementation respectively need corresponding hardware support:

implementation mode 1: in this embodiment, the observation hardware circuit further includes a switching pin 5, please refer to fig. 1, the switching pin 5 is connected to the control signal end of the output multiplexer 3 and provides the switching signal SEL input from the outside of the FPGA chip in real time, in actual application, the switching pin 5 actually needs to occupy a plurality of chip pins according to the difference of bits of the switching signal SEL output from the multiplexer 3, for example, when the output multiplexer 3 needs a 2-bit switching signal SEL, the switching pin 5 includes 2 chip pins, and when the output multiplexer 3 needs a 4-bit switching signal SEL, the switching pin 5 includes 4 chip pins. In this embodiment, the switching pin 5 is a dedicated pin that is separately provided as in the observation pin, and since the switching of the output multiplexer 3 is directly controlled by the pin, the real-time performance is high, and the switching of the output multiplexer can be controlled in real time to change and conduct different paths.

In this implementation, when outputting different signals to be observed according to different switching signals, the output multiplexer 3 switches and outputs each signal to be observed for multiple times according to the same switching order, or switches and outputs each signal to be observed for multiple times according to at least two different switching orders. For example, when the signals 1, 2, 3, and 4 are to be observed, the output may be switched in the order of signal to be observed 1 → signal to be observed 2 → signal to be observed 3 → signal to be observed 4 → signal to be observed 1, or may be switched in the order of signal to be observed 1 → signal to be observed 2 → signal to be observed 4 → signal to be observed 3 → signal to be observed 2 → signal to be observed 3 … without a fixed order. That is, although this implementation method needs to occupy an additional switching pin, the sequence of switching output of the signal to be observed may be variable, and the flexibility is high.

Implementation mode 2: the switching signal acquired by the output multiplexer 3 is from inside the FPGA chip, in this embodiment, the output multiplexer 3 adopts a one-hot encoding method, each signal bit corresponds to one input terminal, and usually, when the signal bit is 1, it indicates that the corresponding input terminal is gated. The observation hardware circuit also comprises a shift register 6 in which a number of different switching signals with a predetermined cyclic sequence are pre-stored, as shown in fig. 2. The output end of the shift register is connected with the control signal end of the output multiplexer, and sequentially switches and outputs different switching signals to the output multiplexer according to the shift clock according to a preset cyclic sequence. For example, the shift register is preset with an initial value of 1000, and the switching signals provided by the shift register to the output multiplexer are sequentially switched according to the cyclic sequence of 1000 → 0100 → 0010 → 0001 → 1000 according to the shift clock, so that the switching signal of 1000 indicates that the path from the first input terminal to the output terminal of the output multiplexer is turned on, and the switching signal of 0100 indicates that the path from the second input terminal to the output terminal of the output multiplexer is turned on, and so on. In this embodiment, the shift clock may be custom configured, such as may be the master clock of the user circuit. Because the shift register is used for providing the switching signal, the switching signal can be changed circularly and rapidly, and the requirement of real-time property is met.

The shift register can be set with an initial value by using the existing pin on the FPGA chip, and the debug pin is a Dynamic Reconfiguration Port (DRP) of the FPGA chip or a boundary scan Port of a boundary scan chain.

In this implementation, unlike the first implementation, since the switching signals are switched and output in a predetermined cyclic order, the respective signals to be observed can also be switched and output only a plurality of times in the same order, for example, the signals to be observed 1 → the signals to be observed 2 → the signals to be observed 3 → the signals to be observed 4 → the signals to be observed 1 can always be switched and output.

Regardless of the implementation mode 1 or the implementation mode 2, the output observation durations of the signals to be observed are all equal, or there is an inequality between the output observation durations of at least two signals to be observed. When one signal to be observed outputs observation time length for multiple times, the multiple output observation time lengths of the signal to be observed are equal, or at least two times of output observation time lengths are unequal.

Regardless of the implementation mode 1 or the implementation mode 2, since the observation pin outputs a plurality of different observation results of the signal to be observed, and the switching signal corresponds to the signal to be observed one by one, after the output, the output signal of the observation pin needs to be decomposed according to time intervals by using the switching signal as a time sequence basis, and the observation results of the signals to be observed are respectively restored, that is, the output signal of the observation pin is decomposed according to time intervals according to the switching time of the switching signal, each output signal is the observation result of the signal to be observed corresponding to the switching signal of the time interval, and the switching real-time property also ensures the accuracy of the observation result obtained by decomposition. In the above-described embodiment 1, since the switching signal is from outside the FPGA chip, the switching signal can be directly decomposed according to the input switching signal. In the above implementation 2, the switching signal is from inside the FPGA chip, and therefore the switching signal needs to be output to outside the FPGA chip; alternatively, under the condition that the predetermined cycle sequence of the switching signal is known, the switching time of the switching signal and the switching signal used in each period can be determined by outputting the shift clock to the outside of the FPGA chip.

Optionally, in implementation mode 2, the shift clock used by the shift register is N times the system clock of the signal to be observed, so that the frequency of each observation result obtained by decomposition is the same as the frequency of the signal to be observed, and the signal to be observed is displayed at the original frequency.

On the basis of realizing the function of sharing the pin time-sharing observation, the method and the device can connect the signals at all the observation points to the input end of the output multiplexer to be used as the signals to be observed which can be output in a time-sharing switching mode, or only connect the signals at part of the observation points to the input end of the output multiplexer to be used as the signals to be observed which can be output in a time-sharing switching mode. That is, in this embodiment, the observation hardware circuit includes the number M > N of observation points, and as shown in fig. 3, the observation hardware circuit further includes an intermediate gating circuit 7, a multi-bit register 8, and a debug pin 9. The M observation points are connected to N input terminals of the output multiplexer 3 through different conduction paths of the intermediate gating circuit, and the multi-bit register 8 controls the conduction path of the intermediate gating circuit 7 according to a debugging instruction SEL0 acquired from the debugging pin 9 to transmit signals at the N observation points of the M observation points to the input terminals of the output multiplexer 3 as N signals to be observed, as shown in fig. 3, where M is 9, and N is 3 as examples. Then, the intermediate gating circuit 7 can select different N signals to be observed which are time-division switched and output, and then the output multiplexer is used for time-division switching and outputting the N signals to be observed, so that the flexibility is higher.

In this embodiment, the debug pin 9 may be a dedicated pin provided separately as the observation pin and the switch pin, or may multiplex an existing pin on the FPGA chip. When the debug pin 9 multiplexes the existing pin on the FPGA chip, the debug pin 9 is a dynamically reconfigurable port of the FPGA chip or a boundary scan port of a boundary scan chain.

In this embodiment, the intermediate gating circuit 7 includes a plurality of multiplexers, and a multi-bit register is connected to control signal terminals of the respective multiplexers. Each first-stage multiplexer is correspondingly connected to a plurality of observation points, for example, as shown in fig. 3, the intermediate gating circuit 7 includes three first-stage multiplexers MUX1, MUX2 and MUX3, and each first-stage multiplexer is correspondingly connected to three observation points. Each first-stage multiplexer is directly connected with the input end of the output multiplexer, and each first-stage multiplexer selects one of signals of each observation point connected with the input end as a signal to be observed. Alternatively, each first-stage multiplexer is connected to the input of an output multiplexer through several other multiplexers forming a cascade structure. According to the different distribution conditions of the observation points, the arrangement conditions of the first-level multiplexers directly connected with the observation points in the intermediate gating circuit are also different, in one embodiment, the observation points are distributed in the FPGA chip according to regions, namely the observation points are distributed in a plurality of different regions, the observation points in each preset region range can be configured to be correspondingly connected with the same first-level multiplexer, and each first-level multiplexer and each observation point correspondingly connected with the first-level multiplexer are located in the preset region range. In another embodiment, the observation points are arranged in a row-column structure inside the FPGA chip, and as shown in fig. 3, the first-level multiplexers are arranged to form a row-column structure, and each observation point correspondingly connected to each first-level multiplexer is located in the same row-column structure or in a plurality of continuous row-column structures.

In another embodiment, the intermediate gating circuit 7 includes a plurality of MOS transistors, the source of each MOS transistor is correspondingly connected to an observation point, each input terminal of the output multiplexer 3 is connected to the drain of each MOS transistor, and the multi-bit register 8 is connected to the gate of each MOS transistor and controls the switching of the MOS transistor. For example, the drains of every three MOS transistors are connected to one input terminal of the output multiplexer 3 as shown in fig. 4.