1. A mapping table management method based on HMB, the method comprising:

the mapping table management module queries corresponding mapping table items in a mapping table Cache module according to a read-write request issued by a host;

checking a corresponding mapping table entry in the mapping table Cache module, and judging whether the mapping table entry is in an SOC SRAM mapping table buffer area;

if the mapping table entry is not in the SOC SRAM mapping table buffer area, continuously judging whether the HMB is enabled;

if the HMB is enabled, continuously judging whether the mapping table entry is in a buffer area of the HMB mapping table;

if the mapping table entry is not in the HMB mapping table buffer area, loading the mapping table from the NAND storage area to the HMB mapping table buffer area;

and loading the corresponding mapping table entry into an SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module.

2. The HMB-based mapping table management method of claim 1, further comprising, after said step of determining whether said mapping table entry is in a SOC SRAM mapping table buffer:

and if the mapping table entry is in the SOC SRAM mapping table buffer area, directly returning the mapping table entry to the mapping table management module.

3. The HMB-based mapping table management method according to claim 2, further comprising, after said step of continuing to determine whether HMB is enabled:

and if the HMB is not enabled, loading the mapping table from the NAND storage area to the SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module.

4. The HMB-based mapping table management method of claim 3, wherein after said step of continuing to determine whether said mapping table entry is in an HMB mapping table buffer, further comprising:

and if the mapping table entry is in the HMB mapping table buffer area, loading the corresponding mapping table entry into the SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module.

5. An HMB-based mapping table management apparatus, the apparatus comprising:

the query module is used for querying a corresponding mapping table item from the mapping table Cache module according to a read-write request issued by the host;

the first judgment module is used for checking a corresponding mapping table item in the mapping table Cache module and judging whether the mapping table item is in an SOC SRAM mapping table buffer area;

the second judgment module is used for continuously judging whether the HMB is enabled or not if the mapping table item is not in the SOC SRAM mapping table buffer area;

a third determining module, configured to, if the HMB is enabled, continue to determine whether the mapping table entry is in a HMB mapping table buffer area;

the first loading module is used for loading the mapping table from the NAND storage area to the HMB mapping table buffer area if the mapping table entry is not in the HMB mapping table buffer area;

and the second loading module is used for loading the corresponding mapping table entry into the SOC SRAM mapping table buffer area and returning the corresponding mapping table entry to the mapping table management module.

6. The HMB-based mapping table management apparatus according to claim 5, wherein the apparatus further comprises a first returning module, the first returning module being configured to:

and if the mapping table entry is in the SOC SRAM mapping table buffer area, directly returning the mapping table entry to the mapping table management module.

7. The HMB-based mapping table management apparatus according to claim 6, wherein the apparatus further comprises a second return module for:

and if the HMB is not enabled, loading the mapping table from the NAND storage area to the SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module.

8. The HMB-based mapping table management apparatus of claim 7, wherein the apparatus further comprises a third return module, the third return module configured to:

and if the mapping table entry is in the HMB mapping table buffer area, loading the corresponding mapping table entry into the SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module.

9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 4 are implemented when the computer program is executed by the processor.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.

Background

SSD (solid state disk) has been widely used in various occasions, and has been gradually replacing the conventional HDD in the PC market at present, providing better experience for users in terms of reliability and performance. On an SSD, there is generally a relatively large DRAM storing data such as mapping tables (logical addresses accessed by the host to NAND physical addresses storing data), and for a 512GB SSD, 512MB of DRAM is usually configured. With the evolution of interface technology, the PCIe Gen 4 era can provide higher bandwidth; meanwhile, due to the power consumption/cost requirements of the whole machine, higher requirements are put forward for the SSD. Combining these factors, on the mainstream PCIe Gen 44 channel SSD, it is generally required to adopt a scheme without DRAM, and only about 10MB of SRAM is reserved inside the SSD SOC.

In this scenario, the mapping table needs to be dynamically replaced on the SRAM/NAND to satisfy the read/write request of the host. Furthermore, a part of the memory of the host can be allocated to the SSD to serve as a mapping table cache through an HMB technology, more table entries can be loaded into the memory, and high-speed read-write performance in a wider range is provided.

At present, in the existing SSD, the buffer management model for the SOC SRAM and the HMB mapping table is a peer-to-peer model, and is mainly used to expand the number of mapping tables in the memory. However, for the requirement of the PCIe Gen 4 in the high-speed performance scene, the read-write IOPS reaches 1M, and only 1us of processing time can be provided for one IO. When the mapping table is located in the HMB, the mapping table access corresponding to random read-write needs to query the mapping table from the PCIe bus to the host memory in real time, and each request incurs an overhead of approximately 1us, thereby greatly affecting the random read-write performance. In addition, because the HMB mapping table buffer and the SOC SRAM mapping table buffer are peer-to-peer models, once the mapping table is loaded from the NAND, the mapping table will not move, and thus the overhead described above is always present.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a mapping table management method and apparatus based on HMB, a computer device, and a storage medium.

A mapping table management method based on HMB, the method comprising:

the mapping table management module queries corresponding mapping table items in a mapping table Cache module according to a read-write request issued by a host;

checking a corresponding mapping table entry in the mapping table Cache module, and judging whether the mapping table entry is in an SOC SRAM mapping table buffer area;

if the mapping table entry is not in the SOC SRAM mapping table buffer area, continuously judging whether the HMB is enabled;

if the HMB is enabled, continuously judging whether the mapping table entry is in a buffer area of the HMB mapping table;

if the mapping table entry is not in the HMB mapping table buffer area, loading the mapping table from the NAND storage area to the HMB mapping table buffer area;

and loading the corresponding mapping table entry into an SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module.

In one embodiment, after the step of determining whether the mapping table entry is in the SOC SRAM mapping table buffer, the method further includes:

and if the mapping table entry is in the SOC SRAM mapping table buffer area, directly returning the mapping table entry to the mapping table management module.

In one embodiment, after the step of continuously determining whether HMB is enabled, the method further includes:

and if the HMB is not enabled, loading the mapping table from the NAND storage area to the SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module.

In one embodiment, after the step of continuously determining whether the map entry is in the HMB map table buffer, the method further includes:

and if the mapping table entry is in the HMB mapping table buffer area, loading the corresponding mapping table entry into the SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module.

An HMB-based mapping table management apparatus, the apparatus comprising:

the query module is used for querying a corresponding mapping table item from the mapping table Cache module according to a read-write request issued by the host;

the first judgment module is used for checking a corresponding mapping table item in the mapping table Cache module and judging whether the mapping table item is in an SOC SRAM mapping table buffer area;

the second judgment module is used for continuously judging whether the HMB is enabled or not if the mapping table item is not in the SOC SRAM mapping table buffer area;

a third determining module, configured to, if the HMB is enabled, continue to determine whether the mapping table entry is in a HMB mapping table buffer area;

the first loading module is used for loading the mapping table from the NAND storage area to the HMB mapping table buffer area if the mapping table entry is not in the HMB mapping table buffer area;

and the second loading module is used for loading the corresponding mapping table entry into the SOC SRAM mapping table buffer area and returning the corresponding mapping table entry to the mapping table management module.

In one embodiment, the apparatus further comprises a first return module configured to:

and if the mapping table entry is in the SOC SRAM mapping table buffer area, directly returning the mapping table entry to the mapping table management module.

In one embodiment, the apparatus further comprises a second return module configured to:

and if the HMB is not enabled, loading the mapping table from the NAND storage area to the SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module.

In one embodiment, the apparatus further comprises a third return module configured to:

and if the mapping table entry is in the HMB mapping table buffer area, loading the corresponding mapping table entry into the SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module.

A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.

A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the methods described above.

The mapping table management method, the mapping table management device, the computer equipment and the storage medium based on the HMB query the corresponding mapping table items in the mapping table Cache module through the mapping table management module according to the read-write request issued by the host; checking a corresponding mapping table entry in the mapping table Cache module, and judging whether the mapping table entry is in an SOC SRAM mapping table buffer area; if the mapping table entry is not in the SOC SRAM mapping table buffer area, continuously judging whether the HMB is enabled; if the HMB is enabled, continuously judging whether the mapping table entry is in a buffer area of the HMB mapping table; if the mapping table entry is not in the HMB mapping table buffer area, loading the mapping table from the NAND storage area to the HMB mapping table buffer area; and loading the corresponding mapping table entry into an SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module. According to the invention, different mapping table Cache models are defined under different working modes according to the performance of different mapping table storage areas, so that the delay of mapping table query can be effectively reduced. For data frequently accessed by the host, the mapping table of the data is loaded into the fastest SOC SRAM, so that the optimal read-write performance of the host is ensured.

Drawings

FIG. 1 is a flow diagram of a typical SSD internal access flow;

FIG. 2 is a flow chart illustrating a read process when a mapping table is stored in an HMB according to the prior art;

FIG. 3 is a flowchart illustrating an HMB-based mapping table management method according to an embodiment;

FIG. 4 is a diagram of a mapping table Cache model in an embodiment;

FIG. 5 is a flow chart illustrating a mapping table management method based on HMB in another embodiment;

FIG. 6 is a block diagram of an HMB based mapping table management apparatus in one embodiment;

FIG. 7 is a block diagram of an HMB-based mapping table management apparatus according to another embodiment;

FIG. 8 is a block diagram showing a structure of an HMB-based mapping table management apparatus according to still another embodiment;

FIG. 9 is a block diagram of an HMB-based mapping table management apparatus in another embodiment;

FIG. 10 is a diagram showing an internal structure of a computer device according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

As shown in fig. 1, a typical SSD internal access flow is shown. The specific implementation process comprises the following steps: the host submits a read command to a front end module of the SSD. The SSD front-end module fragments the command into mapped units (LPAs, typically 4 KB). And submitting the operation request to a buffer management module and allocating a read-write buffer. If the command is a write command, data transmission with the host is established according to the allocated buffer area, and the host is informed that the command is completed after the data transmission is completed. If the command is a read command, the operation request is submitted to the mapping table management module. The mapping table management module is responsible for allocating a corresponding physical address (write command) according to the logical address or converting the logical address into a NAND physical address (read command), and the mapping table management module initiates a query/modification request to the mapping table Cache module according to the logical address. And the mapping table Cache module is used for storing a part of logical to physical mapping tables according to the size of the usable memory, wherein the index of each mapping table entry is a logical address, and the value of each mapping table entry is an NAND physical address for storing corresponding data. The method comprises the steps that two types of mapping table buffer areas exist, wherein one type of the mapping table buffer area is an SOC SRAM mapping table buffer area which exists in an SSD controller and is provided with an SRAM with a certain size when leaving a factory, the number of the SRAM is typically MB, and the other type of the mapping table buffer area is an HMB mapping table buffer area. Because the HMB mapping table buffer area entity is at the host end, if the request initiated by the mapping table management module falls into the host end, the HMB mapping table buffer area entity needs to communicate with the host end; and the SOC SRAM is positioned in the SSD controller, so that the access is extremely fast. The mapping table Cache module processes an access request corresponding to the mapping table management module according to a mapping table cached in the mapping table Cache module; in particular, when the request for access is not in the mapping table buffer, it needs to be loaded from the corresponding mapping table storage area on the NAND. And the mapping table management module submits the operation request to the back-end module, and the back-end module initiates a read/write request for the NAND according to the physical address. Waiting for the NAND read/write operation request to complete. If a read command, the data is loaded into the NAND Cache Register at this time. After the data Ready, the transfer of data from the NAND Cache Register to the host is initiated.

Because the access of the host has certain space aggregation, the corresponding mapping table generally resides in a limited mapping table buffer area, thereby realizing higher read-write performance.

At present, because a certain difference exists between the access delay of the HMB mapping table buffer area and the SOC SRAM mapping table buffer area, the performance is greatly affected in a high-speed IOPS application scenario. As shown in fig. 2, taking a typical read request as an example: s0, the host issues a read command. S1 the SSD front-end module splits the command into mapping units (LPAs, typically 4 KB). And S2, submitting to the read-write buffer module and allocating the read-write buffer. And S3, submitting the request to the mapping table management module. S4, the mapping table managing module inquires whether the corresponding mapping table (assumed to be LPA a) is loaded. S5, the mapping table is loaded and located in the HMB mapping table buffer. And S6, acquiring corresponding mapping table data through a PCIe bus, and inquiring the user data NAND physical storage address corresponding to the LPA A. And S7, submitting the back-end module, loading data from the user data storage area according to the inquired NAND physical address, and returning the data to the host.

In the whole process, S6 needs to query the table entry from the host-side HMB mapping table buffer in real time, which basically causes about 1us of delay. In the PCIe Gen 4 era, random read IOPS of the SSD is up to 1M, and the processing time corresponding to each IO is only 1us, so that the extra 1us mapping table query overhead in this case will have a great influence on the performance. In addition, because the HMB mapping table buffer and the SOC SRAM mapping table buffer are peer-to-peer models, once the mapping table is loaded from the NAND, the mapping table will not move, and thus the overhead described above is always present.

Based on the above, the invention provides a mapping table management method based on HMB, in the method, different mapping table Cache models are defined under different working modes according to the performance of different mapping table storage areas, so that the delay of mapping table query can be effectively reduced:

1. of the three map storage areas, the NAND area is the slowest to access (on the order of 100 us), the HMB area the second (on the order of 1 us), and the SOC SRAM the fastest (on the order of ns).

2. And when the HMB is not enabled, the SOC SRAM is used as the Cache of the NAND mapping table storage area, for the host access request, if the Cache is hit, the direct reading and writing are carried out, otherwise, the load is carried out from the NAND to the Cache.

3. When HMB is enabled, SOC SRAM is used as the Cache for HMB (denoted as L1 Cache), and HMB is used as the Cache for NAND map storage (denoted as L2 Cache). For a host access request, if the L1 Cache is hit, directly reading and writing; otherwise, checking the L2Cache, and loading the L1 Cache for reading and writing when the L2Cache is hit; if not in the L2Cache, then load from the NAND mapping table storage to the L1/L2 Cache.

Based on the invention, for the data frequently accessed by the host, the mapping table can be loaded into the fastest SOC SRAM, thereby ensuring the optimal read-write performance of the host.

In one embodiment, as shown in fig. 3, there is provided a mapping table management method based on HMB, the method including:

step 302, the mapping table management module queries corresponding mapping table items in a mapping table Cache module according to a read-write request issued by a host;

step 304, checking a corresponding mapping table entry in a mapping table Cache module, and judging whether the mapping table entry is in an SOC SRAM mapping table buffer area;

step 306, if the mapping table entry is not in the SOC SRAM mapping table buffer area, continuing to judge whether the HMB is enabled;

step 308, if the HMB is enabled, continuing to judge whether the mapping table entry is in the HMB mapping table buffer area;

step 310, if the mapping table entry is not in the HMB mapping table buffer area, loading the mapping table from the NAND storage area to the HMB mapping table buffer area;

step 312, load the corresponding mapping table entry into the buffer area of the SOC SRAM mapping table, and return the corresponding mapping table entry to the mapping table management module.

Specifically, as described in fig. 4, the mapping table dynamic Cache model provided in this embodiment is described. The traditional SSD mapping table Cache model comprises:

there are two separate mapping table buffers to speed up the NAND mapping table buffer.

When HMB is not enabled, only SOC SRAM provides Cache services, which are smaller than cacheable map entries.

When the entry corresponding to the logical address accessed by the host falls in the Cache: if the mapping table buffer area of the SOC SRAM is in the buffer area, the access performance is high, and the corresponding mapping table access interface is expressed as high speed; if the buffer area of the mapping table of the HMB has low access performance, the corresponding interface for accessing the mapping table is shown as low speed.

When the entry corresponding to the logical address accessed by the host is not in the Cache: the corresponding mapping table is loaded from the NAND mapping table storage area and placed in the currently available mapping table buffer (SOC SRAM/HMB).

The SSD mapping table Cache model provided in this embodiment includes:

when the HMB is not enabled, the system works in a primary Cache model, and the SOC SRAM is used as an L1 Cache of the storage area of the NAND mapping table, and the behavior in the scene is similar to that in the traditional SSD Cache model.

When HMB is enabled, then work in the secondary Cache model. The HMB mapping table buffer area is used as an L2Cache of the NAND mapping table storage area; SOC SRAM mapping table buffer, L1 Cache as HMB mapping table buffer. For the access request of the mapping table management module, preferentially retrieving from an L1 Cache, and directly processing if the access request is hit; if not, searching is carried out in the L2Cache, and the like until the storage area of the NAND mapping table is reached. When the L1 Cache miss occurs, the corresponding content is loaded into the L1 Cache in addition to being queried from the L2Cache, so that subsequent high-speed access is guaranteed.

Obviously, when the HMB is not enabled, a first-level Cache model is established, and the SRAM in the SOC serves as the Cache of mapping table data stored on the NAND, so that the response to the host read-write command is accelerated. And when the HMB is enabled, establishing a secondary Cache model, wherein a mapping table memory area distributed by the HMB is used as an L2Cache of mapping table data stored on the NAND, and the SRAM in the SOC is used as an L1 Cache of the HMB mapping table memory area. Different Cache models are established according to the access speeds and the working scenes of different storage areas, so that the SSD access performance without the DRAM can be effectively accelerated.

In this embodiment, a mapping table management module queries a corresponding mapping table item from a mapping table Cache module according to a read-write request issued by a host; checking a corresponding mapping table entry in the mapping table Cache module, and judging whether the mapping table entry is in an SOC SRAM mapping table buffer area; if the mapping table entry is not in the SOC SRAM mapping table buffer area, continuously judging whether the HMB is enabled; if the HMB is enabled, continuously judging whether the mapping table entry is in a buffer area of the HMB mapping table; if the mapping table entry is not in the HMB mapping table buffer area, loading the mapping table from the NAND storage area to the HMB mapping table buffer area; and loading the corresponding mapping table entry into an SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module. According to the scheme, different mapping table Cache models are defined under different working modes according to the performance of different mapping table storage areas, so that the delay of mapping table query can be effectively reduced. For data frequently accessed by the host, the mapping table of the data is loaded into the fastest SOC SRAM, so that the optimal read-write performance of the host is ensured.

In one embodiment, after the step of determining whether the mapping table entry is in the SOC SRAM mapping table buffer area, the method further includes: and if the mapping table entry is in the SOC SRAM mapping table buffer area, directly returning the mapping table entry to the mapping table management module.

In one embodiment, after the step of determining whether HMB is enabled, the method further comprises: and if the HMB is not enabled, loading the mapping table from the NAND storage area to the SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module.

In one embodiment, after the step of continuously determining whether the mapping table entry is in the HMB mapping table buffer, the method further comprises: and if the mapping table entry is in the HMB mapping table buffer area, loading the corresponding mapping table entry into the SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module.

In an embodiment, as shown in fig. 5, a method for completely implementing mapping table management based on HMB is provided, and the specific implementation steps include:

and 5.1, the mapping table management module queries corresponding mapping table items from the mapping table Cache module according to the host read-write request.

And 5.2, checking the corresponding table entry by the mapping table Cache module.

Step 5.3, judging whether the buffer area is in the SOC SRAM mapping table buffer area; if so, directly returning the corresponding table entry to the mapping table management module; if not, continue with step 5.4.

Step 5.4, whether HMB is enabled; if not, loading the mapping table from the NAND storage area to the SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module; if so, continue with step 5.5.

Step 5.5, whether the buffer area is in the HMB mapping table buffer area or not; if yes, loading the corresponding table entry into an SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module; if not, continue with step 5.6.

And 5.6, loading the mapping table from the NAND storage area to the HMB mapping table buffer area.

And 5.7, loading the corresponding table entry into the SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module.

And 5.8, returning the corresponding table entry to the mapping table management module.

In this embodiment, it can be ensured that the mapping table corresponding to the data frequently accessed by the host falls in the high-speed SOC SRAM Cache, so that higher performance can be provided.

It should be understood that although the various steps in the flow charts of fig. 1-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.

In one embodiment, as shown in fig. 6, there is provided an HMB-based mapping table management apparatus 600, including:

the query module 601 is used for querying a corresponding mapping table item from the mapping table Cache module according to a read-write request issued by the host;

a first determining module 602, configured to check a corresponding mapping table entry in the mapping table Cache module, and determine whether the mapping table entry is in a buffer area of an SOC SRAM mapping table;

a second determining module 603, configured to continue to determine whether the HMB is enabled if the mapping table entry is not in the SOC SRAM mapping table buffer area;

a third determining module 604, configured to, if the HMB is enabled, continue to determine whether the mapping table entry is in a HMB mapping table buffer area;

a first loading module 605, configured to load a mapping table from a NAND storage area to an HMB mapping table buffer area if the mapping table entry is not in the HMB mapping table buffer area;

a second loading module 606, configured to load the corresponding mapping table entry into the buffer area of the SOC SRAM mapping table, and return the corresponding mapping table entry to the mapping table management module.

In one embodiment, as shown in fig. 7, there is provided an HMB-based mapping table management apparatus 600, further comprising a first returning module 607 for:

and if the mapping table entry is in the SOC SRAM mapping table buffer area, directly returning the mapping table entry to the mapping table management module.

In one embodiment, as shown in fig. 8, there is provided an HMB-based mapping table management apparatus 600, further comprising a second return module 608 for:

and if the HMB is not enabled, loading the mapping table from the NAND storage area to the SOC SRAM mapping table buffer area, and returning the corresponding mapping table entry to the mapping table management module.

In one embodiment, as shown in fig. 9, there is provided an HMB-based mapping table management apparatus 600, further comprising a third returning module 609, configured to:

and if the mapping table entry is in the HMB mapping table buffer area, loading the corresponding mapping table entry into the SOC SRAM mapping table buffer area, and returning the corresponding table entry to the mapping table management module.

For specific limitations of the HMB-based mapping table management apparatus, reference may be made to the above limitations of the HMB-based mapping table management method, which is not described herein again.

In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 10. The computer apparatus includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation device in the nonvolatile storage medium and the execution of the computer program. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a mapping table management method based on HMB.

Those skilled in the art will appreciate that the architecture shown in fig. 10 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above respective method embodiments.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.