1. A flash memory controller, comprising:

an interface circuit coupled between the host and the internal bus;

a read-only memory coupled to the internal bus for storing program codes;

a control logic circuit coupled between the internal bus and a flash memory module, the flash memory module being externally coupled to the flash memory controller;

a processor coupled to the internal bus for executing the program code to access the flash memory module using the control logic; and

a cache coupled to the internal bus;

the flash memory module comprises a plurality of chips, each chip comprises a plurality of storage pages, and each storage page comprises a plurality of storage sections; when the processor receives a specific write command and specific data with data amount of N storage sections from the host through the interface circuit and the internal bus, the processor is used for storing the specific data to the cached area, and the processor builds or updates the binary tree by adding a specific node to the binary tree, wherein the specific node has node information, and the node information comprises a node index, a logical address carried by the specific write command, a cache index corresponding to the cached area, a left node, a right node and a storage section length corresponding to the data amount of the N storage sections; and, when the processor receives a read command from the host requesting to read a certain data cached in the cache, the processor is arranged to use node information of one or more nodes recorded in the binary tree to obtain the certain data from the cache and to send the certain data to the host without controlling the control logic to access the flash memory module.

2. The flash memory controller of claim 1, wherein the processor comprises a first core and a second core, the first core for controlling operations between the flash memory controller and the host, the second core for controlling operations between the flash memory controller and the flash memory module; and the second core building or updating the binary tree by adding the particular node to the binary tree, wherein the particular node has the node index, the logical address carried by the particular write command, the cache index corresponding to the region of the cache, the left node, the right node, and the storage block length corresponding to the amount of data for the N storage blocks.

3. The flash memory controller of claim 1 wherein when moving a portion of first data from the cache to the flash memory module and writing to a minimum write unit within the flash memory module, if the amount of first data is greater than the minimum write unit, the second core is arranged to delete a first node corresponding to the first data and insert a second node in the binary tree indicating that another portion of the first data has not been moved from the cache to the flash memory module.

4. A memory device includes:

a flash memory module; and

the flash memory controller of claim 1.

5. A method of a flash memory controller, comprising:

providing an interface circuit coupled between a host and an internal bus;

providing a control logic circuit coupled between the internal bus and a flash memory module, the flash memory module being externally coupled to the flash memory controller, the flash memory module having a plurality of chips, each chip having a plurality of storage pages, each storage page having a plurality of storage segments;

providing a cache coupled to the internal bus;

when a specific write command and specific data with the data size of N storage sections are received from the host through the interface circuit and the internal bus, storing the specific data into the cached area and building or updating the binary tree by adding a specific node into the binary tree, wherein the specific node has node information, and the node information comprises a node index, a logical address carried by the specific write command, a cache index corresponding to the cached area, a left node, a right node and a storage section length corresponding to the data size of the N storage sections; and

when a read command is received from the host requesting to read a certain data cached in the cache, node information of one or more nodes recorded in the binary tree is used to obtain the certain data from the cache and send the certain data to the host without controlling the control logic circuit to access the flash memory module.

6. The method of claim 5, wherein the control logic is controlled by a processor, the processor comprising a first core and a second core, and the method comprising:

using the first core to control operations between the flash controller and the host;

using the second core to control operations between the flash controller and the flash memory module; and

using the second core to create or update the binary tree by adding the specific node to the binary tree, wherein the specific node has the node information including the node index, the logical address carried by the specific write command, the cache index corresponding to the region of the cache, the left node, the right node, and the storage block length corresponding to the amount of data of the N storage blocks.

7. The method of claim 5, further comprising:

when a portion of first data is moved from the cache to the flash memory module and written to a minimum write location within the flash memory module, if the amount of the first data is greater than the minimum write location, deleting a first node corresponding to the first data and inserting a second node in the binary tree, wherein the second node indicates that another portion of the first data has not been moved from the cache to the flash memory module.

8. A flash memory controller, comprising:

an interface circuit coupled between the host and the internal bus;

a read-only memory coupled to the internal bus for storing program codes;

a control logic circuit coupled between the internal bus and a flash memory module, the flash memory module being externally coupled to the flash memory controller;

a processor coupled to the internal bus for executing the program code to access the flash memory module using the control logic; and

a cache coupled to the internal bus;

the flash memory module comprises a plurality of chips, each chip comprises a plurality of storage pages, and each storage page comprises a plurality of storage sections; when the processor receives a specific write command and specific data having a data size of N storage segments from the host through the interface circuit and the internal bus, the processor compares the data size of the N storage segments with a data size of a minimum write unit within the flash memory module to determine whether to generate flash-based cache information to create or update a binary tree.

9. A memory device includes:

a flash memory module; and

the flash memory controller of claim 8.

10. A method of a flash memory controller, comprising:

providing an interface circuit coupled between a host and an internal bus;

providing a control logic circuit coupled between the internal bus and a flash memory module, the flash memory module being externally coupled to the flash memory controller, the flash memory module having a plurality of chips, each chip having a plurality of memory pages, each memory page having a plurality of memory segments;

providing a cache coupled to the internal bus; and

when a specific write command and specific data having a data size of N storage sectors are received from the host through the interface circuit and the internal bus, the data size of the N storage sectors is compared with a data size of a minimum write unit within the flash memory module to determine whether to generate flash-based cache information to create or update a binary tree.

Background

Conventionally, when a host wants to write data to a flash memory module through a flash memory controller, the host sends the data to the flash memory controller, the data is temporarily stored in a cache or a buffer inside the flash memory controller, and the data is written to the flash memory module when the amount of data temporarily stored in the cache reaches a predetermined value, for example, the flash memory controller continuously receives data from the host and stores the received data to the cache, and the flash memory controller moves data from the cache to the flash memory module when the amount of data of the received data is sufficient to be written to a plurality of word lines of the flash memory module.

Since the cache in the flash memory controller can temporarily store the data that has not been written into the flash memory module, when the host suddenly wants to read the data, the flash memory controller can directly send the data stored in the cache to the host to shorten the access time. Specifically, each piece of data stored in the cache of the flash memory controller includes a corresponding logical address, and when the host sends a read command including a specific logical address, the flash memory controller searches the logical addresses of the pieces of data temporarily stored in the cache to determine whether at least one of the logical addresses matches the specific logical address, and if the cache has data corresponding to the specific logical address, the flash memory controller can directly send the piece of data to the host.

However, if the data corresponding to the specific logical address is updated in a short time, i.e. the host transmits two or more data corresponding to the same specific logical address in a short time, two or more data in the cache of the flash memory controller correspond to the specific logical address, wherein the latest data having the specific logical address is valid data and the older data having the specific logical address is invalid data. Therefore, in order to ensure that the flash memory controller can send valid data to the host, when the host sends the read command containing the specific logical address, the flash memory controller must search all logical addresses of all data temporarily stored in the cache, which results in inefficiency of the flash memory controller. In addition, since one logical address may correspond to two or more data in the cache, the conventional binary search method is not suitable for a flash memory controller.

Disclosure of Invention

It is therefore one of the objectives of the present invention to provide a flash memory controller, which is capable of generating a copy of host-based cache data or a copy of flash-based cache information and building and optimizing a binary tree with fewer nodes when the cache of the flash memory controller stores data from the host, so as to greatly improve the search speed of the binary tree, reduce the computation cost of multiple cores in the flash memory controller, and minimize the number of times of accessing the cache (which may be a dynamic random access memory, for example) to greatly reduce the total time delay, thereby solving the above-mentioned problems.

According to the embodiment of the application, a flash memory controller is disclosed. The flash memory controller includes an interface circuit, a read-only memory, a control logic circuit, a processor and a cache. The interface circuit is coupled between a host and an internal bus. The ROM is coupled to the internal bus and is used for storing a program code. The control logic circuit is coupled between the internal bus and a flash memory module, which is externally coupled to the flash memory controller. The processor is coupled to the internal bus and is used for executing the program codes to access the flash memory module by using the control logic circuit. A cache is coupled to the internal bus. The flash memory module comprises a plurality of chips, each chip comprises a plurality of storage pages, and each storage page comprises a plurality of storage sections. When the processor receives a specific write command and specific data with the data volume of N storage sections from the host through the interface circuit and the internal bus, the processor is used for storing the specific data into an area of the cache, and the processor establishes or updates the binary tree by adding a specific node into the binary tree, wherein the specific node has node information, and the node information comprises a node index, a logic address carried by the specific write command, a cache index corresponding to the area of the cache, a left node, a right node and a storage section length corresponding to the data volume of the N storage sections. When the processor receives a read command from the host requesting to read a certain data cached in the cache, the processor is arranged to use the node information of the one or more nodes recorded in the binary tree to obtain the certain data from the cache and to send the certain data to the host without controlling the control logic circuit to access the flash memory module.

According to an embodiment of the present application, a memory device is disclosed. The memory device comprises the flash memory module and the flash memory controller.

According to the embodiment of the application, a method of a flash memory controller is disclosed. The method comprises the following steps: providing an interface circuit coupled between a host and an internal bus; providing a control logic circuit coupled between the internal bus and a flash memory module, the flash memory module being externally coupled to the flash memory controller, the flash memory module having a plurality of chips, each chip having a plurality of storage pages, each storage page having a plurality of storage segments; providing a cache coupled to the internal bus; when a specific write command and specific data with the data volume of N storage sections are received from the host through the interface circuit and the internal bus, storing the specific data into an area of the cache and establishing or updating the binary tree by adding a specific node into the binary tree, wherein the specific node has node information, and the node information comprises a node index, a logic address carried by the specific write command, a cache index corresponding to the area of the cache, a left node, a right node and a storage section length corresponding to the data volume of the N storage sections; and when a read command is received from the host to request to read certain data cached in the cache, using the node information of the one or more nodes recorded in the binary tree to obtain the certain data from the cache and send the certain data to the host without controlling the control logic circuit to access the flash memory module.

According to the embodiment of the application, a flash memory controller is disclosed. The flash memory controller includes an interface circuit, a read-only memory, a control logic circuit, a processor and a cache. The interface circuit is coupled between a host and an internal bus. The ROM is coupled to the internal bus and is used for storing a program code. The control logic circuit is coupled between the internal bus and a flash memory module, which is externally coupled to the flash memory controller. The processor is coupled to the internal bus and is used for executing the program codes to access the flash memory module by using the control logic circuit. A cache is coupled to the internal bus. The flash memory module comprises a plurality of chips, each chip comprises a plurality of storage pages, and each storage page comprises a plurality of storage sections. When the processor receives a specific write command and specific data having a data size of N storage blocks from the host through the interface circuit and the internal bus, the processor compares the data size of the N storage blocks with a data size of a minimum write unit in the flash memory module to determine whether to generate a flash-based cache information to create or update a binary tree.

According to an embodiment of the present application, a memory device is disclosed. The memory device comprises a flash memory module and the flash memory controller.

According to the embodiment of the application, a method of a flash memory controller is disclosed. The method comprises the following steps: providing an interface circuit coupled between a host and an internal bus; providing a control logic circuit coupled between the internal bus and a flash memory module, the flash memory module being externally coupled to the flash memory controller, the flash memory module having a plurality of chips, each chip having a plurality of storage pages, each storage page having a plurality of storage segments; providing a cache coupled to the internal bus; and when a specific write command and a specific data having a data size of N storage blocks are received from the host through the interface circuit and the internal bus, comparing the data size of the N storage blocks with a data size of a minimum write unit within the flash memory module to determine whether to generate a flash-based cache information to create or update a binary tree.

Drawings

FIG. 1 is a block diagram of a memory device according to an embodiment of the present application.

FIG. 2 is a schematic diagram of an embodiment of the operation of the flash controller of FIG. 1 to create and insert node N0 to update a binary tree when the flash controller receives data D1 from the host.

FIG. 3 is a schematic diagram of an embodiment of the operation of the flash controller of FIG. 1 to insert node N1 to update a binary tree when the flash controller receives data D2 from the host.

FIG. 4 is a schematic diagram of an embodiment of the operation of the flash controller of FIG. 1 to insert node N2 to update a binary tree when the flash controller receives data D3 from the host.

FIG. 5 is a diagram illustrating an embodiment of the processor rearranging a binary tree to reduce the hierarchical number of the binary tree.

FIG. 6 is a schematic diagram illustrating an operation of the flash controller shown in FIG. 1 to delete node N0 from the binary tree to update the binary tree shown in FIG. 4 when data D1 and data D2 in 128 sectors formed in the previous half are moved from the cache (e.g., DRAM) and then written to a page of the flash memory module.

FIG. 7 is a schematic diagram illustrating an operation of the flash controller shown in FIG. 1 to delete node N1 from the binary tree to update the binary tree shown in FIG. 4 when data D1 and data D2 in 128 sectors formed in the previous half are moved from the cache (e.g., DRAM) and then written to a page of the flash memory module.

FIG. 8 is a schematic diagram illustrating an operation of the flash controller of FIG. 1 inserting a new node N3 into the binary tree to update the binary tree of FIG. 4 when data D1 and data D2 of 128 sectors formed in the previous half are moved from the cache (e.g., DRAM) and then written to a page of the flash memory module.

Fig. 9 is a flowchart of a method for creating or updating a binary tree when data is received from the host according to an embodiment of the present application.

FIG. 10 is a schematic diagram of another embodiment of the present application in which the flash controller determines data D1 as a remaining data portion R1 when the flash controller receives data D1 from the host.

FIG. 11 is a schematic diagram illustrating another embodiment of the present invention in which the flash controller determines data D1 and data D2 as data P1 and residual data R2 of a page size and inserts node N0 to update a binary tree when the flash controller receives data D2 from the host.

FIG. 12 is a schematic diagram illustrating another embodiment of the present invention in which the flash controller determines the data D1, D2 and D3 as the data P1, P2 and P3 of the storage page size and the remaining data portion R3 and inserts nodes N1 and N2 to update the binary tree when the flash controller receives the data D3 from the host.

FIG. 13 is a flow diagram of a method for building or updating a binary tree when data is received from the host according to another embodiment of the present application.

Wherein the reference numerals are as follows:

100 memory device

110 flash memory controller

111 interface circuit

112 processor

113 buffer memory

114 dynamic random access memory controller

115 read-only memory

116 control logic circuit

120 flash memory module

130 host

140 dynamic random access memory

210 data table

220 binary tree

Detailed Description

FIG. 1 is a block diagram of a memory device 100 according to an embodiment of the present application. As shown in FIG. 1, the memory device 100 includes a flash memory controller 110 and a flash memory module 120, wherein the flash memory controller 110 is used to access the flash memory module 120. In addition, the flash memory controller 110 includes an interface circuit 111, a processor 112, a buffer memory 113, a dynamic random access memory controller 114, a Read Only Memory (ROM)115 and a control logic circuit 116, the processor 112 may be a microprocessor or a central processing unit including two cores C0 and C1, the ROM 115 is used for storing a program code, the processor 112 executes the program code to control the access of the flash memory module 120, the core C0 is mainly configured to control operations between the flash memory controller 110 and the host 130, the core C1 of the processor 112 is mainly configured to control operations between the flash memory controller 110 and the flash memory module 120, and the dynamic random access memory controller 114 is arranged to access a dynamic random access memory 140 located outside the flash memory controller 110.

The flash memory module 120 may include one or more flash memory chips, each flash memory chip including a plurality of storage blocks, each storage block being a minimum erase unit, and each storage block including a plurality of storage pages, each storage page being a minimum write unit, for example, a storage page may be 64KB (i.e., 128 storage sectors) in size; however, this is not a limitation of the present application. In addition, the flash memory module 120 may be a stereo NAND type flash memory module.

In one embodiment, the memory device 100 may be a portable memory device, such as a memory card conforming to SD/MMC, CF, MS or XD specifications, and the host 130 may be an electronic device capable of connecting to the portable memory device, such as a mobile phone, a laptop computer, a personal computer, or the like. In another embodiment, the memory device 100 may be a Solid State Drive (SSD) or an Embedded Storage device conforming to the specification of a Universal Flash Storage (UFS) or an Embedded multimedia Card (EMMC). The memory device 100 may be disposed in an electronic device, such as a mobile phone, a laptop computer, a personal computer, etc., and the host 130 may be a processor in the electronic device.

In this embodiment, the buffer memory 113 and/or the DRAM 140 may be used as a cache (or controller cache) of the flash controller 110 to temporarily store data sent from the host 130 before the data is written to the flash memory module 120, so that if the host 130 sends a read command requesting to read the data and the data is still buffered in the cache, the data temporarily cached in the cache can be immediately or quickly retrieved from the cache to send the data to the host 130. The cache of the flash controller 110 may be a buffer memory 113 included within the controller 110, or may be at least a portion of a dram 140 externally coupled to the controller 110, and/or a combination of the buffer memory 113 and the dram 140.

In practice, when the host 130 sends a write command with data to the controller 110 to control the controller 110 to write the data into the flash memory module 120, the data is temporarily stored in a data cache, such as the dram 140 (but not limited thereto). When the amount of data stored in the buffer memory 113 or the dram 140 reaches a predetermined value (e.g., the amount of data corresponds to one or more word lines of the flash memory module 120 or a storage page size), the data is moved from the cache and then written to the flash memory module 120. in the embodiment, when the host 130 sends a read command to request data at a logical address recorded in the cache, the flash controller 110 may directly access the cache to send the data to the host 130 without/without accessing the flash memory module 120. Thus, the response time of the flash controller 110 may be reduced.

A conventional flash memory controller needs to search all logical addresses of all data temporarily stored in a controller cache to ensure that valid data is being retrieved by the flash memory controller. In order to increase the search speed and reduce the latency in accessing the cache (e.g., the dram 140 in particular), the processor 112 is arranged to create a binary tree with a reduced or reduced number of nodes, i.e., to optimize the binary tree, based on the data size/length of a minimum write unit of the flash memory module 120 when the data is received from the host 130 or the same or different data sizes/lengths corresponding to different write commands sent from the host 130, as compared to the prior art.

When the host 130 sends the read command to the flash controller 110, the processor 112 can search the logical address through the binary tree to obtain the required data more quickly, which greatly improves the efficiency of the flash controller 110 and reduces the latency of accessing the cache, so as to reduce the latency of accessing the DRAM 140. If the cache is implemented using the dram 140, the binary tree created using a smaller or minimum number of nodes can significantly reduce the latency of the dram 140, so as to effectively reduce the response time of the controller 110, since accessing the cache based on the cache information (host-based cache information or flash-based cache information) of a corresponding node of the binary tree may also cause some delay.

Fig. 2 to 5 respectively show schematic diagrams of an embodiment of operations of the controller 110 to establish and update the binary tree 220 when the flash controller 110 receives data from the host 130 according to the embodiment of the present application.

The host 130, for example, sequentially sends a first write command, data D1 and corresponding logical address LBA0, a second write command, data D2 and corresponding logical address LBA64, and a third write command, data D3 and corresponding logical address LBA192 to the controller 110 to write the aforementioned data to the flash memory module 120, wherein the data D1, for example, has a data size of 64 storage sectors, the data D2, for example, has a data size of 128 storage sectors, and the data D3, for example, has a data size of 256 storage sectors, one storage sector refers to a smaller storage unit of a flash memory, for example, one storage page includes 128 storage sectors, which is not a limitation of the present application.

For example, the memory device 100 operates in a sequential write mode in the host 130 and is allowed to continuously send and write a larger amount of data to the memory device 100, but this is not a limitation of the present application, and the memory device 100 may operate in a single write mode, or the host 130 may sequentially write a plurality of different data with the same amount of data to the memory device 100, that is, the host 130 may be arranged to sequentially write data with the same or different amounts of data to the memory device 100.

In FIG. 2, the host 130 sends the first write command, data D1 and the corresponding logical address LBA0 to the flash controller 110, and the core C0 stores the data D1 corresponding to the logical address LBA0 in a cache, such as the DRAM 140 (the DRAM 140 is illustrated as an example and not limited thereto), in this embodiment, the data D1 is stored in a region corresponding to a cache index "0" of the DRAM 140, wherein the cache index is also referred to as a DRAM index, and the DRAM 140 includes a data size of the data table 21 recording the cache index "0", the corresponding logical address LBA0 and data D1, wherein the data size is defined by the number of storage blocks, i.e., the storage block length "64", and the cache index indicates that a specific data is stored in a storage region of the DRAM 140 For example, the relationship between the dram index and the length of the storage sector corresponds to the data size of eight storage sectors in the dram 140 (but not limited thereto) each time the value of the dram index is increased by 1, and in other embodiments, the number of the storage sectors may vary. The starting position of the data D1 in a storage area of the dram 140 is "0", and the length of the storage section is "64", so that the starting position of the next data (i.e. the data D2) in a storage area of the dram 140 will be "8".

The core C0 also sends the cache information (i.e., host-based cache information including the cache index "0", logical address LBA0, and store block length "64") to the core C1 to indicate that data D1 is stored in the DRAM 140. Next, when core C1 is idle (e.g., during busy hours of the flash module 120), core C1 may begin building the binary tree 220 based on the cache information sent from core C0.

Taking fig. 2 as an example, the LBA0 is node N0 (top node) of the binary tree, and the binary tree 220 also records the node information, which includes node index "0", LBA0, CNT of LBA0, cache index "0", node index of the left node (left child node), node index of the right node (right child node), and length of storage section "64", where CNT is equal to 0 since there is only one LBA0 in the dram 140, and the node indexes of the left node and the right node are "FFFF" since there is no node following the top node corresponding to LBA0 in this condition.

Next, in FIG. 3, the host 130 sends the second write command and the data D2 corresponding to the logical address LBA64 to the flash controller 110 shown in FIG. 3, and the core C0 stores the data D2 corresponding to the logical address LBA64 to the DRAM 140. In the embodiment, the data D2 is stored in a region of the DRAM 140 corresponding to a cache index "8", and the data table 210 records the cache index "8", the corresponding logical address LBA64 and the storage block length "128". The starting position of the data D2 in the storage area of the DRAM 140 is 8, and the data D2 has a data size of 128 sectors, so that the starting position of the next data (i.e. data D3) in the storage area of the DRAM 140 is 24. At the same time, core C0 sends the cache information (i.e., the cache index "8", logical address LBA64, and the bucket length "128") to core C1 indicating that data D2 is stored in DRAM 140. Next, when core C1 is idle, core C1 updates the binary tree 220 based on the cache information sent from core C0.

Taking fig. 3 as an example, since the logical address LBA64 is greater than the logical address LBA0, the logical address LBA64 follows the top node of the binary tree and becomes the right node of the binary tree, and the binary tree 220 records node information thereof, which includes the node index "1", the logical address LBA64, the number of times of repetition count CNT of the logical address LBA64 (since the dram 140 currently has only one logical address 64, the number of times of repetition count CNT equals 0), the cache index "8", the node index of the left node, the node index of the right node, and the length of the storage section "128", wherein the node indexes of the left node and the right node are both "FFFF" since no node follows the node corresponding to the logical address LBA 64. Further, since the node index "1" corresponding to the logical address LBA64 is added to the right node of the node N0 corresponding to the logical address LBA0, the right node of the node N0 is updated to "1".

Next, in FIG. 4, the host 130 sends the third write command and the data D3 corresponding to the logical address LBA192 to the flash controller 110 shown in FIG. 4, and the core C0 stores the data D3 corresponding to the logical address LBA192 in the DRAM 140. In the present embodiment, the data D3 with a data size of 256 storage sectors is stored in a region of the DRAM 140 corresponding to a cache index "24", and the data table 210 records the cache index "24", the corresponding logical address LBA192 and the storage sector length "256". At the same time, core C0 sends the cache information (i.e., the cache index "24", logical address LBA192, and the bucket length "256") to core C1 to indicate that data D3 is stored in DRAM 140. Next, when core C1 is idle, core C1 updates the binary tree 220 based on the cache information sent from core C0.

Taking fig. 4 as an example, since the logical address LBA192 is greater than the logical address LBA64, the node index "2" corresponding to the logical address LBA192 is located at a right node of the node index "1" of the logical address LBA64 of the binary tree, and the binary tree 220 records node information thereof, wherein the node information includes the node index "2", the logical address LBA192, the number of times of repetition count CNT of the logical address LBA192 (since only one logical address LBA192 exists in the dram 140, the number of times of repetition count CNT is equal to 0), the cache index "24", the node index of the left node, the node index of the right node, and the length of the storage section "256", wherein since no node follows the LBA192, the node indexes of the left node and the right node are "FFFF". In addition, since the node index "2" corresponding to the logical address LBA192 is added to the right node of the node index "1" corresponding to the logical address LBA4, the content of the right node of the node index "1" is updated to the node index "2".

In one embodiment, if the flash controller 110 receives a read command from the host 130 containing the logical address LBA64, for the binary tree 220 shown in FIG. 4, the processor 112 compares the logical address LBA64 with the logical address LBA0 of the top node of the binary tree 220, and since the logical address LBA64 is greater than the logical address LBA0, the processor 112 will find the right node of the top node in the next step. Then, since the right node of the top node of the binary tree 220 corresponds to the logical address LBA64 and the logical address LBA64 matches the logical address required by the read command, the processor 112 can refer to the cache index "8" of the binary tree 220 to obtain the cache address of the required data, and the processor 112 controls the DRAM controller 114 to read the data D2 stored in the area corresponding to the cache index "8" and transmit the data D2 to the host 130 through the interface circuit 111 without accessing the flash memory module 120. In view of the above, the embodiment of the present invention can find the required data in two steps, which greatly improves the searching speed compared to the conventional method that has to find the required data in three steps.

In addition, if the flash controller 110 receives a read command from the host 130 containing the LBA7, the processor 112 can determine that the LBA7 is not stored in the DRAM 140 as illustrated in the binary tree 220 of FIG. 4. The processor 112 can then control the control logic 116 to read the data with the logical address LBA7 from the flash memory module 120 and then send the data to the host 130 through the interface circuit 111. The flash controller 110 can quickly determine whether the LBA7 is stored in the cache (e.g., the DRAM 140) to increase the read speed of the flash controller 110.

In one embodiment, the core C1 may rearrange the binary tree 220 to reduce its number of layers when idle. For example, the core C1 may use a self-balancing binary search tree algorithm (self-balancing binary search tree algorithm), such as an AVL tree or a red-black tree (red-black tree), to reduce the number of levels. Taking fig. 5 as an example, the binary tree 220 may be rotated such that the node N1 of the logical address LBA64 becomes the top node, and the node N0 of the logical address LBA0 becomes a left node of the node N1 of the logical address LBA64, whereby the binary tree 220 may be updated from level 3 to level 2, and the search speed thereof may be further improved.

For implementing the cache using the dram 140, the flash controller 110 is used, for example, to control the dram controller 114 and the control logic 116 to move and write the data size of the minimum write unit (e.g., one page) from the data buffered in the cache to the flash memory module 120 each time the data amount of the data to be written to the flash memory module 120 reaches a predetermined value, such as one or more pages, one or more word lines, or other data amounts. Core C0 is arranged to update the information recorded in the data table 210 accordingly and to send appropriate information to core C1 to inform core C1 about the information that binary tree 220 should be updated, which core C1 may update when idle to remove the relevant information.

The data size of a minimum write unit is, for example, a storage page size, such as an amount of data equal to 64KB (i.e., 128 storage blocks); this is not a limitation of the present application. In other words, data of a size of one storage page (e.g., data of 128 storage sectors) is moved from the dynamic random access memory 140 and then written into a corresponding storage page of the flash memory module 120, such that, in practice, data of 128 storage sectors formed by the data D1 and a portion of the data D2 (e.g., the first half of the data D2), i.e., all contents of the data D1 and contents corresponding to the cache index "8" and a portion of the data D2 having the storage sector length "64", are moved from the dynamic random access memory 140 and then written into a storage page of the flash memory module 120. Then, another data of 128 sectors formed by another portion of the data D2 (e.g., the second half of the data D2 and a portion of the data D3), i.e., another portion of the data D2 corresponding to the cache index "16" and having the sector length "64", and a portion of the data D3 corresponding to the cache index "24" and having the sector length "64", is moved from the DRAM 140 and then written to the next page of the flash memory module 120. That is, if the data amount of the plurality of different specific data written from the host 130 is respectively different from the data amount of the minimum writing unit of the flash memory module 120, the different specific data are not sequentially and individually written into the flash memory module 120.

Fig. 6 to 8 are schematic diagrams illustrating an exemplary operation of the controller 110 for updating the binary tree 220 in fig. 4 when data of 128 sectors formed by the data D1 and the previous half of the data D2 are moved and then written into one page of the flash memory module 120. As shown in FIG. 6, in this case, all the contents of data D1 and the data of the 128 sectors formed by the previous half of data D2 are moved from DRAM 140 to flash module 120. Since all of the data D1 is being moved from DRAM 140 to flash module 120, core C0 deletes the corresponding cache information (i.e., cache index "0", LBA0, and block length "64") and informs core C1 that the cache information was deleted. Core C1 is then arranged, when idle, to delete the node with node index "0" from binary tree 220 and reset its corresponding node information to the default value "FFFF". For example, for node index "0", the logical address LBA is reset to "FFFF", the number of times CNT is reset to "0", the cache index is reset to "FFFF", the left node is reset to "FFFF", the right node is reset to "FFFF", and the storage block length is reset to "FFFF". The node of the node index "1" becomes the top node, and the node information of the node index "1" and the node information of the node index "2" are not changed. It should be noted that the data table 210 can be maintained or updated by the core C1 without using the core C0 when the buffered data is being flushed from the cache to the flash memory module 120.

Next, since the first half of data D2 was moved from DRAM 140 to flash module 120, core C0 is used to update the cache in table 210, and core C1 updates binary tree 220 when idle. For example, as shown in FIG. 7, the core C0 is used to update the original cache information (i.e., cache index "8", logical address LBA64 and store block length "128") to a new cache information (i.e., cache index "16", logical address LBA128 and store block length "64"). Core C1, when idle, deletes the node with node index "1" from binary tree 202 and resets the corresponding information to the default value "FFFF". For example, for the node index "1", the logical address LBA is reset to "FFFF", the repetition count number CNT is reset to "0", the cache index is reset to "FFFF", the left node is reset to "FFFF", the right node is reset to "FFFF", and the storage block length is reset to "FFFF", the node index "2" node becomes the top node, and the node information of the node index "2" is not changed.

As shown in FIG. 8, core C0 notifies core C1 of the contents of the new cache information (i.e., cache index "16", logical address LBA128 and store block length "64") and core C1 updates the binary tree 220 based on the new cache information. For example, the core C1 adds or inserts a node N3 with node index "3" into the left child node of the node with node index "2", wherein the node information of node N3 with node index "3" includes the logical address LBA128, the number of iterations CNT equal to 0, the cache index "16", the left node "FFFF", the right node "FFFF", and the store block length "64", and the node index of the left node is updated to "3" for the node with node index "2".

That is, for a specific data cached in the dram 140 and to be written into the flash memory module 120 by the host 130, if the data size of the specific data is different from the data size of a minimum write unit (e.g., a page), in the present embodiment, each time a portion of the specific data is moved from the dram 140 to the flash memory module 120, the core C1 deletes a corresponding node and resets cache information according to one or more cache indexes corresponding to the remaining portion of the specific data and then adds or inserts a new node and corresponding cache information into the binary tree.

Fig. 9 is a flowchart illustrating a method for creating or updating the binary tree 220 when receiving data from the host 130 according to an embodiment of the present application. With reference to fig. 1-4 and the above paragraphs, the steps of the method flow of fig. 9 are described as follows:

step 900: starting;

step 902: receiving data from the host 130;

step 904: core C0 stores or buffers the received data in a cache internal to the flash controller;

step 906: the core C0 uses the data table 210 to record cache information including a cache index, a logical address, and a data length of the received data;

step 908: core C0 sends the cache information to core C1;

step 910: core C1 determines whether a binary tree has been established; if no binary tree is established, flow proceeds to step 912, otherwise flow proceeds to step 914;

step 912: the core C1 builds a binary tree, which includes a top node and corresponding cache information, the cache information records that the node index of the top node is "0", the logical address, the cache index, the left node, the right node and the data length of the received data;

step 914: the core C1 compares the logical address of the received data with the logical addresses of one or more nodes in the binary tree to establish a node corresponding to the logical address of the received data and record corresponding cache information, wherein the cache information includes a corresponding node index, the logical address, the cache index, a left node, a right node, and a data length of the received data;

step 916: the flash controller 110 determines whether the data size of the data stored in the cache reaches a predetermined value (e.g., a data size of a storage page); if the data size of the data stored in the cache reaches the predetermined value, the process proceeds to step 918, otherwise, the process proceeds to step 902 to receive the next data from the host 130;

step 918: core C1 transfers a page size of data from the cache (e.g., DRAM 140) to the flash module 120 by controlling the DRAM controller 114 and control logic 116;

step 920: if necessary, deleting one or more nodes from the binary tree and resetting corresponding cache information to a default value "FFFF" when the core C1 is idle and then adding a new node and corresponding cache information to the binary tree, wherein the new node is used to indicate a remaining portion of the data and another portion of the data has been moved from the cache to the flash memory module 120; and

step 922: and (6) ending.

In other embodiments, to reduce the computational/computational cost of deleting and adding nodes by core C1, flash controller 110 may be able to build binary tree 220 based on the minimum write unit (e.g., a page of flash memory module 120).

Fig. 10 to 12 are schematic diagrams respectively illustrating operations of the controller 110 for establishing and updating the binary tree 220 when the flash controller 110 receives data from the host 130 according to another embodiment of the present application. The host 130, for example, sends the first write command, data D1 and logical address LBA0, the second write command, data D2 and logical address LBA64 having 128 sectors, and the third write command, data D3 and logical address LBA192 having 256 sectors to the controller 110 in sequence, so as to write the data to the flash memory module 120, wherein data D1, for example, has a data size of 64 sectors, data D2, for example, has a data size of 128 sectors, and data D3, for example, has a data size of 256 sectors, a sector is a smaller unit of the flash memory, for example, a page may include 128 sectors. The host 130 may write a larger amount of data to the memory device 100 using, for example, a sequential write mode. Furthermore, in the present embodiment, it is assumed that the data size of the minimum write unit (e.g., a storage page) is equal to 128 storage sectors (but not limited thereto). Core C0 is arranged to determine whether host 130 used the sequential write mode to write data. If the sequential write mode is used, then core C0 will store a larger amount of data to a cache, such as a DRAM 140, and then the stored data will be sequentially moved from the cache to the flash module 120; this is not a limitation of the present disclosure.

In FIG. 10, when the host 130 sends the first write command, data D1 and LBA0 to the flash controller 110, the core C0 stores the data D1 and LBA0 to the cache memory, such as the DRAM 140 (but not limited to). The data D1 is stored in the area of the DRAM 140 corresponding to both the cache index "0" and the storage block length "64", and the DRAM 140 includes the data table 210, the data table 210 records the cache index "0", the corresponding logical address LBA0 and the storage block length "64". In this case, the data D2 having a data size of 128 storage sections has not been received yet. Since the total data size (i.e., data D) currently cached in dram 140 is equal to 64 sectors and less than the sector length of one page (i.e., 128 sectors), core C0 is arranged not to generate flash-based cache information to core C1 and accordingly considers or determines data D1 as a remaining data portion R1, wherein core C0 records remaining data information in a storage portion of dram 140, the remaining data information including an initial cache index of the remaining data portion R1 and a corresponding sector length that has not been used to generate flash-based cache information, i.e., the cache index "0" and the sector length "64", as shown in fig. 10. Core C0 then waits to receive the next transaction from host 130. The core C0 waits for data from the host 130 until the amount of data currently buffered in the dram 140 is greater than or equal to 128 sectors (i.e., equal to the data size of a page (i.e., the number of sectors)), and the core C0 does not wait for data from the host 130. Since core C0 does not generate and send flash-based cache information to core C1 in this case to inform core C1 about this information, core C1 does not add or update a node to the binary tree 220. As indicated in fig. 10, the binary tree 220 does not contain any nodes at this time.

Next, in FIG. 11, the host 130 sends the second write command, data D2 and LBA64 to the flash controller 110, and the core C0 stores the data D2 and LBA64 to the DRAM 140. Similarly, in the present embodiment, the data D2 is stored in the area corresponding to both the cache index "8" and the storage block length "128" of the DRAM 140, and the data table 210 records the cache index "8", the corresponding logical address LBA64 and the storage block length "128". In this case, the core C0 compares the total data amount currently buffered in the dram 140 with the number of the storage sections defined by the minimum write unit (e.g., one storage page), so as to know that the total data amount currently buffered in the dram 140 is greater than or equal to 128 storage sections, the core C0 arranges or considers the data D1 and the data D2 as a set of data formed by the data P1 of the minimum write unit and a remaining data portion R2 following the data P1, wherein the data P1 is formed by the first half of data D1 and data D2 and corresponds to a storage area defined by the cache index "0" and storage block length "128", the remaining data portion R2 is formed by the last half of data D2 and corresponds to a storage area defined by the cache index "16" and the storage block length "64". The core C0 determines that the logical address of the data P1 is LBA 0. Next, the core C0 notifies the core C1 of the contents of the flash-based cache information for data P1, including the cache index "0", logical address LBA0 and block length "128", by sending cache information to the core C1. In addition, the start cache index "16" of the remaining data portion R2 and the corresponding storage block length "64" are stored in DRAM 140 by core C0. Next, when core C1 is idle, core C1 updates the binary tree 220 with the flash-based cache information from core C0. For example, the logical address LBA0 is at node N0 (the top node) of the binary tree 220, and the binary tree 220 also records the node information thereof, which includes the logical address LBA0, the number of times of the logical address LBA0 is repeated (since there is only one logical address LBA0 in the DRAM 140, the number of times of the repeated count CNT is equal to 0), the cache index "0", the node index of the left node (left child node), the node index of the right node (right child node), and the length of the storage section "128" (since the data size of one page data is equal to 128 storage sections, the data length is equal to 128). In addition, the node indexes of the left node and the right node are both "FFFF", since in this case there is no node following the top node corresponding to logical address LBA 0. In addition, since the remaining data portion R2 still exists, core C0 is arranged to wait for the next data from host 130 to be received.

Next, in FIG. 12, the host 130 sends the third write command, data D3 and logical address LBA192 to the flash controller 110, and the core C0 stores the data D3 with a data size of 256 storage sectors and the logical address LBA192 to the DRAM 140. In the embodiment, the data D3 is stored in a storage area of the DRAM 140 corresponding to both the cache index "24" and the storage block length "256", and the data table 210 records the cache index "24", the corresponding logical address LBA192, and the storage block length "256". Similarly, the core C0 determines that the total data size formed by a portion (i.e., the second half portion) of the second data D2 and the entire third data D3 is larger than 128 storage sectors, the core C0 therefore organizes or treats the remaining data portion R2 and the third data D3 of FIG. 11 as a set of data formed by data P2, P3 and a remaining data portion R3 (following data P3), where data P2 and P3 correspond to the minimum write unit (e.g., a page), respectively, the data P2 corresponds to a storage area defined by the cache index "16" and the storage block length "128", the data P3 corresponds to a storage area defined by the cache index "32" and the storage block length "128", and the remaining data portion R3 corresponds to a storage area defined by the cache index "48" and the storage block length "64". The core C0 determines the logical address of data P2 as LBA128 and the logical address of data P3 as LBA 256. Next, the core C0 generates and sends flash-based cache information to the core C1 to inform the core C1 of the contents of the cache information, including the cache index "16", LBA128, and Bank Length "128" of data P2, and further including the cache index "32", LBA256, and Bank Length "128" of data P3. In addition, the start cache index "48" of the remaining data portion R3 and its corresponding storage block length "8" are stored in DRAM 140 by core C0. Next, when core C1 is idle, core C1 updates the binary tree 220 based on the flash-based cache information sent from core C0. For example, the data P2 corresponding to the logical address LBA128 is represented by node N1 (with node index "1") of the binary tree 220, and the information of node N1 records the logical address LBA128, the number of times of the logical address LBA128 is repeated (since there is only one logical address LBA128 in DRAM 140, the number of times of the repeated count CNT is equal to 0), the cache index "16", the node index of the left node (left child node), the node index of the right node (right child node), and the length of the storage block "128" (since the data size of a stored page data is equal to 128 storage blocks, the length is equal to 128). In addition, the node N1 follows the top node, so the node index of the right node of node N0 is updated to "1". In addition, the data P3 corresponding to the LBA256 is represented by the node N2 (with node index "2") of the binary tree 220. the information of node N2 records the LBA256, the LBA 256's repeat count CNT (since there is only one LBA256 currently in the DRAM 140, the CNT is equal to 0), the cache index "32", the node index of the left node (left child node), the node index of the right node (right child node), and the storage block length "128" (since the data size of a stored page data is equal to 128 storage blocks, the length is equal to 128). In addition, the node N2 follows the node N1, so the node index of the right node of the node N1 is updated to "2".

Similarly, the binary tree 220 shown in FIG. 12 can be rotated by core C1 such that the node of logical address LBA128 becomes the top node and the node of logical address LBA0 becomes the left node of the node of logical address LBA128, whereby the binary tree 220 can be updated from a level 3 architecture to a level 2 architecture and its node seek speed can be further improved; the operation thereof is similar to that of fig. 5, and will not be repeated here. Similarly, when data is transferred from dram 140 to flash module 120, the data table 210 is updated by core C0, and the binary tree 220 is updated by core C1.

In one embodiment, if the flash controller 110 receives a read command from the host 130 containing the logical address LBA64 and the corresponding data has not been removed from the DRAM 140, taking the binary tree 220 shown in FIG. 12 as an example, the core C1 compares the logical address LBA64 with the logical address LBA0 and the storage block length "128" of the top node of the binary tree 220, and the core C1 finds the top node because the logical address LBA64 falls within a storage space defined by the logical address LBA0 and the storage block length "LBA 36128". If the read command requests data defined by the LBA64 and the length of the storage sector "128", then the core C1 can find the node of the LBA0 and the node of the LBA128 in the binary tree 220 to obtain the corresponding cache information, so that the core C0 can send the corresponding data to the host 130 based on the cache information obtained from the core C1.

It should be noted that when data is moved from dram 140 to flash module 120 by moving one page at a time, core C1 may delete a corresponding node and information from binary tree 220 directly when idle, without having to calculate and add one or more nodes and corresponding node information to binary tree 220. Since the binary tree 220 can also be stored in the cache (e.g., DRAM 140), the amount of computation/cost and the frequency of accessing the DRAM 140 can be greatly reduced.

Furthermore, it should be noted that in other embodiments, the logical addresses of any two data sequentially sent from the host 130 to the controller 110 may not be consecutive. None of the above embodiment variations is in any way limiting of the present disclosure.

Fig. 13 is a flowchart illustrating a method for creating or updating the binary tree 220 when data is received from the host 130 according to another embodiment of the present application. Referring to fig. 10 to 12, the process steps of fig. 13 are described as follows:

step 1300: starting;

step 1302: receiving data from the host 130;

step 1304: core C0 stores or buffers the received data in a cache internal to flash controller 110;

step 1306: the core C0 uses the data table 210 to record cache information including a cache index, a logical address, and a data length of the received data;

step 1308: core C0 monitors the amount of data currently cached in the cache to determine whether to generate and send a flash-based cache to core C1; if the monitored amount of data is greater than or equal to the data size of a minimum write unit (e.g., the data size of a page of storage, such as 128 sectors), then the process continues to step 1310, otherwise the process continues to step 1302 to receive additional data;

step 1310: the core C0 generates and sends corresponding flash-based cache information to the core C1;

step 1312: core C1 creates or updates a binary tree based on the corresponding flash-based cache information;

step 1314: core C1 writes page size data to a page of flash memory module 120 by controlling the DRAM controller 114 and control logic 116 to move page size data from the cache (e.g., DRAM 140);

step 1316: the core C1 deletes one or more nodes from the binary tree while idle and resets the corresponding flash-based cache to the default value "FFFF" without adding new nodes to the binary tree; and

step 1318: and (6) ending.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.