1. A method for preventing read errors caused by over-erasure is characterized by comprising the following steps:

receiving an erasing pause instruction;

interrupting the erasing command to exit in response to the erasing pause command;

receiving a reading operation instruction;

and applying negative voltage to the storage units which do not need to execute the reading operation in the chip according to the reading operation instruction, and applying positive voltage to the storage units which need to execute the reading operation in the chip.

2. The method of claim 1, wherein the memory unit of the chip for interrupting the exit of the erase command in response to the erase halt command and the memory unit for executing the read command are located in the same column of the chip.

3. The method of claim 2, wherein the memory unit of the chip for interrupting the exit of the erase command in response to the erase halt command and the memory unit for executing the read command are located in two different blocks, and the two different blocks are located in the same column of the chip.

4. The method of claim 2, wherein the memory unit of the chip for interrupting the exit of the erase command in response to the erase halt command and the memory unit for executing the read command are located in two different sectors, and the two different sectors are located in the same column of the chip.

5. The method of claim 1, wherein a negative voltage is applied to the memory cells in the chip that are not required to be read by a negative charge pump, and the negative charge pump is activated when the erase command is interrupted in response to the erase pause command.

6. The method of claim 1, wherein a negative voltage is applied by a negative voltage circuit to memory cells in the chip that are not required to perform a read operation.

7. The method of claim 1, wherein a negative voltage is applied to the memory cells in the chip that do not need to be read by the negative voltage output power supply.

8. An apparatus for preventing a read error due to over-erase, comprising:

the pause instruction receiving module receives an erasing pause instruction;

the response quitting module responds to the erasing pause instruction and interrupts the erasing instruction to quit;

the read instruction receiving module receives a read operation instruction;

and the voltage application module applies negative voltage to the storage units which do not need to execute the reading operation in the chip according to the reading operation instruction and applies positive voltage to the storage units which need to execute the reading operation in the chip.

9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 7.

10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 7 by calling the computer program stored in the memory.

Background

During the erase of sector a (sector a) in array a (array a) by NOR FLASH, if a suspend command is received, if the internal algorithm flow is in the erase step (as shown in fig. 1), the step of repairing the "over-erased" cell is not suspended (i.e. branch 2), then there may be an error in reading the data of another sector B (sector B) in the same array a (array a) during the erase suspension, the read data is a random value (depending on the number and distribution of the "over-erased" cells in sector a, because the threshold voltage of the "over-erased" cells is generally negative, and if there are "over-erased" cells in sector B, 0v cannot turn off the "over-erased" cells, which generate current, resulting in an error in reading the data, as shown in fig. 2).

In order to avoid the above problems, the conventional method is as follows: after receiving the erase suspend instruction, the over-erase repair is executed first, and then the user suspend erase instruction is responded, so as to eliminate the read data error of the "over-erase" unit to other sectors (as shown in fig. 3), however, the over-erase repair usually needs a longer time and cannot meet the time requirement (Tsus) of the user to respond to the erase suspend.

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

The invention aims to provide a method, a device, a storage medium and a terminal for preventing reading errors caused by over-erasure, and aims to solve the problem that the prior art can not simultaneously give consideration to the time requirement of quickly executing response after a NOR FLASH receives an erasure pause instruction and avoid reading errors caused by over-erasure during pause.

The technical scheme of the invention is as follows: the technical scheme provides a method for preventing reading errors caused by over-erasure, which specifically comprises the following steps:

receiving an erasing pause instruction;

interrupting the erasing command to exit in response to the erasing pause command;

receiving a reading operation instruction;

and applying negative voltage to the storage units which do not need to execute the reading operation in the chip according to the reading operation instruction, and applying positive voltage to the storage units which need to execute the reading operation in the chip.

In the technical scheme, when an erasing pause instruction is received, the erasing pause instruction is immediately responded to, and the erasing instruction is interrupted to exit, so that the time requirement of instruction response is met; if a read operation instruction is received during the pause period of erasing, negative voltage is applied to the memory cells which do not need to execute the read operation in the chip, and positive voltage is applied to the memory cells which need to execute the read operation in the chip, so that the problem of reading data errors caused by the existence of over-erasing cells can be avoided.

Furthermore, the storage unit of the chip for interrupting the exit of the erasing instruction in response to the erasing pause instruction and the storage unit for executing the reading operation instruction are positioned in the same column of the chip.

Further, the storage unit of the chip for interrupting the exit of the erasing instruction in response to the erasing pause instruction and the storage unit for executing the reading operation instruction are positioned in two different blocks, and the two different blocks are positioned in the same column of the chip.

Further, the storage unit for interrupting the exit of the erasing instruction in response to the erasing pause instruction and the storage unit for executing the reading operation instruction in the chip are positioned in two different sectors, and the two different sectors are positioned in the same column of the chip.

Further, a negative voltage is applied to memory cells in the chip that are not required to perform a read operation by a negative charge pump that is activated in parallel with the erase command exiting in response to the erase pause command interrupting the erase operation.

Further, a negative voltage is applied by a negative voltage circuit to memory cells within the chip that are not required to perform a read operation.

Further, a negative voltage is applied to the memory cells in the chip that do not need to perform a read operation by the negative voltage output power supply.

This technical scheme still provides a device for preventing to cause the mistake of reading because of overerase, includes:

the pause instruction receiving module receives an erasing pause instruction;

the response quitting module responds to the erasing pause instruction and interrupts the erasing instruction to quit;

the read instruction receiving module receives a read operation instruction;

and the voltage application module applies negative voltage to the storage units which do not need to execute the reading operation in the chip according to the reading operation instruction and applies positive voltage to the storage units which need to execute the reading operation in the chip.

The present invention also provides a storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute any one of the methods described above.

The technical solution also provides a terminal, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used for executing any one of the methods by calling the computer program stored in the memory.

According to the method, when the erasing pause instruction is received, the erasing pause instruction is immediately responded to and interrupted to quit, the time requirement of instruction response is met, and the negative charge pump is started while the erasing pause instruction is responded; if a read operation instruction is received during the pause period of erasing, a negative voltage is applied to the storage units which do not need to execute the read operation in the chip through the negative charge pump, and a positive voltage is applied to the storage units which need to execute the read operation in the chip through the positive charge pump, so that the problem of reading data errors caused by over-erasing units can be avoided, and the response time requirement of the read instruction can be ensured.

Drawings

Fig. 1 is a schematic diagram of an erase algorithm in the prior art.

Fig. 2 is a block diagram in the prior art.

FIG. 3 is a flow chart of a prior art method for addressing read data errors caused by over-erasure during an erase pause.

FIG. 4 is a flowchart illustrating steps of a method for preventing a read error due to over-erase in the present invention.

FIG. 5 is a schematic diagram of an apparatus for preventing a read error due to over-erase in the present invention.

Fig. 6 is a schematic diagram of a terminal in the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 4, a method for preventing a read error caused by over-erase is applicable to a NOR FLASH chip, and specifically includes the following steps:

s1: an erase suspend instruction is received.

During the process of executing an erasing operation (block erase) or a sector (sector) in an Array (Array) of a chip, an erasing pause instruction sent by a user may be received; in a memory chip, generally, a sector has a size of 4096 bytes, a block has a size of 65536 bytes, and for a chip with a capacity of 128Mbit, 256 blocks are contained, and usually, part of the blocks are placed in the same array, for example, 32 blocks are placed in an array, and the substrates of the storage units in an array are connected together, so if data of another block or sector in the column is read during execution of an erase pause instruction in a certain block or sector in an array, a read data error may be caused because of over-erase units in the block or sector in which the erase pause instruction is executed.

S2: and interrupting the erasing instruction to exit in response to the erasing pause instruction.

S3: and receiving a read operation instruction.

In the chip, a sector for executing an erasing pause instruction and a sector for executing a reading operation instruction during the erasing pause are two different sectors, and the two different sectors are positioned in the same column of the chip; in the chip, the block for executing the erase pause instruction and the block for executing the read operation instruction during the erase pause are two different blocks, and the two different blocks are located in the same column of the chip. Because during the execution of the erase pause command on a certain sector/block, the user will not perform other operations on the sector/block to avoid data errors.

S4: and applying a negative voltage to the storage units which do not need to execute the reading operation in the chip according to the reading operation instruction, and applying a positive voltage (namely, a reading operation voltage) to the storage units which need to execute the reading operation in the chip and executing the reading operation.

The negative voltage output module can apply negative voltage to the storage unit which does not need to execute reading operation in the chip, and can be realized in different modes according to requirements: (1) applying negative voltage to the memory cells which do not need to execute read operation in the chip through a negative charge pump; because the negative charge pump is in a closed state when not in use and is opened only when in use, and the opening of the negative charge pump needs a certain time, the negative charge pump is started to apply negative voltage to all memory cells in the chip when the chip responds to the erase pause instruction, so that the quick response can be ensured without waiting for the opening of the negative charge pump when other operation instructions (such as a read operation instruction) are received subsequently. (2) And applying negative voltage to the memory cells which do not need to perform reading operation in the chip through a negative voltage circuit. (3) And applying negative voltage to the memory cells which do not need to perform read operation in the chip by using the negative voltage output power supply. And so on. The negative voltage applied to all memory cells within the chip may be set according to the performance of the memory cells of the chip, such as-1V.

In which a positive charge pump applies a positive voltage (i.e., a read operation voltage) to a memory cell requiring a read operation in a chip. Because the positive charge pump is always in the starting state, when a read operation instruction is received, the positive voltage can be quickly applied to the memory unit needing to be read in the chip in response. If the negative pressure output module is realized by adopting a negative charge pump, the negative charge pump needs to be started when responding to the erasing pause instruction so as to avoid influencing the response of the chip to the read operation instruction and ensure that the response speed of the instruction meets the requirement.

When an erasing pause instruction is received, the erasing pause instruction is immediately responded to, and the erasing instruction is interrupted to exit, so that the time requirement of instruction response is met; if a read operation instruction is received during the pause period of erasing, negative voltage is applied to the memory cells which do not need to execute the read operation in the chip, and positive voltage is applied to the memory cells which need to execute the read operation in the chip, so that the problem of reading data errors caused by the existence of over-erasing cells can be avoided.

As shown in fig. 5, an apparatus for preventing a read error due to over-erase includes:

a pause instruction receiving module 101 for receiving an erase pause instruction;

the response quitting module 102 is used for responding the erasing pause instruction and interrupting the erasing instruction to quit;

a read instruction receiving module 103 for receiving a read operation instruction;

and the voltage applying module 104 is used for applying a negative voltage to the storage units which do not need to execute the read operation in the chip according to the read operation instruction, applying a positive voltage to the storage units which need to execute the read operation in the chip and executing the read operation.

Referring to fig. 6, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.

In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: receiving an erasing pause instruction; interrupting the erasing command to exit in response to the erasing pause command; receiving a reading operation instruction; and applying negative voltage to the storage units which do not need to execute the reading operation in the chip according to the reading operation instruction, applying positive voltage to the storage units which need to execute the reading operation in the chip, and executing the reading operation.

Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.

An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: receiving an erasing pause instruction; interrupting the erasing command to exit in response to the erasing pause command; receiving a reading operation instruction; and applying negative voltage to the storage units which do not need to execute the reading operation in the chip according to the reading operation instruction, applying positive voltage to the storage units which need to execute the reading operation in the chip, and executing the reading operation. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.