1. A method for inhibiting programming crosstalk of an upper storage layer of a 3D NAND memory is characterized by comprising the following steps:

providing the 3D NAND memory, the 3D NAND memory comprising: the storage device comprises a plurality of stacked storage layers and a plurality of stacked pseudo storage layers positioned on the storage layers, wherein the uppermost storage layer in the plurality of stacked storage layers is a top storage layer, the pseudo storage layer adjacent to the top storage layer is a bottom pseudo storage layer, each storage layer is provided with a plurality of storage units, each pseudo storage layer is provided with a plurality of pseudo storage units which are arranged in the same way as the plurality of storage units, the plurality of storage units in the vertical direction and the plurality of pseudo storage units form a storage string, a lower selection transistor is arranged between the storage layer at the bottommost layer and a semiconductor substrate, and an upper selection transistor is also arranged on the pseudo storage layer at the topmost layer; when programming a certain memory cell in the top memory layer, applying the same programming voltage to control gates corresponding to the top memory layer and the bottom pseudo memory layer respectively; in programming, the upper select transistor is turned on and the lower select transistor is turned off.

2. The method for suppressing the program crosstalk of the top storage layer in the 3D NAND memory according to claim 1, wherein the step of applying the same program voltage to the control gates corresponding to the top storage layer and the bottom dummy storage layer at the same time comprises: connecting the top storage layer and the bottom dummy storage layer together while applying the same program voltage for operation.

3. The method of 3D NAND memory for suppressing top-level storage layer programming crosstalk as claimed in claim 1 wherein 3D NAND memory comprises: a semiconductor substrate; a stacked structure in which a control gate and an isolation layer are stacked on a semiconductor substrate; a plurality of passage holes penetrating the stacked structure; the storage structure is positioned in the channel hole and comprises a charge storage layer positioned on the side wall surface of the channel hole and a channel layer positioned on the side wall surface of the charge storage layer, each layer of control gate and the storage structure at the corresponding position form a storage layer or a pseudo storage layer, the storage structure in each channel hole forms a storage string, and the intersecting position of the storage structure in each channel hole and each control gate corresponds to a storage unit or a pseudo storage unit.

4. The method of 3D NAND memory for suppressing top-level memory layer program cross talk in a 3D NAND memory according to claim 3 wherein the charge storage layer comprises a blocking oxide layer on sidewall surfaces of the trench hole, a charge trapping layer on sidewall surfaces of the blocking oxide layer, and a tunneling oxide layer on sidewall surfaces of the charge trapping layer; the channel layer fills the remaining channel holes.

5. The method for suppressing the program crosstalk of the top storage layer in the 3D NAND memory as claimed in claim 3, wherein when one memory cell in the top storage layer is programmed, the same program voltage is applied to the control gates corresponding to the top storage layer and the bottom dummy storage layer respectively, and the same program voltage is applied to the channel layer corresponding to the memory cell to be programmed in the top storage layer, the high voltage is applied to the channel layer corresponding to the memory cell not to be programmed in the top storage layer, and the bias voltage is applied to the control gates corresponding to the dummy storage layers in the bottom dummy storage layer.

6. The method for suppressing the program crosstalk of the upper storage layer in the 3D NAND memory according to claim 5, wherein the bias voltage applied to the control gates corresponding to the plurality of dummy storage layers on the lower dummy storage layer is gradually reduced from a direction away from the lower dummy storage layer.

7. The method for suppressing the program crosstalk of the top storage layer in the 3D NAND memory as claimed in claim 3, wherein the top storage layer and the bottom dummy storage layer are separately operated to read only data in corresponding memory cells in the top storage layer when a read operation is performed.

8. The method for suppressing the program crosstalk of the top storage layer in the 3D NAND memory as claimed in claim 3, wherein the top storage layer and the bottom dummy storage layer are connected together to perform an operation when performing an erase operation, and data in the corresponding memory cell in the top storage layer and the corresponding dummy memory cell in the bottom dummy storage layer are erased.

9. The method of 3D NAND memory for suppressing top-level storage layer programming crosstalk of claim 1, wherein the 3D NAND memory further comprises: and the plurality of pseudo storage layers are positioned below the plurality of stacked storage layers, the lowest storage layer in the plurality of stacked storage layers is a bottom storage layer, and the pseudo storage layer adjacent to the bottom storage layer is a top pseudo storage layer.

10. The method of claim 9, wherein the bottom storage layer and the top dummy storage layer are connected together while applying the same programming voltage for operation when programming one of the memory cells in the bottom storage layer.

11. A3D NAND memory, comprising:

the memory device comprises a plurality of stacked memory layers and a plurality of stacked pseudo memory layers positioned on the memory layers, wherein the topmost memory layer in the plurality of stacked memory layers is a top memory layer, the pseudo memory layer adjacent to the top memory layer is a bottom pseudo memory layer, each memory layer is provided with a plurality of memory cells, each pseudo memory layer is provided with a plurality of pseudo memory cells which are arranged in the same way as the plurality of memory cells, the plurality of memory cells and the plurality of pseudo memory cells in the vertical direction form a memory string, a lower selection transistor is arranged between the memory layer at the bottommost layer and a semiconductor substrate, an upper selection transistor is further arranged on the pseudo memory layer at the topmost layer, the upper selection transistor is configured to be opened during programming, and the lower selection transistor is configured to be closed during programming;

when programming one memory cell in the top memory layer, the control gates corresponding to the top memory layer and the bottom dummy memory layer are configured to be applied with the same programming voltage.

12. The 3D NAND memory of claim 11 further comprising:

a semiconductor substrate; a stacked structure in which a control gate and an isolation layer are stacked on a semiconductor substrate; a plurality of passage holes penetrating the stacked structure; the storage structure is positioned in the channel hole and comprises a charge storage layer positioned on the side wall surface of the channel hole and a channel layer positioned on the side wall surface of the charge storage layer, each layer of control gate and the storage structure at the corresponding position form a storage layer or a pseudo storage layer, the storage structure in each channel hole forms a storage string, and the intersecting position of the storage structure in each channel hole and each control gate corresponds to a storage unit or a pseudo storage unit.

13. The 3D NAND memory of claim 12 wherein the charge storage layer comprises a blocking oxide layer on a sidewall surface of the trench hole, a charge trapping layer on a sidewall surface of the blocking oxide layer, and a tunneling oxide layer on a sidewall surface of the charge trapping layer; the channel layer fills the remaining channel holes.

14. The 3D NAND memory of claim 10 further comprising:

the storage system comprises a plurality of layers of stacked storage layers, a plurality of pseudo storage layers located below the plurality of stacked storage layers, wherein the lowest storage layer in the plurality of stacked storage layers is a bottom storage layer, and the pseudo storage layer adjacent to the bottom storage layer is a top pseudo storage layer.

15. The 3D NAND memory of claim 14 wherein the bottom storage layer and the top dummy storage layer are configured to apply the same programming voltage when programming a certain memory cell in the bottom storage layer.

Background

NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile storage products with low power consumption, light weight and good performance. At present, NAND flash memories with a planar structure are approaching the limit of practical expansion, and in order to further improve the storage capacity and reduce the storage cost per bit, NAND memories with a 3D structure are proposed.

In the 3D NAND memory structure, a stacked 3D NAND memory structure is realized by vertically stacking a plurality of layers of data storage units.

Existing 3D NAND memory structures include: a semiconductor substrate; a stacked structure in which a control gate and an isolation layer are stacked on a semiconductor substrate; a plurality of passage holes penetrating the stacked structure; the storage structure is positioned in the channel hole and comprises a charge storage layer positioned on the side wall surface of the channel hole and a channel layer positioned on the side wall surface of the charge storage layer, each layer of control gate and the storage structure at the corresponding position form a storage layer or a pseudo storage layer, the storage structure in each channel hole forms a storage string, and the intersecting position of the storage structure in each channel hole and each control gate corresponds to a storage unit or a pseudo storage unit.

In the prior art, when a memory layer, especially a certain memory cell (target memory cell) in an uppermost memory layer (top memory layer) is programmed, memory cells other than the target memory cell in the top memory layer are interfered by programming, and a threshold voltage is shifted.

Disclosure of Invention

The technical problem to be solved by the invention is how to prevent the programming crosstalk in the programming process of the top storage layer of the 3D NAND memory and prevent the threshold voltage from drifting.

The invention provides a method for inhibiting programming crosstalk of a top storage layer of a 3D NAND memory, which comprises the following steps:

providing the 3D NAND memory, the 3D NAND memory comprising: the storage device comprises a plurality of stacked storage layers and a plurality of stacked pseudo storage layers positioned on the storage layers, wherein the uppermost storage layer in the plurality of stacked storage layers is a top storage layer, the pseudo storage layer adjacent to the top storage layer is a bottom pseudo storage layer, each storage layer is provided with a plurality of storage units, each pseudo storage layer is provided with a plurality of pseudo storage units which are arranged in the same way as the plurality of storage units, the plurality of storage units in the vertical direction and the plurality of pseudo storage units form a storage string, a lower selection transistor is arranged between the storage layer at the bottommost layer and a semiconductor substrate, and an upper selection transistor is also arranged on the pseudo storage layer at the topmost layer;

when programming a certain memory cell in the top memory layer, applying the same programming voltage to control gates corresponding to the top memory layer and the bottom pseudo memory layer respectively; in programming, the upper select transistor is turned on and the lower select transistor is turned off.

Optionally, applying the same programming voltage to the control gates respectively corresponding to the top storage layer and the bottom dummy storage layer simultaneously to perform the operation includes: connecting the top storage layer and the bottom dummy storage layer together while applying the same program voltage for operation.

Optionally, the 3D NAND memory comprises: a semiconductor substrate; a stacked structure in which a control gate and an isolation layer are stacked on a semiconductor substrate; a plurality of passage holes penetrating the stacked structure; the storage structure is positioned in the channel hole and comprises a charge storage layer positioned on the side wall surface of the channel hole and a channel layer positioned on the side wall surface of the charge storage layer, each layer of control gate and the storage structure at the corresponding position form a storage layer or a pseudo storage layer, the storage structure in each channel hole forms a storage string, and the intersecting position of the storage structure in each channel hole and each control gate corresponds to a storage unit or a pseudo storage unit.

Optionally, the charge storage layer includes a blocking oxide layer on a sidewall surface of the trench hole, a charge trapping layer on a sidewall surface of the blocking oxide layer, and a tunneling oxide layer on a sidewall surface of the charge trapping layer; the channel layer fills the remaining channel holes.

Optionally, when programming a certain memory cell in the top storage layer, the same programming voltage is applied to the control gates corresponding to the top storage layer and the bottom dummy storage layer respectively to perform an operation, a low voltage is applied to the channel layer corresponding to the memory cell to be programmed in the top storage layer, a high voltage is applied to the channel layer corresponding to the memory cell not to be programmed in the top storage layer, and a bias voltage is applied to the control gates corresponding to the dummy storage layers on the bottom dummy storage layer.

Optionally, the bias voltage applied to the control gates corresponding to the plurality of dummy storage layers on the bottom dummy storage layer is gradually reduced from a direction away from the bottom dummy storage layer.

Optionally, when performing a read operation, the top storage layer and the bottom pseudo storage layer are separately operated, and only data in a corresponding storage unit in the top storage layer is read.

Optionally, when performing an erasing operation, the top storage layer and the bottom pseudo storage layer are connected together to perform an operation, and data in the corresponding storage unit in the top storage layer and the corresponding pseudo storage unit in the bottom pseudo storage layer are erased.

Optionally, the 3D NAND memory further comprises: and the plurality of pseudo storage layers are positioned below the plurality of stacked storage layers, the lowest storage layer in the plurality of stacked storage layers is a bottom storage layer, and the pseudo storage layer adjacent to the bottom storage layer is a top pseudo storage layer.

Optionally, when programming one of the memory cells in the bottom memory layer, the bottom memory layer and the top dummy memory layer are connected together and operated by applying the same programming voltage.

In order to solve the above problems, the present invention also provides a 3D NAND memory comprising:

the memory device comprises a plurality of stacked memory layers and a plurality of stacked pseudo memory layers positioned on the memory layers, wherein the topmost memory layer in the plurality of stacked memory layers is a top memory layer, the pseudo memory layer adjacent to the top memory layer is a bottom pseudo memory layer, each memory layer is provided with a plurality of memory cells, each pseudo memory layer is provided with a plurality of pseudo memory cells which are arranged in the same way as the plurality of memory cells, the plurality of memory cells and the plurality of pseudo memory cells in the vertical direction form a memory string, a lower selection transistor is arranged between the memory layer at the bottommost layer and a semiconductor substrate, an upper selection transistor is further arranged on the pseudo memory layer at the topmost layer, the upper selection transistor is configured to be opened during programming, and the lower selection transistor is configured to be closed during programming;

when programming one memory cell in the top memory layer, the control gates corresponding to the top memory layer and the bottom pseudo memory layer are configured to apply the same programming voltage.

Optionally, the method further includes:

a semiconductor substrate; a stacked structure in which a control gate and an isolation layer are stacked on a semiconductor substrate; a plurality of passage holes penetrating the stacked structure; the storage structure is positioned in the channel hole and comprises a charge storage layer positioned on the side wall surface of the channel hole and a channel layer positioned on the side wall surface of the charge storage layer, each layer of control gate and the storage structure at the corresponding position form a storage layer or a pseudo storage layer, the storage structure in each channel hole forms a storage string, and the intersecting position of the storage structure in each channel hole and each control gate corresponds to a storage unit or a pseudo storage unit.

Optionally, the charge storage layer includes a blocking oxide layer on a sidewall surface of the trench hole, a charge trapping layer on a sidewall surface of the blocking oxide layer, and a tunneling oxide layer on a sidewall surface of the charge trapping layer; the channel layer fills the remaining channel holes.

Optionally, the method further includes:

the storage system comprises a plurality of layers of stacked storage layers, a plurality of pseudo storage layers located below the plurality of stacked storage layers, wherein the lowest storage layer in the plurality of stacked storage layers is a bottom storage layer, and the pseudo storage layer adjacent to the bottom storage layer is a top pseudo storage layer.

Optionally, when programming one of the memory cells in the bottom memory layer, the bottom memory layer and the top dummy memory layer are configured to apply the same programming voltage.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the 3D NAND memory and the method for inhibiting the programming crosstalk of the top storage layer, when one storage unit in the top storage layer is programmed, the top storage layer and the bottom pseudo storage layer are connected together and are simultaneously applied with the same programming voltage for operation, so that the same programming voltage is applied to the control gates corresponding to the top storage layer and the bottom pseudo storage layer, the potential of a channel region of a storage unit which does not need to be programmed in the top storage layer is the same as the potential of a channel region of a pseudo storage unit of the bottom pseudo storage layer, no potential fluctuation exists between the two, and hot carriers are not injected into a charge storage layer of the storage unit which does not need to be programmed in the top storage layer. Even if there is injection of hot carriers, the hot carriers are injected into only the charge storage layers corresponding to the dummy memory cells of the lower dummy storage layer (because the potential of the dummy memory cell channel region of the lower dummy storage layer fluctuates with the potential of the dummy memory cell channel region in the upper dummy storage layer, so that the hot carriers are injected into the charge storage layers of the dummy memory cells of the lower dummy storage layer), so that the threshold voltage of the memory cells in the top storage layer which do not need to be programmed does not drift, and is not subjected to the program crosstalk when the memory cells in the top storage layer which need to be programmed are programmed, and, even if hot electrons are injected into the charge storage layer of the dummy memory cell of the lower dummy memory layer, since the lower dummy memory layer is a non-memory layer, it does not participate in the storage of actual data and thus does not affect the performance of the 3D NAND memory. In addition, the method of the invention does not need to change the structure of the existing 3D NAND memory, and is convenient and simple.

Drawings

Fig. 1-2 are schematic structural diagrams illustrating a process of suppressing program crosstalk of a top storage layer in a 3D NAND memory according to an embodiment of the invention.

Detailed Description

As mentioned in the background, when programming a memory layer, especially a certain memory cell (target memory cell) in the uppermost memory layer (top memory layer), the memory cells other than the target memory cell in the top memory layer are interfered by the programming, and the threshold voltage is shifted.

Research finds that when a certain memory cell (target memory cell) of the top memory layer is programmed, a high programming voltage needs to be applied to the entire control gate corresponding to the top memory layer, that is, a high programming voltage is also applied to the control gate corresponding to the memory cell other than the target memory cell in the top memory layer, so that a potential between the word line and the other memory cells other than the target memory cell in the top memory layer is greatly reduced, and external partial hot electrons are injected into the charge storage regions of the other memory cells other than the target memory cell in the top memory layer, so that threshold voltages of the other memory cells other than the target memory cell in the top memory layer are shifted.

Further research shows that although several dummy memory layers can be formed on the top memory layer, and the drop of the channel potential can be buffered by adjusting the bias voltage applied to the gate corresponding to the dummy memory layer, the program crosstalk of the top memory layer can be reduced in this way, but the program crosstalk cannot be reduced without limit, that is, the problem of threshold voltage shift still exists in the top memory layer.

Therefore, the invention provides a 3D NAND memory and a method for inhibiting programming crosstalk of a top storage layer thereof, wherein when one memory cell in the top storage layer is programmed, the top storage layer and a bottom pseudo storage layer are connected together and are simultaneously applied with the same programming voltage for operation, so that threshold voltages of memory cells which do not need to be programmed in the top storage layer cannot drift, and the memory cells which need to be programmed in the top storage layer cannot be subjected to programming crosstalk when the memory cells are programmed.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Fig. 1-2 are schematic structural diagrams illustrating a process of suppressing program crosstalk of a top storage layer in a 3D NAND memory according to an embodiment of the invention.

Referring to fig. 1 and 2, there is provided the 3D NAND memory, the 3D NAND memory including: the storage system comprises a plurality of stacked storage layers 111 and a plurality of stacked pseudo storage layers 112 located on the storage layers 111, wherein the uppermost storage layer in the plurality of stacked storage layers 111 is a top storage layer 120, one pseudo storage layer adjacent to the top storage layer 120 is a bottom pseudo storage layer 121, each storage layer 111 is provided with a plurality of storage units, each pseudo storage layer 112 is provided with a plurality of pseudo storage units which are arranged in the same way as the plurality of storage units, and the plurality of storage units in the vertical direction and the plurality of pseudo storage layers form a storage string 31;

when one memory cell 20 of the top memory layer 120 is programmed, the top memory layer 120 and the bottom dummy memory layer 121 are connected together while applying the same programming voltage to perform an operation.

The specific structure of the 3D NAND memory, please refer to fig. 2, includes: a semiconductor substrate 100; a stacked structure in which a control gate 103 and an isolation layer 104 are stacked on a semiconductor substrate 100; a plurality of passage holes penetrating the stacked structure; and the memory structure 126 is positioned in the channel hole, the memory structure 126 comprises charge storage layers (122, 123 and 124) positioned on the side wall surfaces of the channel hole and a channel layer 125 positioned on the side wall surfaces of the charge storage layers, each control gate 103 and the memory structure 126 at the corresponding position form a storage layer 111 or a dummy storage layer 112, the memory structure in each channel hole forms a memory string (31a or 31b, refer to fig. 1), and the position where the memory structure in each channel hole intersects each control gate corresponds to a memory cell (20 or 21) or a dummy memory cell (42). In this embodiment, only two storage strings (31a and 31b) are taken as an example for explanation, and in other embodiments, the number of the storage strings may be other numbers.

The charge storage layer comprises a blocking oxide layer 122 positioned on the surface of the side wall of the channel hole, a charge trapping layer 123 positioned on the surface of the side wall of the blocking oxide layer 122 and a tunneling oxide layer 124 positioned on the surface of the side wall of the charge trapping layer 123; the channel layer 125 fills the remaining channel hole.

The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).

The number of layers of the stacked structure 111 is determined according to the number of memory cells and dummy memory cells to be formed in the vertical direction, the number of layers of the stacked structure 111 may be 8, 32, 64, or the like, and the greater the number of layers of the stacked structure 111, the higher the integration level can be. In this embodiment, the number of dummy storage layers 112 is 3 layers as an example, and in other embodiments, the number of dummy storage layers 112 may be other.

The material of the isolation layer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. In this embodiment, the material of the isolation layer 104 is silicon oxide.

The control gate 103 comprises a high-K dielectric layer and a metal gate positioned on the surface of the high-K dielectric layer, and the metal gate can be made of one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

HfO as the material of the high-K dielectric layer₂、TiO₂、HfZrO、HfSiNO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃Or BaSrTiO.

In other embodiments, the control gate 103 may include a silicon oxide dielectric layer and a polysilicon gate on the dielectric layer.

In one embodiment, a lower selection transistor is arranged between the bottommost storage layer 111 and the semiconductor substrate, the lower selection transistor comprises an epitaxial semiconductor layer 107 located at the bottom of the channel hole and control gates 131 of the lower selection transistor located on two sides of the epitaxial semiconductor layer 107, a buffer dielectric layer 101 is arranged between the control gates 131 of the lower selection transistor and the semiconductor substrate, and an isolation dielectric layer 132 is arranged between the control gates 131 of the lower selection transistor and the bottommost storage layer 111.

In one embodiment, the topmost dummy storage layer 112 further has an upper selection transistor thereon, the upper selection transistor includes an epitaxial semiconductor layer 137 on the channel layer 125, and an upper selection transistor gate 134 on both sides of the epitaxial semiconductor layer 137, the upper selection transistor gate 134 has an isolation dielectric layer 135 thereon, and the epitaxial semiconductor layer 137 is connected to bit lines (136a, 136 b).

Referring to fig. 1, in the embodiment, when programming the top memory layer 120, the process of connecting the top memory layer 120 and the bottom dummy memory layer 121 together while applying the same programming voltage to perform the operation includes: the same program voltage Vpgn is applied to the control gates of the top storage layer 120 and the bottom dummy storage layer 121 at the same time, a low voltage (0V applied through the bit line 136 a) is applied to the channel layer corresponding to the memory cell (memory cell 20) to be programmed in the top storage layer 120, a high voltage Vcc (0V applied through the bit line 136b) is applied to the channel layer corresponding to the memory cell (memory cell 21) not to be programmed in the top storage layer 120, and bias voltages (Vbias1, Vbias2) are applied to the control gates corresponding to the plurality of dummy storage layers 112 in the bottom dummy storage layer 121. Note that, in the programming, the upper selection transistor 141 is turned on, and the lower selection transistor 140 is turned off.

In this embodiment, through the foregoing operations, when programming the top storage layer 120, the top storage layer 120 and the bottom dummy storage layer 121 are connected together and the same programming voltage is applied to perform an operation, so that the control gates corresponding to the top storage layer 120 and the bottom dummy storage layer 121 are both applied with the same programming voltage Vpgn, so that the potential of the channel region of the memory cell (memory cell 21) in the top storage layer 120 that does not need to be programmed is the same as the potential of the channel region of the dummy memory cell 41 in the bottom dummy storage layer 121, there is no potential fluctuation between the two, and hot carriers are not injected into the charge storage layer of the memory cell (memory cell 21) in the top storage layer 120 that does not need to be programmed. Even if there is injection of hot carriers, the hot carriers are injected only into the charge storage layers corresponding to dummy memory cells 41 in lower dummy storage layer 121 (since program voltage Vpgn is applied to the control gates corresponding to lower dummy storage layer 121 and bias voltage Vbias1 (which is smaller than the program voltage) is applied to the control gates of dummy storage layers 112 in lower dummy storage layer 121, so that there is fluctuation between the potential of the channel regions of dummy memory cells 41 in lower dummy storage layer 121 and the potential of the channel regions of dummy memory cells 42 in dummy storage layers in lower dummy storage layer 121, and hot carriers are injected into the charge storage layers of dummy memory cells 41 in lower dummy storage layer 121), and thus the threshold voltages of memory cells (memory cells 21) in upper storage layer 120 that do not need to be programmed do not drift and do not suffer from program crosstalk when programming memory cells (memory cells 20) that need to be programmed in upper storage layer 120, hot electrons are injected into the charge storage layer of the dummy memory cell 41 of the lower dummy memory layer 121, but since it does not participate in the storage of actual data, it does not affect the performance of the 3D NAND memory.

In a specific embodiment, the magnitude of the program voltage Vpgn is 20V, the magnitude of the high voltage Vcc is 3.3V, the magnitude of the bias voltage Vbias1 is 10V, and the magnitude of the bias voltage Vbias2 is 7V.

In one embodiment, the bias voltage applied to the control gates corresponding to the plurality of dummy storage layers on the bottom dummy storage layer 121 is gradually decreased from a direction away from the bottom dummy storage layer, so that the potential of the channel of the dummy storage layer 112 is buffered and dropped to prevent the threshold voltage of the channel region of the dummy storage layer from drifting, thereby reducing the influence on the threshold voltage of the channel of the bottom dummy storage layer 121. Specifically, in this embodiment, the bottom dummy storage layer 121 further has two layers of dummy storage layers 112, a bias voltage Vbias1 and a bias voltage Vbias2 are correspondingly applied to control gates of the two layers of dummy storage layers 112, and the bias voltage Vbias2 is smaller than the bias voltage Vbias 1.

In one embodiment, during a read operation, the top storage layer 120 and the bottom dummy storage layer 121 are separately operated to read only data in corresponding memory cells in the top storage layer 120, and the bottom dummy storage layer is applied with a Vpass voltage of 7V.

In one embodiment, when performing an erase operation, the top storage layer 120 and the bottom pseudo storage layer 121 are connected together to perform an operation, and data in corresponding memory cells in the top storage layer and corresponding pseudo storage cells in the bottom pseudo storage layer are erased. That is, when an erase operation is performed, the corresponding control gates of the top and bottom dummy memory layers 120 and 121 are connected together while the same erase voltage is applied.

In other embodiments, the 3D NAND memory further comprises: and the plurality of pseudo storage layers are positioned below the plurality of stacked storage layers, the lowest storage layer in the plurality of stacked storage layers is a bottom storage layer, and the pseudo storage layer adjacent to the bottom storage layer is a top pseudo storage layer. When programming one memory cell in the bottom memory layer, connecting the bottom memory layer and the top dummy memory layer together and applying the same programming voltage to operate.

The process of connecting the bottom storage layer and the top dummy storage layer together and applying the same programming voltage to operate when programming a certain memory cell in the bottom storage layer is similar to or the same as the process of connecting the bottom storage layer and the top dummy storage layer together and applying the same programming voltage to operate when programming a certain memory cell in the bottom storage layer in the foregoing embodiment, and reference is specifically made to the definitions or descriptions of corresponding parts in the foregoing embodiment.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.