1. A reference unit replacement method, comprising:

receiving an erasing operation instruction;

measuring an output current of a reference unit, and when the output current of the reference unit is different from a design current of the reference unit, performing a replacement operation on the reference unit;

and executing the erasing operation according to the erasing operation instruction.

2. The reference cell replacement method of claim 1, wherein measuring the output current of the reference cell comprises:

selecting a reference unit according to the address information of the reference unit;

and acquiring the output current of the selected reference unit.

3. The reference cell replacement method according to claim 1 or 2, further comprising:

and switching to the next reference unit from the current reference unit for measurement after measuring one reference unit.

4. The reference cell replacement method of claim 3, wherein: the switching from the current reference unit to the next reference unit for measurement includes:

the address of the current reference cell is incremented so that the current address points to the address of the next reference cell.

5. The method of claim 1, wherein the performing the replacement operation on the reference cell comprises:

determining that at least one replacement unit is available to perform a replacement operation;

and selecting an available replacing unit to perform replacing operation on the reference unit.

6. The method of claim 5, wherein the selecting an available replacement unit to perform a replacement operation on the reference unit comprises:

programming replacement information according to the selected replacement unit when the reference unit is not replaced;

returning an error report when the reference cell has been replaced and there are no replacement cells of the reference cell available for replacement.

7. The method of claim 5, wherein the performing the replacement operation on the reference cell further comprises:

the replacement information is stored.

8. The method of claim 1, further comprising, after measuring the output current of the reference cell:

acquiring a design current of the reference unit;

an output current of a reference cell and a design current of the reference cell are input to a comparator circuit.

9. A reference unit replacement apparatus comprising at least one processor and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the reference cell replacement method of any one of claims 1 to 8.

10. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the reference cell replacement method of any one of claims 1 to 8.

Background

The reading circuit of the nonvolatile memory chip can be used for comparing the current of the memory cell and the current of the reference cell so as to judge whether the data of the memory cell is correct or not; however, as the memory chip is used, the reference cell will slowly age, and the generated current will have a deviation, which easily causes the memory chip to read by mistake and reduces the reliability of the memory chip.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the invention provides a reference unit replacing method, a reference unit replacing device and a storage medium, wherein the reference unit is measured and replaced in the erasing operation process, so that the performance of the reference unit is ensured, and the reliability of a storage chip is improved.

In a first aspect, an embodiment of the present invention provides a reference unit replacement method, including: receiving an erasing operation instruction;

measuring an output current of a reference unit, and when the output current of the reference unit is different from a design current of the reference unit, performing a replacement operation on the reference unit;

and executing the erasing operation according to the erasing operation instruction.

The reference unit replacing method provided by the embodiment of the invention at least has the following beneficial effects: when an erasing operation instruction is received, the reference unit is detected before the memory chip executes the erasing operation, and the reference unit with the problem is replaced, so that the problem that the reference unit gradually fails along with the increase of the service time of the memory chip can be effectively solved, and the reliability of the memory chip is improved; on the other hand, compared with the read-write operation, the erasing operation takes longer time, so that the reference unit detection is selected before the erasing operation, and the influence of the detection process on the read-write speed of the memory chip can be avoided.

In some embodiments, the measuring the output current of the reference cell comprises:

selecting one of the reference units according to the address information of the reference units;

and acquiring the output current of the selected reference unit.

In some embodiments, further comprising:

and switching to the next reference unit from the current reference unit for measurement after measuring one reference unit.

In some embodiments, the switching from the current reference cell to the next reference cell for measurement comprises:

the address of the current reference cell is incremented so that the current address points to the address of the next reference cell.

In some embodiments, said performing a replacement operation on said reference cell comprises:

determining that at least one replacement unit is available to perform a replacement operation;

and selecting an available replacing unit to perform replacing operation on the reference unit.

In some embodiments, the selecting an available replacement unit to perform a replacement operation on the reference unit includes:

programming replacement information according to the selected replacement unit when the reference unit is not replaced;

returning an error report when the reference cell has been replaced and there are no replacement cells of the reference cell available for replacement.

In some embodiments, said performing a replacement operation on said reference cell further comprises:

the replacement information is stored.

In some embodiments, after measuring the output current of the reference cell, further comprising:

acquiring a design current of the reference unit;

an output current of a reference cell and a design current of the reference cell are input to a comparator circuit.

In a second aspect, an embodiment of the present invention further provides a reference unit replacing apparatus, including at least one processor and a memory, communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the reference cell replacement method of the first aspect.

In a third aspect, the embodiment of the present invention further provides a computer-readable storage medium, where computer-executable instructions are stored, and the computer-executable instructions are configured to cause a computer to execute the reference unit replacement method according to the first aspect.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a general flow chart of a reference cell replacement method provided by an embodiment of the present invention;

FIG. 2 is a flow chart of a method for measuring an output current of a reference cell according to an embodiment of the present invention;

FIG. 3 is a flow chart of an alternative operation performed on a reference cell provided by an embodiment of the present invention;

FIG. 4 is a flowchart of a method for selecting an available replacement unit to perform a replacement operation according to an embodiment of the present invention;

FIG. 5 is a flow chart of a method for comparing a design current to an output current provided by an embodiment of the present invention;

FIG. 6 is an overall flow chart of a reference cell replacement method provided by an example of the present invention;

FIG. 7 is a flow chart of a particular method of measuring and replacing a reference cell provided by an example of the present invention;

FIG. 8 is a detailed flow chart of a reference cell replacement method provided by an example of the present invention;

fig. 9 is a schematic block diagram of a reference cell replacement apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The embodiment of the invention provides a reference unit replacing method, a reference unit replacing device and a storage medium, wherein before a memory chip executes erasing operation, the reference unit is measured, and the reference unit with problems is replaced according to the measurement result, so that the performance of the reference unit is maintained, and the reliability of the memory chip is improved.

The embodiments of the present invention will be further explained with reference to the drawings.

Referring to fig. 1, an embodiment of the present invention provides a reference unit replacement method, including, but not limited to, the following steps S100, S200, and S300.

Step S100, receiving an erasing operation instruction;

step S200, measuring the output current of the reference unit, and when the output current of the reference unit is different from the design current of the reference unit, performing replacement operation on the reference unit;

in step S300, an erase operation is performed according to the erase operation command.

In the prior art, a semiconductor memory product includes at least one memory chip, the memory chip generally includes a plurality of memory cells, and since the memory cells have a tunnel oxide layer, multiple times of PE (Program/Erase) of the memory cells may cause damage to the tunnel oxide layer, which affects data in the memory cells. Generally, the service life of the reference unit is often long, but the problem that the reference unit is damaged in the use process cannot be avoided, and at this time, the output current of the reference unit has deviation, so that the control chip easily makes a misjudgment that the storage unit corresponding to the reference unit is damaged, and further the reliability of the product is affected.

At present, a few schemes for repairing a reference cell are available, and it takes a long time to repair the reference cell, and when a user performs operations such as programming and reading during the repair of the reference cell, a delay occurs, which affects the experience of the user in using a product, so that the existing repair scheme sacrifices the response speed of the product, or can only perform the repair operation during the idle period of the product, and generally, the improvement is still needed.

Based on the method, the repair of the reference unit is daily normalized, after the memory unit receives the erasing operation instruction and before the normal erasing operation is carried out, the reference unit of the memory unit is detected, the reference unit with the problem is replaced, and then the normal erasing operation is carried out. Specifically, in step S100, when the driving chip receives an erase operation command, the process enters a reference cell detection process, in step S200, an output current of a corresponding reference cell is measured, the output current is compared with a design current, and when the output current is different from the design current, the reference cell is considered to be not in accordance with the design requirement, and the reference cell needs to be replaced to ensure the performance of the reference cell. When the replacement operation of step S200 is completed or the reference cell does not need to be replaced, a formal erase operation is performed according to the erase operation command, via step S300. Since the erase operation itself takes a lot of time, and the erase operation does not require much time efficiency compared to the program operation and the read operation, the reference cell is selected to be detected before the erase operation is performed, thereby avoiding unnecessary stuck. Because the reference unit of the memory unit of the erasing object is replaced, compared with full disk or partition detection/replacement, the single detection/replacement of the application takes less time and has little influence on the erasing operation. Through the replacement operation, the performance of the reference unit can be maintained, and the storage product can still ensure good reliability after being used for a long time.

It can be understood that, for two input signals which are very close but not absolutely equal, the comparator circuit has a certain judgment error, and in the present application, only if the difference between the output current of the reference unit and the design current is greater than a certain value, the comparator circuit will judge that the output current and the design current are different, so the expression "the output current and the design current are different" in the embodiment of the present application is substantially the expression that the judgment accuracy of the comparator circuit is considered, and as long as the difference between the output current and the design current is within the judgment accuracy of the comparator circuit, the output current and the design current are considered to be the same.

The number of reference cells is obviously more than one, each reference cell corresponding to a different address, so in step S200, the output current of the reference cell is measured, including but not limited to the following steps S210 and S220, refer to fig. 2:

step S210: selecting one of the reference units according to the address information of the reference units;

step S220: and acquiring the output current of the selected reference unit.

When the reference unit is measured, it is necessary to determine address information of the reference unit, perform an erase operation on the reference unit according to an erase operation command, erase the reference unit at the same time in the current erase operation, and obtain an output current of the reference unit (for example, by applying a voltage to a gate of the reference unit, reading the output current from a drain of the reference unit), which is to be input into a comparator circuit to be compared with a design current.

It will be appreciated that for a single erase operation, the number of reference cells involved is typically more than one, so that each time a reference cell is measured, the measurement is switched from the current reference cell to the next. Thus, each reference unit is measured in sequence, and the condition of omission and no measurement can be ensured. When all the reference cells are judged to be finished measuring, the reference cell measuring operation is finished, and the erasing operation can be formally started.

During the measurement process of switching the reference units, the switching may be performed in address order, that is, the address of the current reference unit is incremented to point to the address of the next reference unit. The reference cells are formed by wafer processing as well as the memory cells, and the address form of the reference cells generally corresponds to the address form of the memory cells, so the reference cells can also be located by addresses, for example, the addresses of the reference cells are determined by matching word lines and bit lines, and when the reference cells are switched, the next word line is selected according to the word line of the current address, so that the reference cells are switched to the corresponding reference cells in the next row.

Referring to fig. 3, the replacement operation is performed on the reference cell in the above-described step S200, including, but not limited to, the following steps S230 and S240.

Step S230, determining that at least one replacement unit is available for performing a replacement operation;

in step S240, an available replacement unit is selected to perform a replacement operation on the reference unit.

According to the existing storage product, a part of storage units are divided from the storage product and used as replacement units, the replacement units do not store data and are only used for replacing the storage units with errors when the storage units have errors, and therefore the overall reliability of the storage product is guaranteed. The application expands the use of the replacement unit, and when a problem occurs in the reference unit, the replacement unit is selected to replace the reference unit. Therefore, when the replacement operation is performed in step S200, it is required to determine that at least one replacement unit available for performing the replacement operation exists in the current storage product, and when there is an available replacement unit, one of the replacement units is selected to replace the problematic reference unit.

Of course, if there are no available replacement units in the current storage product, there is no way to replace the problematic reference unit. But in other cases the replacement unit is not suitable for replacing the reference unit despite the availability of the replacement unit, and at this point an error is reported to the master. Specifically, referring to fig. 4, the step S240 may further include the steps of:

step 241, when the reference unit is not replaced, programming replacement information according to the selected replacement unit;

in step S242, when the reference unit has been replaced and there is no replacement unit available for the replaced reference unit, an error report is returned.

Step S241, corresponding to the situation that the reference unit is successfully replaced for the first time, points the address of the reference unit to the replacement unit by programming the replacement information, and writes the relevant address replacement information into the master control, stores the replacement information, i.e., completes the replacement operation. Step S242 corresponds to the case where the reference cell has been replaced, and there are no spare replacement cells available, and an error is reported to the master.

It is understood that after measuring the output current of the reference unit, the following steps S250 and S260 are also included, but not limited to, with reference to fig. 5:

step S250, acquiring the design current of the reference unit;

in step S260, the output current of the reference cell and the design current of the reference cell are input to the comparator circuit.

The design current is typically a design value of the output current of the reference cell, which is used as a reference current value for comparison with the current output current value of the reference cell. In this embodiment, the comparator circuit is used to compare the output current with the design current, and when the current values received by the two input ends of the comparator circuit are different, the comparator circuit outputs a corresponding result (such as outputting a low level signal) to the main control, and the main control makes a judgment according to the result. It will be appreciated that there are many forms of comparator circuit, and in the case of the most conventional comparator, the comparator has a non-inverting input, an inverting input and an output, the non-inverting input and the inverting input being connected to the output current and the design current respectively, and the output being provided with a corresponding level signal by the comparator depending on the magnitude relationship between the two inputs.

The reference unit replacing method can measure the reference unit when the memory chip executes the erasing operation, and when the reference unit with the problem is measured, the reference unit is replaced, so that the accuracy of the reference unit in the using process is ensured, the problem that the main control mistakenly recognizes the corresponding memory unit as the reference unit has the fault due to the current deviation after long-time use is avoided, the reliability of the memory chip is ensured, and the service life of a memory product is prolonged.

The following describes an embodiment of the present invention with a practical example:

referring to fig. 6-8, the present example provides a reference cell replacement method, applied to a storage product having a storage cell, a reference cell and a replacement cell, specifically including the steps of:

step S400, receiving an erasing operation instruction;

step S500, measuring the reference unit and replacing the reference unit with problems in the measuring process;

in step S600, an erase operation is performed according to the erase operation command.

Referring to fig. 7, step S500 may specifically include the following steps:

step S510, determining all reference cells corresponding to the memory cells to be subjected to the erase operation;

step S520, selecting a reference unit for measurement;

step S530, obtaining the output current of the reference unit, inputting the output current of the reference unit and the design current into a comparator circuit, and judging whether the reference unit needs to be replaced according to the output result of the comparator circuit;

step 540, if the reference unit needs to be replaced, when a replacement unit available for replacement exists, performing replacement operation on the reference unit and jumping to step 560, and when no replacement unit available for replacement exists, sending an error report;

step S550, if the reference unit does not need to be replaced, judging whether all the reference units are tested, if so, jumping to the step S600, and if not, jumping to the step S560;

step S560, switch to the next reference cell and jump to step S530.

Through the steps, the reference unit is measured and replaced in the erasing process, the influence of the process on the read-write operation of a user is avoided, the reliability of the storage chip is guaranteed, and the service life of a storage product is prolonged.

The embodiment of the invention also provides a reference unit replacing device, which comprises at least one processor and a memory which is in communication connection with the at least one processor; the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the aforementioned reference cell replacement method.

Referring to fig. 9, it is exemplified that the control processor 1001 and the memory 1002 in the device 1000 may be connected by a bus. The memory 1002, which is a non-transitory computer-readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer-executable programs. Further, the memory 1002 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk memory, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1002 may optionally include memory located remotely from the control processor 1001, which may be connected to the device 1000 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Those skilled in the art will appreciate that the arrangement of devices shown in fig. 9 does not constitute a limitation of apparatus 1000, and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.

Also provided in an embodiment of the present invention is a computer-readable storage medium storing computer-executable instructions, which are executed by one or more control processors, for example, by one control processor 1001 in fig. 9, and which may cause the one or more control processors to perform the reference unit replacement method in the above-described method embodiment, for example, to perform method steps S100 to S300 in fig. 1, method steps S210 to S220 in fig. 2, method steps S230 to S240 in fig. 3, method steps S241 to S242 in fig. 4, method steps S250 to S260 in fig. 5, method steps S400 to S600 in fig. 6, and method steps S510 to S560 in fig. 7, which are described above.

The above-described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may also be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.