1. A circuit board fault detection method comprises the following steps:

acquiring a microscopic image of the circuit board;

determining a candidate fault area according to the microscopic image and a pre-trained image recognition model, wherein the image recognition model is used for representing the corresponding relation between the microscopic image and the fault area;

determining a test input node and a test output node according to the candidate fault area;

analyzing an output signal of the test output node in response to the test stimulus input to the test input node, and determining a fault feature vector;

and predicting the fault information of the circuit board based on the fault feature vector and a pre-trained fault prediction model, wherein the fault prediction model is used for representing the corresponding relation between the feature vector and the fault information.

2. The method of claim 1, wherein said determining a test input node and a test output node from said candidate fault region comprises:

scanning the candidate fault area and acquiring an amplified image of the candidate fault area;

and determining a test input node and a test output node according to the amplified image.

3. The method of claim 2, wherein said determining a test input node and a test output node from said magnified image comprises:

determining wiring of electronic components of the candidate fault area according to the enlarged image;

and determining a test input node and a test output node according to the wiring.

4. The method of claim 1, wherein said inputting a test stimulus to said test input node comprises:

receiving a selected instruction of a test stimulus;

inputting the test stimulus indicated by the selected instruction to the test input node.

5. The method of claim 1, wherein said analyzing the output signal of the test output node to determine a fault signature vector comprises:

and performing wavelet transformation on each path of output signals of the test output node to determine a fault characteristic vector.

6. The method of claim 1, wherein the predicting fault information for the circuit board based on the fault signature vector and a pre-trained fault prediction model comprises:

fusing the test input node, the test output node, the test excitation and the fault characteristic vector to obtain a fused vector;

and predicting the fault information of the circuit board according to the fusion vector and the fault prediction model.

7. The method of any of claims 1-6, wherein the method further comprises:

determining a solution aiming at the fault information according to the fault information and a preset information base;

based on the solution, a diagnostic report is generated.

8. The method of claim 7, wherein the method further comprises:

and receiving modification information aiming at the diagnosis report, and storing the modified diagnosis report.

9. The method according to any one of claims 1-8, wherein the image recognition model is obtained by the following training steps:

acquiring a training sample set, wherein each training sample in the training sample set comprises a sample circuit board image and a corresponding fault area;

and taking the sample circuit board image in each training sample as input, taking a fault area corresponding to the input sample circuit board image as expected output, and training to obtain the image recognition model.

10. A circuit board fault detection device comprising:

an image acquisition unit configured to acquire a microscopic image of the circuit board;

the image recognition unit is configured to determine a candidate fault area according to the microscopic image and a pre-trained image recognition model, and the image recognition model is used for representing the corresponding relation between the microscopic image and the fault area;

a node determination unit configured to determine a test input node and a test output node according to the candidate fault region;

a signal analysis unit configured to analyze an output signal of the test output node in response to input of a test stimulus to the test input node, determining a fault feature vector;

and the fault prediction unit is configured to predict fault information of the circuit board based on the fault feature vector and a pre-trained fault prediction model, and the fault prediction model is used for representing the corresponding relation between the feature vector and the fault information.

11. The apparatus of claim 10, wherein the node determination unit is further configured to:

scanning the candidate fault area and acquiring an amplified image of the candidate fault area;

and determining a test input node and a test output node according to the amplified image.

12. The apparatus of claim 11, wherein the node determination unit is further configured to:

determining wiring of electronic components of the candidate fault area according to the enlarged image;

and determining a test input node and a test output node according to the wiring.

13. The apparatus of claim 10, wherein the signal analysis unit is further configured to:

receiving a selected instruction of a test stimulus;

inputting the test stimulus indicated by the selected instruction to the test input node.

14. The apparatus of claim 10, wherein the signal analysis unit is further configured to:

and performing wavelet transformation on each path of output signals of the test output node to determine a fault characteristic vector.

15. The apparatus of claim 10, wherein the failure prediction unit is further configured to:

fusing the test input node, the test output node, the test excitation and the fault characteristic vector to obtain a fused vector;

and predicting the fault information of the circuit board according to the fusion vector and the fault prediction model.

16. The apparatus according to any one of claims 10-15, wherein the apparatus further comprises a report generation unit configured to:

determining a solution aiming at the fault information according to the fault information and a preset information base;

based on the solution, a diagnostic report is generated.

17. The apparatus of claim 16, wherein the apparatus further comprises a report modification unit configured to:

and receiving modification information aiming at the diagnosis report, and storing the modified diagnosis report.

18. The apparatus according to any of claims 10-17, wherein the apparatus further comprises a model training unit configured to derive the image recognition model by training steps of:

acquiring a training sample set, wherein each training sample in the training sample set comprises a sample circuit board image and a corresponding fault area;

and taking the sample circuit board image in each training sample as input, taking a fault area corresponding to the input sample circuit board image as expected output, and training to obtain the image recognition model.

19. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-9.

20. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-9.

21. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-9.

Background

With the rapid development of electronic technology, circuit boards are also widely used. Damage and failure of certain electronic circuits and components of the printed circuit board can cause the whole equipment not to work normally. As China is in an important period of converting from mechanization to informatization. Various integrated instruments and equipment integrate various new technologies, new materials and new processes, have high requirements on technical standards, very complex operation mechanism and high difficulty in maintenance and fault diagnosis, and the traditional guarantee means and fault diagnosis method can not be adapted to the requirements of information-based equipment guarantee construction.

Disclosure of Invention

The disclosure provides a circuit board fault detection method, a device, equipment and a storage medium.

According to a first aspect, there is provided a circuit board fault detection method comprising: acquiring a microscopic image of the circuit board; determining a candidate fault area according to the microscopic image and a pre-trained image recognition model, wherein the image recognition model is used for representing the corresponding relation between the microscopic image and the fault area; determining a test input node and a test output node according to the candidate fault area; analyzing an output signal of a test output node in response to the test excitation input to the test input node, and determining a fault characteristic vector; and predicting the fault information of the circuit board based on the fault characteristic vector and a pre-trained fault prediction model, wherein the fault prediction model is used for representing the corresponding relation between the characteristic vector and the fault information.

According to a second aspect, there is provided a circuit board fault detection apparatus comprising: an image acquisition unit configured to acquire a microscopic image of the circuit board; the image recognition unit is configured to determine a candidate fault area according to the microscopic image and a pre-trained image recognition model, and the image recognition model is used for representing the corresponding relation between the microscopic image and the fault area; a node determination unit configured to determine a test input node and a test output node according to the candidate fault region; a signal analysis unit configured to analyze an output signal of the test output node in response to input of a test stimulus to the test input node, determining a fault feature vector; and the fault prediction unit is configured to predict fault information of the circuit board based on the fault feature vector and a pre-trained fault prediction model, and the fault prediction model is used for representing the corresponding relation between the feature vector and the fault information.

According to a third aspect, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in the first aspect.

According to a fourth aspect, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method as described in the first aspect.

According to a fifth aspect, a computer program product comprising a computer program which, when executed by a processor, implements the method as described in the first aspect.

According to the technology disclosed by the invention, automatic fault detection can be carried out on the circuit board, the diagnosis speed is high, and the result accuracy is high.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is an exemplary system architecture diagram in which one embodiment of the present disclosure may be applied;

FIG. 2 is a flow diagram of one embodiment of a circuit board fault detection method according to the present disclosure;

FIG. 3 is a schematic diagram of one application scenario of a circuit board fault detection method according to the present disclosure;

FIG. 4 is a flow diagram of another embodiment of a circuit board fault detection method according to the present disclosure;

FIG. 5 is a schematic structural diagram of one embodiment of a circuit board fault detection apparatus according to the present disclosure;

fig. 6 is a block diagram of an electronic device for implementing a circuit board fault detection method of an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 illustrates an exemplary system architecture 100 to which embodiments of the circuit board fault detection method or circuit board fault detection apparatus of the present disclosure may be applied.

As shown in fig. 1, the system architecture 100 may include a circuit board 101, a microscope 102, a terminal device 103, a network 104, and a server 105. The microscope 102 is used for acquiring a microscopic image of the circuit board 101. During the acquisition process, the lens of the microscope 102 may be moved continuously to acquire microscope images of different areas of the circuit board 101.

The microscope 102 may transmit the acquired microscope image to the terminal device 103 and/or the server 105 through the network 104 during or after acquiring the microscope image. Network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, to name a few.

Various types of application programs, such as image processing type applications, etc., may be installed on the terminal device 103 and/or the server 105. The user can view the microscopic image or view the failure detection result using the terminal apparatuses 101, 102, 103.

The terminal apparatuses 101, 102, and 103 may be hardware or software. When the terminal devices 101, 102, 103 are hardware, they may be various electronic devices including, but not limited to, smart phones, tablet computers, e-book readers, car computers, laptop portable computers, desktop computers, and the like. When the terminal apparatuses 101, 102, 103 are software, they can be installed in the electronic apparatuses listed above. It may be implemented as multiple pieces of software or software modules (e.g., to provide distributed services) or as a single piece of software or software module. And is not particularly limited herein.

The server 105 may be a server that provides various services, such as a background server that provides various models for the terminal device 103. The background server may feed back the trained models to the terminal device 103, so that the terminal device 103 may perform image processing by using the models.

The server 105 may be hardware or software. When the server 105 is hardware, it may be implemented as a distributed server cluster composed of a plurality of servers, or may be implemented as a single server. When the server 105 is software, it may be implemented as multiple pieces of software or software modules (e.g., to provide distributed services), or as a single piece of software or software module. And is not particularly limited herein.

It should be noted that the circuit board fault detection method provided by the embodiment of the present disclosure may be executed by the terminal device 103, and may also be executed by the server 105. Accordingly, the circuit board fault detection apparatus may be provided in the terminal device 103, and may also be provided in the server 105.

It should be understood that the number of circuit boards, microscopes, terminal devices, networks, and servers in fig. 1 are merely illustrative. There may be any number of circuit boards, microscopes, terminal devices, networks, and servers, as desired for implementation.

With continued reference to fig. 2, a flow 200 of one embodiment of a circuit board fault detection method according to the present disclosure is shown. The circuit board fault detection method of the embodiment comprises the following steps:

step 201, obtaining a microscopic image of the circuit board.

When circuit fault detection is carried out, instruments are not used for measurement immediately under normal conditions, and abnormal parts possibly existing in the circuit are searched by naked eyes. And checking whether the resistor and the capacitor are obviously burnt or not, and whether the components are overheated, smoke or obviously scorched or not under the power-on condition. With the development of the technology, the printed circuit board is developed towards ultra-thin type, high density, multi-layer, high performance and the like. At present, the design and processing level of the printed circuit board reaches 0.2-0.3mm (aperture) and 0.10-0.12mm (line width and spacing), and the printed circuit board cannot be identified by naked eyes.

In this embodiment, the execution main body of the circuit board fault detection method may acquire a microscopic image of the circuit board in various ways. For example, the execution body may acquire a microscopic image of the circuit board from the microscope through a network. The microscope may be any of various microscopes capable of acquiring microscopic images of the circuit board. When the microscope collects the surface image of the circuit board, the detailed surface image of the circuit board is obtained by continuously zooming and moving the lens. Because the lens needs to be moved continuously to collect image information in the detection process, the naked eyes cannot concentrate on the image information for a long time, and the information is easy to miss. So that the microscopic image in this embodiment can contain more comprehensive circuit board information. It is understood that the microscopic image may be one or more. The multiple microscopic images may be the same size.

Step 202, determining candidate fault areas according to the microscopic images and the image recognition models trained in advance.

The execution subject may input the obtained microscopic image into a pre-trained image recognition model, and determine whether a candidate failure region exists in the microscopic image. Here, the failure region candidate may be an image region where scorching, blackening, or disconnection exists. The image recognition model can be used for representing the corresponding relation between the microscopic image and the fault region, and can be various machine learning algorithms, such as a convolutional neural network and the like.

In some specific implementations, the image recognition model may be a restianet network. The network structure of restianet may include four parts: ResNet (residual network), FPN (Feature Pyramid network), class subnet, and box subnet. ResNet and FPN are used for extracting multi-scale features, class subnet is used for target classification, and box subnet is used for object detection. The network mainly comprises a loss function of focal loss, can solve the problem of large difference between the number of positive samples and the number of negative samples, has very high performance and precision, and can accurately detect the defects on the surface of the circuit board. The defects mainly comprise: short circuit, open circuit, cold solder, missolder, etc. By using the image recognition model, the execution subject can mark the region where the defect is located, and the marked region can be called a candidate fault region.

Step 203, according to the candidate fault area, a test input node and a test output node are determined.

In this embodiment, the execution subject may perform the key detection on the candidate fault region, that is, determine the test input node and the test output node from the candidate fault region. Specifically, the execution body may take a node where a current enters the electronic component in the candidate fault region as a test input node, and a first node through which a current output in the candidate fault region passes as a test output node. Alternatively, the execution body may analyze nodes in the candidate fault region, and take each node as a test output node, and take a node that inputs a current to the test output node as a test input node.

Step 204, in response to the test stimulus input to the test input node, the output signal of the test output node is analyzed to determine a fault feature vector.

The diagnostic information available in the circuit board fault diagnosis is more (the circuit board tests are more in types, such as voltage, current, admittance and the like), and although the fault diagnosis of the circuit can be completed by using a single test method, the diagnostic result is more and unreliable. In circuit board fault diagnosis, the diversity of devices and the complexity of circuits determine that the fault modes of the circuits are necessarily diverse. Moreover, in the circuit board fault diagnosis, the measurement information often has large changes due to the change of the environment, the electromagnetic interference and the error of the measuring instrument.

In this embodiment, in order to sufficiently detect a fault of the circuit board, a plurality of test stimuli may be input to the test input node. Here, the test stimulus may be various signals, for example, a sinusoidal signal, a pulse signal, or the like. The test stimulus may be emitted by the test equipment. After inputting the test stimulus into the test input node, the execution body may derive an output signal from the test output node. In order to analyze the output signals corresponding to each path of test excitation, the execution main body may perform processing such as fusion on the output signals to obtain a fault feature vector.

And step 205, predicting the fault information of the circuit board based on the fault feature vector and a pre-trained fault prediction model.

After the execution main body obtains the fault feature vector, the fault information of the circuit board can be predicted by combining a pre-trained fault prediction model. The fault prediction model can be used for representing the corresponding relation between the characteristic vector and the fault information. In some specific implementations, the fault prediction model may be an Informer model. The reason why the Informer model is applied here is that it can refer to the results of the previous time in making the fault prediction at time t. The overall structure of the Informer model is divided into two parts, encoding and decoding. And in the encoding process, the encoder receives a long sequence input and obtains a characteristic representation through a ProbSparse self-attention module and a self-attention distillation module. In the decoding process, a decoder receives long sequence input, interacts with coding characteristics through multi-head attention, and finally directly predicts an output result. The ProbSparse self-attention module and the self-attention distillation module of Informer are capable of reducing computational complexity and reducing network parameters, respectively.

The execution subject may input the fault feature vector into the fault prediction model, and an output of the fault prediction model is fault information. In the fault prediction process, the model can obtain the output of the system according to the input result and compare the output with an expected value to generate a residual error. And when the generated residual error is smaller than a preset threshold value, no fault occurs. When the controlled object is abnormal, the residual error between the expected value and the actual output of the controlled object is larger than a preset threshold value, and then the fault is considered to occur.

The fault information may include a node where the fault is located, a type of the fault, characteristic information for proving the fault, a source of a fault signal, and the like. The node where the fault is located may be a test input node, a test output node, or a node between the test input node and the test output node. The type of fault may include a short circuit, an open circuit, etc. The characteristic information for proving the fault may include a signal output by the test output node, a certain parameter obtained by analyzing the output signal, and the like.

With continued reference to fig. 3, a schematic diagram of one application scenario of the circuit board fault detection method according to the present disclosure is shown. In the application scenario of fig. 3, the microscope 301 sends the acquired microscopic image of the circuit board to the terminal device 302, and the terminal device 302 determines a candidate fault area in the circuit board by using an image recognition model. Then, the test input node and the test output node are analyzed. After the test stimulus is input to the test input node, the output signal of the test output node can be analyzed to determine the fault feature vector. And finally, predicting the fault information of the circuit board by using a fault prediction model, and displaying the fault information for a user to check.

According to the circuit board fault detection method provided by the embodiment of the disclosure, the candidate fault area is determined by using the image recognition method, and then the fault test is performed on the candidate fault area in a focused manner, so that the intelligent fault detection can be performed on the circuit board, the diagnosis speed is high, and the result accuracy is high.

With continued reference to fig. 4, a flow 400 of another embodiment of a circuit board fault detection method according to the present disclosure is shown. As shown in fig. 4, the method of the present embodiment may include the following steps:

step 401, a microscopic image of the circuit board is acquired.

Step 402, determining candidate fault areas according to the microscopic images and the pre-trained image recognition model.

In some optional implementations of this embodiment, the image recognition model may be trained by the following training steps not shown in fig. 4: acquiring a training sample set; and taking the sample circuit board image in each training sample as input, taking a fault area corresponding to the input sample circuit board image as expected output, and training to obtain an image recognition model.

In this implementation, each training sample in the training sample set includes a sample circuit board image and a corresponding fault area. The execution subject may take the sample circuit board image in each training sample as input, take the fault region corresponding to the input sample circuit board image as expected output, and perform iterative optimization on the parameters of the model, so as to train to obtain the image recognition model.

The execution subject for training the image recognition model may be the same as or different from the execution subject of the present embodiment. If not, the executing agent for training the image recognition model may send the trained image recognition model to the executing agent of the present embodiment for use.

Step 403, scanning the candidate fault area, and acquiring an amplified image of the candidate fault area; and determining a test input node and a test output node according to the amplified image.

In this embodiment, after the candidate fault region is determined, in order to more accurately determine the diagnosable minimum unit, the candidate fault region may be scanned to acquire an enlarged image of the candidate fault region. Here, in order to facilitate acquisition of an enlarged image of the candidate trouble area, the execution subject may perform continuous scanning of the candidate trouble area to improve acquisition efficiency of the enlarged image. The smallest unit that can be diagnosed can be understood as the unit that diagnoses the fault with the fewest nodes. The unit may include a plurality of nodes and at least one element. It will be appreciated that the magnification of the magnified image is greater than the magnification of the microscopic image. This facilitates analysis of the wiring relationship of the electronic components of the candidate failure regions on the circuit board. And determining a test input node and a test output node according to the wiring relation. Specifically, the execution body may use each node as a test output node, and determine a test input node for each test output node. The execution body may use a node where the input signal and the output signal are more as a test input node. The nodes have a greater effect on the test output nodes, and by inputting test stimuli at these nodes, the problems of the circuit board can be reflected more accurately.

In some optional implementations of the present embodiment, the execution subject may determine the wiring of the electronic component of the candidate failure region from the enlarged image; and determining a test input node and a test output node according to the wiring.

In this implementation, the enlarged image may be subjected to image processing to identify the electronic components and the wiring in the circuit board, so that the wiring relationship between the electronic components can be determined. The execution body may use an output of the electronic component as a test output node, and use a node having a number of wires exceeding a preset value as a test input node.

In some optional implementations of the present embodiment, if no candidate fault region is detected in the microscopic image after the processing of step 402, the execution subject may take all nodes as test output nodes and then take nodes having a large influence on each test output node as test input nodes.

And step 404, performing wavelet transformation on each path of output signals of the test output node to determine a fault characteristic vector.

The fault information in the circuit board is often contained in singular points of the detected signal, and the wavelet transformation is a time-frequency analysis method and has the characteristic of multi-resolution analysis. With a higher frequency resolution and a lower time resolution in the low frequency part and a lower frequency resolution and a higher time resolution in the high frequency part.

Due to good localization or approximate localization property of wavelet transformation in time domain and frequency domain and the capability of signal self-adaptive zooming and multi-resolution analysis, the method can spread signals on different scales, extract the characteristics on different frequency bands, simultaneously retain the time-frequency characteristics of the signals on each scale, and is very suitable for detecting transient abnormal phenomena carried in normal signals and displaying the components of the transient abnormal phenomena. The wavelet transform transducer is used to decompose the mixed signals composed of different frequencies into block signals with different frequency components, so that the signal-noise separation and the feature extraction can be effectively carried out.

In this embodiment, the execution body may first sample the output signal of the test output node. Then, preprocessing the sampling data by applying wavelet analysis, and extracting fault characteristics. And selecting the low-frequency coefficient after wavelet decomposition as a characteristic value and giving the characteristic value a larger weight, and using the high-frequency coefficient as the characteristic value, but giving the weight smaller. When the circuit board is diagnosed, orthogonal wavelet packet decomposition is carried out on data of an output node selected in a circuit to obtain wavelet decomposition coefficient sequences, and energy of each coefficient sequence is combined into a feature vector.

Step 405, fusing the test input node, the test output node, the test excitation and the fault characteristic vector to obtain a fusion vector; and predicting the fault information of the circuit board according to the fusion vector and the fault prediction model.

The diagnostic information available in the circuit board fault diagnosis is more (the circuit board tests are more in types, such as voltage, current, admittance and the like), and although the fault diagnosis of the circuit can be completed by using a single test method, the diagnostic result is more and unreliable. In circuit board fault diagnosis, the diversity of devices and the complexity of circuits determine that the fault modes of the circuits are necessarily diverse. Moreover, in the circuit board fault diagnosis, the measurement information often has large variation due to the variation of the environment, the electromagnetic interference and the error of the measuring instrument, and the tolerance and the noise cannot be completely eliminated even if the data preprocessing is performed by using the wavelet decomposition. The information fusion fully utilizes each item of observable information, and because the characteristics of the obtained information are different, the shortage of single information is made up through reasonable domination and use of each item of information, so that each item of information can be complemented in time or space.

In this embodiment, the execution main body may perform uniform coding on information from different sources, map different feature vectors at the same time to the same space, and then perform feature merging. Namely, the signals output by each test output node are uniformly coded, mapped to the same space and then combined. In order to fully utilize the information in the test process, the execution main body can also uniformly encode the test input node, the test output node and the test excitation, and fuse the obtained information with the characteristics to obtain a fusion vector. And then, inputting the fusion vector into the fault prediction model to obtain fault information. The fault information may include the node where the fault is located, the type of fault, and the important feature vector and source of the fault signal that resulted in this prediction.

Optionally, in this embodiment, the fault prediction model may be obtained through training by the following steps: acquiring a second training sample set comprising a plurality of second training samples; and taking the sample fault feature vector in each second training sample as input, taking fault information corresponding to the input sample fault feature vector as expected output, and training to obtain a fault prediction model.

In this implementation manner, each second training sample in the second training sample set includes a sample fault feature vector and corresponding fault information. The execution subject may take the sample fault feature vector in each second training sample as an input, take fault information corresponding to the input sample fault feature vector as an expected output, and perform iterative optimization on the parameters of the model, thereby being able to train and obtain the fault prediction model.

It should be noted that the execution subject for training the failure prediction model may be the same as or different from the execution subject of the present embodiment. If not, the executing agent for training the fault prediction model may send the trained fault prediction model to the executing agent of the embodiment for use.

Step 406, recording the failure information.

In this embodiment, the execution may record the failure information for subsequent use.

Step 407, determining a solution for the fault information according to the fault information and a preset information base; based on the solution, a diagnostic report is generated.

In this embodiment, the execution main body may further query the fault information in a preset information base to determine a solution for the fault information. The information base may include fault information and corresponding solutions. The executive agent may generate a diagnostic report based on the solution described above. Specifically, the execution body may have a diagnosis report template built therein, and then fill the template with specific information according to a solution, and automatically generate a diagnosis report. It will be appreciated that the executive may also output diagnostic reports for viewing.

Step 408, receiving modification information for the diagnosis report, and storing the modified diagnosis report.

In this embodiment, the execution subject may also provide an interactive interface. Through the above-described interactive interface, the execution subject may receive user operations, such as confirmation, modification, and adjustment, for the diagnostic report. When the user modifies the diagnosis report, modification information is uploaded through the interactive interface. The modification information may be modified for the solution in the diagnosis report or modified for the fault information. The execution subject can store the modified diagnosis report in the information base, so that the information base can be updated and enriched.

In some optional implementation manners of this embodiment, the execution subject may further generate a new training sample by using the fault information generated in the fault process of the circuit board and the diagnosis report modified by the user, so as to train the fault prediction model again, so as to improve the accuracy of the fault prediction model.

According to the circuit board fault detection method provided by the embodiment of the disclosure, data of a test instrument can be fully utilized, and hidden problems in the data can be mined; the diagnosis report can be automatically formed and displayed on a manual interaction interface, so that a user can conveniently check and modify the diagnosis report; the data and the results of fault diagnosis can be kept, which is equivalent to the expert experience of fault diagnosis. For the same problem, the positioning can be fast.

With further reference to fig. 5, as an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a circuit board fault detection apparatus, which corresponds to the method embodiment shown in fig. 2, and which is particularly applicable to various electronic devices.

As shown in fig. 5, the circuit board fault detection apparatus 500 of the present embodiment includes: an image acquisition unit 501, an image recognition unit 502, a node determination unit 503, a signal analysis unit 504, and a failure prediction unit 505.

An image acquisition unit 501 configured to acquire a microscopic image of the circuit board.

An image recognition unit 502 configured to determine candidate fault regions according to the microscopic images and a pre-trained image recognition model. The image recognition model is used for representing the corresponding relation between the microscopic image and the fault area.

The node determination unit 503 is configured to determine a test input node and a test output node according to the candidate fault region.

A signal analysis unit 504 configured to analyze an output signal of the test output node to determine a fault signature vector in response to inputting a test stimulus to the test input node.

And a fault prediction unit 505 configured to predict fault information of the circuit board based on the fault feature vector and a pre-trained fault prediction model. The fault prediction model is used for representing the corresponding relation between the characteristic vector and the fault information.

In some optional implementations of this embodiment, the node determining unit 503 may be further configured to: scanning the candidate fault area, and acquiring an amplified image of the candidate fault area; and determining a test input node and a test output node according to the amplified image.

In some optional implementations of this embodiment, the node determining unit 503 may be further configured to: determining wiring of the electronic components of the candidate fault area according to the enlarged image; and determining a test input node and a test output node according to the wiring.

In some optional implementations of this embodiment, the signal analysis unit 504 may be further configured to: receiving a selected instruction of a test stimulus; the test stimulus indicated by the selected instruction is input to the test input node.

In some optional implementations of this embodiment, the signal analysis unit 504 may be further configured to: and performing wavelet transformation on each path of output signals of the test output node to determine a fault characteristic vector.

In some optional implementations of the present embodiment, the failure prediction unit 505 may be further configured to: fusing the test input node, the test output node, the test excitation and the fault characteristic vector to obtain a fused vector; and predicting the fault information of the circuit board according to the fusion vector and the fault prediction model.

In some optional implementations of this embodiment, the apparatus 500 may further include an information recording unit, not shown in fig. 5, configured to: and recording fault information.

In some optional implementations of this embodiment, the apparatus 500 may further include a report generating unit, not shown in fig. 5, configured to: determining a solution for the fault information according to the fault information and a preset information base; based on the solution, a diagnostic report is generated.

In some optional implementations of this embodiment, the apparatus 500 may further include a report modification unit, not shown in fig. 5, configured to: modification information for the diagnostic report is received, and the modified diagnostic report is stored.

In some optional implementations of this embodiment, the apparatus 500 may further include a model training unit, not shown in fig. 5, configured to obtain the image recognition model by the following training steps: acquiring a training sample set, wherein each training sample in the training sample set comprises a sample circuit board image and a corresponding fault area; and taking the sample circuit board image in each training sample as input, taking a fault area corresponding to the input sample circuit board image as expected output, and training to obtain an image recognition model.

It should be understood that units 501 to 505, which are described in the circuit board fault detection apparatus 500, respectively correspond to the respective steps in the method described with reference to fig. 2. Thus, the operations and features described above with respect to the circuit board fault detection method are equally applicable to the apparatus 500 and the units included therein and will not be described again here.

In the technical scheme of the disclosure, the acquisition, storage, application and the like of the personal information of the related user all accord with the regulations of related laws and regulations, and do not violate the good customs of the public order.

The present disclosure also provides an electronic device, a readable storage medium, and a computer program product according to an embodiment of the present disclosure.

Fig. 6 shows a block diagram of an electronic device 600 that performs a circuit board fault detection method according to an embodiment of the disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 6, the electronic device 600 includes a processor 601 that may perform various suitable actions and processes in accordance with a computer program stored in a Read Only Memory (ROM)602 or a computer program loaded from a memory 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data necessary for the operation of the electronic apparatus 600 can also be stored. The processor 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An I/O interface (input/output interface) 605 is also connected to the bus 604.

Various components in the electronic device 600 are connected to the I/O interface 605, including: an input unit 606 such as a keyboard, a mouse, or the like; an output unit 607 such as various types of displays, speakers, and the like; a memory 608, such as a magnetic disk, optical disk, or the like; and a communication unit 609 such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows the electronic device 600 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

Processor 601 may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples of processor 601 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. The processor 601 performs the various methods and processes described above, such as circuit board fault detection methods. For example, in some embodiments, the circuit board fault detection method may be implemented as a computer software program tangibly embodied in a machine-readable storage medium, such as memory 608. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 600 via the ROM 602 and/or the communication unit 609. When the computer program is loaded into RAM 603 and executed by processor 601, one or more steps of the circuit board fault detection method described above may be performed. Alternatively, in other embodiments, the processor 601 may be configured to perform the circuit board fault detection method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. The program code described above may be packaged as a computer program product. These program code or computer program products may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program code, when executed by the processor 601, causes the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable storage medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable storage medium may be a machine-readable signal storage medium or a machine-readable storage medium. A machine-readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The Server can be a cloud Server, also called a cloud computing Server or a cloud host, and is a host product in a cloud computing service system, so as to solve the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service ("Virtual Private Server", or simply "VPS"). The server may also be a server of a distributed system, or a server incorporating a blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel or sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions of the present disclosure can be achieved.

The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.