1. An erasure testing system, comprising: the system comprises a main control module, an FPGA module connected with the main control module and a chip to be tested connected with the FPGA module;

the main control module is used for sending an operation instruction and receiving the level signal sent by the FPGA module;

the FPGA module receives an operation instruction sent by the main control module and forwards the operation instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming or reading operation, the FPGA module compares the reading operation result and generates a level signal to be transmitted to the main control module, and the main control module judges whether erasing interference exists or not according to the level signal.

2. The system of claim 1, wherein the FPGA module includes at least a CTRL block and a SLOT block;

the CTRL unit analyzes the operation instruction and then transmits the operation instruction to the SLOT unit;

the SLOT unit receives the instruction analyzed by the CTRL unit and sends the instruction of the corresponding operation to the chip to be tested, so that the chip to be tested executes erasing operation or programming or reading operation, and the SLOT unit receives and registers result information of the chip to be tested executing the reading operation.

3. The system according to claim 1, further comprising a digital potentiometer module, wherein the digital potentiometer module receives an operation instruction from the main control module and supplies power to the FPGA module and the chip to be tested according to the operation instruction.

4. The system according to claim 3, further comprising an analog-to-digital conversion module, wherein the analog-to-digital conversion module collects voltage information of the FPGA module and the chip to be tested, and transmits the voltage information to the main control module through the FPGA module, and the main control module controls the digital potentiometer module to adjust the voltage according to the voltage information.

5. An erasure test method is used for an FPGA module to carry out erasure test, one end of the FPGA module is connected with a main control module, and the other end of the FPGA module is connected with a chip to be tested, and the erasure test method is characterized by comprising the following steps:

acquiring an operation instruction of a main control module to a chip to be tested;

analyzing the operation instruction and sending the analyzed instruction to the chip to be tested so that the chip to be tested executes an erasing operation or a programming operation or a reading operation;

and comparing the results of the reading operation to generate a level signal.

6. The method of claim 5, further comprising:

acquiring voltage information on the chip to be tested;

and sending the voltage information to the main control module to enable the main control module to adjust the voltage.

7. An erasure test method is used for an erasure test of a main control module, the main control module is connected with a chip to be tested through an FPGA module, and the erasure test method is characterized by comprising the following steps:

sending an operation instruction for the chip to be tested to the FPGA module, so that the FPGA module sends the analyzed operation instruction to the chip to be tested, and the chip to be tested executes an erasing operation or a programming operation or a reading operation;

acquiring a level signal generated by comparing the reading operation result of the FPGA module after the reading operation is executed by the chip to be tested;

and judging whether erasing interference exists according to the level signal.

8. The method of claim 7, further comprising:

acquiring voltage information of the FPGA module and the chip to be tested;

and adjusting the power supply of the FPGA module and the chip to be tested according to the voltage information.

9. An execution apparatus, comprising:

the first acquisition module is used for acquiring an operation instruction of the main control module to the chip to be tested;

the first processing module is used for analyzing the operation instruction and sending the analyzed instruction to the chip to be tested so that the chip to be tested can execute an erasing operation or a programming operation or a reading operation;

and the second processing module is used for comparing the results of the reading operation to generate a level signal.

10. An execution apparatus, comprising:

the third processing module is used for sending an operation instruction of the chip to be tested to the FPGA module, so that the FPGA module sends an operation related instruction to the chip to be tested, and the chip to be tested executes an erasing operation or a programming operation or a reading operation;

the second acquisition module is used for acquiring a level signal generated by comparing the reading operation result of the FPGA module after the reading operation is executed on the chip to be tested;

and the fourth processing module is used for judging whether erasing interference exists according to the level signal.

Background

Flash memory chips widely used in the market at present are composed of a floating gate structure (floating gate), electrons move in and out under the action of an electric field to correspond to programming (program) and erasing (erase) operations, respectively, the quantity of electrons stored in the floating gate can change the on voltage of a field effect, namely, the threshold voltage (Vth), which is a threshold voltage for distinguishing stored "0" from stored "1", above Vth identified as "0" for writing, and below Vth identified as "1" for erasing. For Nor flash, writing and erasing respectively correspond to hot electron injection and F-N tunneling principles, wherein programming operation is that a grid electrode and a drain electrode are respectively connected with 8.4V and 3.9V, a substrate and a source electrode are grounded, and erasing operation is that the substrate and the source electrode are both connected with 7-10V, and the grid electrode is connected with-9V.

In order to optimize the area of a flash memory chip with a floating gate structure prepared by a process below 65nm in the market, a plurality of memory matrixes are intensively placed and formed on a physical structure, each memory matrix is logically divided into a plurality of array blocks based on the floating gate technology, different array blocks are located on the same substrate, and when one array block in one physical memory array is subjected to erasing operation, the selected array block and the rest array blocks in the memory array are interfered by the voltage of a drain electrode because the drain electrode, the source electrode and the substrate are connected.

In conclusion, the strength of the erasure interference resistance is one of the important reference indexes for evaluating the quality of a flash chip, so that the accurate and efficient device and method for detecting the erasure interference of the flash chip become more important.

In a conventional scheme for testing whether there is erasure interference, a flash is directly tested by an MCU, if one erasure interference test is to be completed and a result is to be read, the MCU is required to perform an erasing-programming cyclic operation on one sector, and the MCU is required to perform a data reading operation in a gap of the erasing-programming cyclic operation on the other sector, namely erasing-reading-programming-reading, and then the result can be known after the data read back from the flash is compared in the MCU. The MCU can only operate one flash chip at a time, but with the wide application of the chips, the number of the chips increases suddenly, and the erasure test before flowing to the application market is an important evaluation method for the quality of the chips, so that the traditional inefficient test method is not suitable for large-scale application-level chip tests such as flash and the like. Moreover, the erase/write interference test of the flash chip performed by the conventional MCU is serial, for example, only after an erase/write command is sent to one sector, a read command can be sent to another sector to check whether erase/write interference is generated, or a read command is sent to one sector for multiple times and then a read command is sent to another sector to check whether erase/write interference is generated, and this test cannot simulate a scenario in which a client uses the flash chip, that is, a read operation is performed on one sector while an erase/write operation is performed on another sector.

In view of the above problems, improvements are needed.

Disclosure of Invention

The embodiment of the application aims to provide an erasure interference test system, an erasure interference test method and an erasure interference test execution device, and has the advantage of high test efficiency.

In a first aspect, an embodiment of the present application provides an erasure interference test system, which includes:

the method comprises the following steps: the system comprises a main control module, an FPGA module connected with the main control module and a chip to be tested connected with the FPGA module;

the main control module is used for sending an operation instruction and receiving the level signal sent by the FPGA module;

the FPGA module receives an operation instruction sent by the main control module and forwards the operation instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming or reading operation, the FPGA module compares the reading operation result and generates a level signal to be transmitted to the main control module, and the main control module judges whether erasing interference exists or not according to the level signal.

Further, in the embodiment of the present application, the FPGA module at least includes a CTRL unit and a SLOT unit;

the CTRL unit analyzes the operation instruction and then transmits the operation instruction to the SLOT unit;

the SLOT unit receives the instruction analyzed by the CTRL unit and sends the instruction of the corresponding operation to the chip to be tested, so that the chip to be tested executes erasing operation or programming or reading operation, and the SLOT unit receives and registers result information of the chip to be tested executing the reading operation.

Further, in this application embodiment, still include digital potentiometer module, digital potentiometer module receives the operating instruction that main control module sent, and give according to the operating instruction the FPGA module and the chip power supply that awaits measuring.

Further, in this application embodiment, still include the analog-to-digital conversion module, the analog-to-digital conversion module gathers the voltage information of FPGA module and the chip that awaits measuring, and will voltage information passes through the FPGA module transmits to host system, host system is according to voltage information control digital potentiometer module adjusts the voltage.

In a second aspect, the present application further provides an erasure interference testing method for performing an erasure interference test on an FPGA module, where one end of the FPGA module is connected to a main control module, and the other end of the FPGA module is connected to a chip to be tested, including:

acquiring an operation instruction of a main control module to a chip to be tested;

analyzing the operation instruction and sending the analyzed instruction to the chip to be tested so that the chip to be tested executes an erasing operation or a programming operation or a reading operation;

and comparing the results of the reading operation to generate a level signal.

Further, in the embodiment of the present application, the method further includes:

acquiring voltage information on the chip to be tested;

and sending the voltage information to the main control module to enable the main control module to adjust the voltage.

In a third aspect, the present application further provides another erasure test method for performing erasure test on a main control module, where the main control module is connected to a chip to be tested through an FPGA module, and the method includes:

sending an operation instruction for the chip to be tested to the FPGA module, so that the FPGA module sends the analyzed operation instruction to the chip to be tested, and the chip to be tested executes an erasing operation or a programming operation or a reading operation;

acquiring a level signal generated by comparing the reading operation result of the FPGA module after the reading operation is executed by the chip to be tested;

and judging whether erasing interference exists according to the level signal.

Further, in the embodiment of the present application, the method further includes:

acquiring voltage information of the FPGA module and the chip to be tested;

and adjusting the power supply of the FPGA module and the chip to be tested according to the voltage information.

In a fourth aspect, the present application further provides an executing apparatus, including:

the first acquisition module is used for acquiring an operation instruction of the main control module to the chip to be tested;

the first processing module is used for analyzing the operation instruction and sending the analyzed instruction to the chip to be tested so that the chip to be tested can execute an erasing operation or a programming operation or a reading operation;

and the second processing module is used for comparing the results of the reading operation to generate a level signal.

In a fifth aspect, an execution apparatus is provided, including:

the third processing module is used for sending an operation instruction of the chip to be tested to the FPGA module, so that the FPGA module sends an operation related instruction to the chip to be tested, and the chip to be tested executes an erasing operation or a programming operation or a reading operation;

the second acquisition module is used for acquiring a level signal generated by comparing the reading operation result of the FPGA module after the reading operation is executed on the chip to be tested;

and the fourth processing module is used for judging whether erasing interference exists according to the level signal.

As can be seen from the above, the erasure interference test system, the method and the execution device provided in the embodiments of the present application can simultaneously test a large number of chips to be tested by setting the FPGA module, and compared with the conventional method in which a single MCU correspondingly tests one chip to be tested, the efficiency is significantly improved, meanwhile, after sending a read operation command to the chip to be tested, the chip to be tested performs a read operation, the read result can be compared in the FPGA module, and then a high level or a low level is generated according to the comparison result, if the read level is a high level, it means that the comparison is inconsistent, it means that the erasure interference occurs, if the read level is a low level, it means that the erasure interference does not occur, and by this setting, the main control module does not need to generate a read action, but only needs to generate a read action after the high level occurs, and the situation of occurrence of erasing and writing interference is relatively less, so that the main control module does not need to perform frequent reading action, and the scheme of the application has the beneficial effect of high test efficiency compared with the prior art.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Fig. 1 is a schematic diagram of an erasure test system according to an embodiment of the present application.

Fig. 2 is a flowchart of an erasure test method according to an embodiment of the present application.

FIG. 3 is a flowchart of an Erase test method according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an execution device according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of an execution device according to an embodiment of the present disclosure.

In the figure: 100. a main control module; 200. an FPGA module; 300. a digital potentiometer module; 400. an analog-to-digital conversion module; 210. a CTRL unit; 220. a SLOT unit; 510. a first acquisition module; 520. a first processing module; 530. a second processing module; 610. a third processing module; 620. a second acquisition module; 630. and a fourth processing module.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1 to 5, an erasure test system includes:

the main control module 100, the main control module 100 is used for sending an operation instruction; the main control module 100 may be an MCU.

The FPGA module 200 receives the operation instruction sent by the main control module 100 and forwards the operation instruction to the chip to be tested connected to the FPGA module 200, so that the chip to be tested executes an erasing operation or a programming operation or a reading operation, the FPGA module 200 compares the reading operation result and generates a level signal to be transmitted to the main control module 100, and whether erasing interference exists or not is judged according to the level signal. The FPGA module 200 may refer to an FPGA chip, the chip to be tested may refer to a flash chip, or may refer to other chips that need to be tested, and an error _ flag pin is provided on the FPGA module 200 and connected to the main control module, so as to transmit a level signal.

Through the technical scheme, a large number of chips to be tested can be tested simultaneously by setting the FPGA module 200, specifically, 28 chips to be tested can be tested simultaneously in some embodiments, the number of tests is influenced by factors such as pins, logic resources and speed of a development board of the FPGA module 200, compared with the traditional method that a single MCU correspondingly tests one chip to be tested, the efficiency is obviously improved, meanwhile, after a reading operation instruction is sent to the chip to be tested, the chip to be tested executes reading operation, the result of the reading operation can be compared in the FPGA module 200, a comparator or a comparison circuit can be arranged in the FPGA module 200, reading data can be preset in the FPGA module 200, the reading result of the chip to be tested after the reading operation is executed is compared with the preset reading data, then high level or low level is generated according to the comparison result, if the reading result is high level, the comparison is inconsistent, the situation of erasure interference occurs, if the comparison is consistent if the level is low, the situation of erasure interference does not occur, and through the setting mode, the main control module 100 does not need to generate extra reading actions, only an instruction for reading a reading result of the chip to be tested needs to be generated after the level is high, and the situation of erasure interference is relatively less, so that the main control module 100 does not need to perform frequent reading actions, the load of the main control module 100 can be greatly reduced, and the overall testing efficiency is improved.

Moreover, by adopting the technical scheme of the application, the parallel execution characteristics of the FPGA module 200 can be utilized, and one sector can be erased and written while the other sector is read.

Further, in still other embodiments, the FPGA module 200 includes at least a CTRL unit 210 and a SLOT unit 220;

the CTRL unit 210 parses the operation command and transmits the operation command to the SLOT unit 220;

the SLOT unit 220 receives the command analyzed by the CTRL unit 210 and sends a command corresponding to the operation to the chip to be tested, so that the chip to be tested performs an erase operation or performs a program operation or performs a read operation, and the SLOT unit 220 receives and registers result information of the chip to be tested performing the read operation.

The CTRL unit 210 communicates with the main control module 100 through an SPI interface protocol, and the CTRL unit 210 communicates with the SLOT unit 220 through an APB bus and a common direct line.

The plurality of SLOT units 220 are provided, and each SLOT unit 220 is connected with one chip to be tested through the SPI.

Through the above technical solution, the CTRL unit 210 is mainly responsible for parsing and registering an operation instruction sent by the main control module 100 based on the SPI protocol, and sending a corresponding operation instruction registered in the register to the SLOT unit 220 through the APB bus and the normal direct line, and in addition, the CTRL unit 210 may also set a start indication bit register CTRL _ FLASH _ en inside the SLOT unit 220 through the APB bus, thereby starting CTRL _ FLASH operation.

The SLOT unit 220 obtains a corresponding instruction for operating the chip to be tested through a direct connection with a register in the CTRL unit 210, and after setting the instruction bit register CTRL _ flash _ en through an internal state machine, sends the instruction for operating the chip to be tested to the chip to be tested through the SPI, if the instruction for causing the chip to be tested to perform a reading operation is sent, the SLOT unit 220 also receives and registers a reading result output by the chip to be tested in the corresponding register, and when the reading result in the register is sent by the main control module 100 as the instruction for reading the reading result of the chip to be tested, the reading result is read to the CTRL unit 210 through the APB bus, and information read by the APB bus is sent to the SPI interface of the main control module 100 through a handshake protocol.

The APB bus is used as a communication bridge between the CTRL unit 210 and the SLOT unit 220, and is mainly responsible for transmitting the read result of the to-be-tested chip registered by the SLOT unit 220 to the CTRL unit 210 in addition to the enable signal for setting the to-be-tested chip, and the read rate can reach 4 bytes per time.

Further, in some embodiments, the digital potentiometer module 300 is further included, and the digital potentiometer module 300 receives an operation instruction sent by the main control module 100, and supplies power to the FPGA module 200 and the chip to be tested according to the operation instruction.

The digital potentiometer module 300 communicates with the main control module 100 through an SPI interface protocol, and the digital potentiometer module 300 may refer to a digital potentiometer, and in some embodiments, a digital potentiometer AD5160 may be used.

Through the above technical solution, the digital potentiometer module 300 supplies power to the FPGA module 200 and the chip to be tested under the control of the main control module 100, the digital potentiometer module 300 functions as a rheostat, changes a resistance value according to input configuration information, and finally outputs different voltages, because the voltages of the chip to be tested for performing an erasing operation, a programming operation, and a reading operation are different when the chip to be tested is tested, so that different voltages are required, and the corresponding power supply configuration information is mainly received in an operation instruction sent by the main control module 100 based on an SPI protocol.

Further, in some embodiments, the digital potentiometer module 300 further includes an analog-to-digital conversion module 400, where the analog-to-digital conversion module 400 collects voltage information of the FPGA module 200 and the chip to be tested, and transmits the voltage information to the main control module 100 through the FPGA module 200, and the main control module 100 controls the digital potentiometer module 300 to adjust the voltage according to the voltage information.

The analog-to-digital conversion module 400 communicates with the FPGA module 200 through the SPI protocol, and the analog-to-digital conversion module 400 may refer to an analog-to-digital conversion chip, and in some embodiments, the analog-to-digital conversion chip ADC108s may be used.

Through the above technical solution, the analog-to-digital conversion module 400 is configured to monitor the voltage output by the digital potentiometer module 300 to the SLOT unit 220 of the FPGA module 200 for mounting the chip to be tested, then return the voltage to the main control module 100, and adjust the voltage through the digital potentiometer module 300 according to the returned result until the voltage reaches the predetermined voltage range.

It should be noted that, in the scheme of the present application, when the chip to be tested is tested, a cyclic erase-program-erase-program operation is also performed on one sector in the chip to be tested, and then a read operation is performed on the other sector, and the read operation is between the erase operation and the program operation, that is, during the test, the chip to be tested needs to perform the erase-read-program-read-erase operation.

In a second aspect, the present application further provides an erasure test method for performing an erasure test on the FPGA module 200, where one end of the FPGA module 200 is connected to the main control module 100, and the other end is connected to a chip to be tested, including:

s1, acquiring an operation instruction of the main control module 100 to the chip to be tested; the main control module 100 may be an MCU.

S2, analyzing the operation instruction and sending the analyzed instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation;

s3, comparing the results of the reading operation to generate a level signal;

according to the technical scheme, firstly, an operation instruction for the chip to be tested is obtained, the operation instruction comprises an instruction for enabling the chip to be tested to execute erasing operation, an instruction for executing programming operation and an instruction for executing reading operation, then the operation instruction is analyzed and forwarded to the chip to be tested, the chip to be tested is enabled to execute erasing operation or execute programming operation or execute reading operation, after the chip to be tested executes reading operation, reading results are compared, high-level signals or low-level signals are generated according to the comparison result, the high-level signals mean that the comparison result is inconsistent, the low-level signals mean that the comparison result is consistent, and whether erasing interference exists in the chip to be tested can be judged according to the level signals.

Compared with the traditional method for testing one chip by one MCU, the testing method can greatly reduce the load of the MCU, the main control module 100 can know whether erasing interference exists only according to the level signal, the MCU in the existing scheme is not required to read the reading result of the chip to be tested every time, and the overall testing efficiency is effectively improved.

Further, in some embodiments, the method further comprises:

if the erasure interference occurs, receiving an operation instruction of the main control module 100;

and according to the operation instruction of the main control module 100, the read result output by the chip to be tested is registered in the corresponding register and is sent to the main control module 100.

Through the technical scheme, compared with the existing scheme that the MCU needs to read the reading result of the chip to be tested at each time and then compares the reading result with the data on the original reading sector of the chip to be tested, the scheme of the embodiment only needs to send the operation instruction for reading the reading result of the chip to be tested when the high level occurs, and the probability of occurrence of erasing interference is relatively low, so that the main control module 100 does not need to perform the operation in most of time, the burden of the main control module 100 is greatly reduced, and the overall testing efficiency is effectively improved.

Further, in some embodiments, the method further comprises:

acquiring voltage information on a chip to be tested;

the voltage information is sent to the main control module 100, so that the main control module 100 adjusts the voltage.

According to the technical scheme, since the chip to be tested needs to perform the erasing operation, the programming operation and the reading operation, and the operations correspond to different working voltages respectively, the voltage information on the chip to be tested needs to be monitored, the monitored voltage information is sent to the main control module 100, and the main control module 100 correspondingly adjusts the voltage applied to the chip to be tested according to the operation instruction sent to the chip to be tested, so that the chip to be tested can normally perform the operation according to the operation instruction. In addition, whether the chip to be tested is in a normal working state or not can be judged by monitoring the voltage on the chip to be tested.

Specifically, in some embodiments, the voltage information on the chip to be tested is obtained through the analog-to-digital converter, the main control module 100 generates an operation instruction after receiving the voltage information, and then sends the generated operation instruction to the digital potentiometer, so that the digital potentiometer outputs different voltage values to supply power to the chip to be tested.

Further, in some embodiments, the step of comparing the results of the read operations to generate a level signal comprises:

presetting contrast data which is the same as a reading sector of a chip to be tested;

comparing the comparison data with the read result;

and generating a level signal according to the comparison result.

Through the technical scheme, the comparison result is compared with the preset comparison data, wherein the data which is the same as the comparison data needs to be written in the chip to be tested in advance, the written data is fixedly read when the chip to be tested executes the reading operation, if the comparison result is the same, a low level signal is generated, and if the comparison result is different, a high level signal is generated.

Specifically, in some embodiments, data that is the same as the comparison data is written in a first sector on a chip to be tested, the main control module 100 sends an erase operation instruction, the chip to be tested performs an erase operation in a second sector, the main control module 100 sends a program operation instruction, the chip to be tested performs a program operation in the second sector, the main control module 100 sends a read operation instruction, the chip to be tested performs a read operation in the first sector, then the read result is compared with the comparison data, if the comparison results are the same, it is indicated that no erase interference occurs, a low level is generated, and if the comparison results are different, it is indicated that the erase interference occurs, and a high level is generated.

Further, in some other embodiments, the step of comparing the results of the read operation to generate a level signal comprises:

storing programming data when the chip to be tested executes programming operation as comparison data;

comparing the comparison data with the read result;

and generating a level signal according to the comparison result.

Through the technical scheme, when the chip to be tested is controlled to execute the programming operation, the chip to be tested needs to program specified data in the sectors, the data is programming data, such as 010, and when the chip to be tested circularly executes the programming operation, the programming data is the same, so the programming data can be stored as comparison data, when the chip to be tested executes the first round of programming operation, the same programming data can be simultaneously programmed in two sectors, wherein one sector is used as the sector when the reading operation is executed, so that the data can be not written in advance for comparison, the test can be directly carried out on any two sectors of the chip to be tested, and then the level signal is generated according to the comparison result.

Specifically, in some embodiments, when a chip to be tested performs a programming operation, the same data is programmed into a second sector of a first sector, the programmed data is stored as comparison data, the main control module 100 sends an erasing operation instruction, the chip to be tested performs an erasing operation on the first sector, the main control module 100 sends a second and subsequent programming operation instructions, the chip to be tested performs a programming operation on the first sector, the main control module 100 sends a reading operation instruction, the chip to be tested performs a reading operation on the second sector, the reading result is compared with the comparison data, if the comparison results are the same, it is indicated that no erasing interference occurs, a low level is generated, and if the comparison results are different, it is indicated that the erasing interference occurs, and a high level is generated.

In a third aspect, the present application further provides another erasure interference testing method for performing erasure interference testing on the main control module 100, where the main control module 100 is connected to a chip to be tested through the FPGA module 200, including:

s10, sending an operation instruction of the chip to be tested to the FPGA module 200, so that the FPGA module 200 sends the analyzed operation instruction to the chip to be tested, and further the chip to be tested executes an erasing operation or a programming operation or a reading operation; the FPGA module 200 may refer to an FPGA chip.

S20, obtaining a level signal generated by comparing the reading operation result of the FPGA module 200 after the chip to be tested executes the reading operation;

s30, judging whether there is erasing interference according to the level signal.

Through the technical scheme, an operation instruction of the chip to be tested is sent to the FPGA module 200, the operation instruction comprises an instruction for enabling the chip to be tested to execute an erasing operation, an instruction for executing a programming operation and an instruction for executing a reading operation, the FPGA module 200 analyzes the instructions, then forwards the analyzed instructions to the chip to be tested, and enables the chip to be tested to execute the erasing operation or the programming operation or the reading operation, after the chip to be tested executes the reading operation, the FPGA module 200 registers the reading result, compares the reading result, generates a level signal according to the comparison result, then acquires the level signal and can judge whether the chip to be tested has the erasing interference or not according to the level of the level signal, if the level signal is high level, the comparison result is inconsistent, namely the erasing interference is generated, if the level signal is low level, the comparison result is consistent, i.e. no erasure interference occurs.

Compared with the means of testing a chip by using an MCU in the existing scheme, the testing method can know whether the erasing interference exists or not only according to the level signal, and does not need to read the reading result of the chip to be tested every time like the MCU in the existing scheme, and then compares the reading result to judge whether the erasing interference occurs or not, so that the overall testing efficiency is effectively improved by using the scheme of the application.

Further, in some embodiments, the method further comprises:

acquiring voltage information of the FPGA module 200 and a chip to be tested;

and adjusting the power supply of the FPGA module 200 and the chip to be tested according to the voltage information.

According to the technical scheme, since the chip to be tested needs to perform the erasing operation, the programming operation and the reading operation, and the operations correspond to different working voltages respectively, the voltage information on the chip to be tested needs to be monitored, the monitored voltage information is sent to the main control module 100, and the main control module 100 correspondingly adjusts the voltage applied to the chip to be tested according to the operation instruction sent to the chip to be tested, so that the chip to be tested can normally perform the operation according to the operation instruction. In addition, whether the chip to be tested is in a normal working state or not can be judged by monitoring the voltage on the chip to be tested.

Specifically, in some embodiments, the voltage information on the chip to be tested is obtained through the analog-to-digital converter, the main control module 100 generates an operation instruction after receiving the voltage information, and then sends the generated operation instruction to the digital potentiometer, so that the digital potentiometer outputs different voltage values to supply power to the chip to be tested.

Specifically, in some embodiments of the present application, components and parts mainly related to the scheme provided by the present application include: MCU, FPGA chip, digital potentiometer, analog-to-digital conversion chip and the chip that awaits measuring.

In this embodiment, the MCU serves as the main control module 100 and communicates with the FPGA chip and the digital potentiometer on the development board through the SPI protocol. The MCU firstly sends an operation instruction to the FPGA chip for the operation of the chip to be tested, and the operation instruction is analyzed and registered by the FPGA chip and then forwarded to the chip to be tested through an internal state machine to execute corresponding operations, such as executing an erasing operation, executing a programming operation and executing a reading operation.

In this embodiment, the FPGA chip is mainly divided into two units as a communication link between the MCU and the chip to be tested: CTRL unit 210 and SLOT unit 220. The CTRL unit 210 is mainly responsible for analyzing and registering operation information that the MCU transmits based on the SPI protocol, and transmitting configuration information to the analog-to-digital conversion chip through the SPI protocol, and transmitting a corresponding operation instruction registered in the register to the SLOT unit 220 through the APB bus and the common direct line, respectively. The SLOT unit 220 is set by the CTRL unit 210 through the APB bus with a start indication bit register CTRL _ FLASH _ en therein, thereby starting CTRL _ FLASH operation, acquiring a corresponding instruction for operating the chip to be tested through a direct line with a register in the CTRL unit 210, and after the indication bit register CTRL _ FLASH _ en is set through an internal state machine, transmitting the instruction to the chip to be tested through the SPI, if the instruction for causing the chip to be tested to execute the read operation is transmitted, receiving and registering data of the read result output by the chip to be tested in the corresponding register, where the data in the registers will be read by the APB bus to the CTRL unit 210 when the MCU transmits the instruction for reading the read result of the chip to be tested, and transmitting the information read by the APB bus to the SPI interface of the MCU terminal through a handshake protocol.

In the embodiment, the APB bus, which is a communication bridge between the CTRL unit 210 and the SLOT unit 220, is mainly responsible for transmitting the result of the read result output by the chip under test registered by the SLOT unit 220 to the CTRL unit 210, in addition to the enable signal for setting the chip under test, with a read rate of 4 bytes per time.

In this embodiment, the digital potentiometer is mainly responsible for supplying power to the FPGA chip and the chip to be tested on the development board under the control of the MCU, and has a function equivalent to a rheostat, so as to change a resistance value according to input configuration information and finally output different voltage values, and the corresponding power supply configuration information is mainly received by the MCU based on the SPI protocol.

In this embodiment, the analog-to-digital conversion chip is mainly responsible for acquiring the Bank voltages of the chip to be tested and the FPGA chip, and outputs a corresponding numerical value after receiving the address information sent by the CTRL unit 210 through the SPI protocol by converting the voltages into digital information, the numerical value FPGA chip is sent to the SPI interface of the MCU through the handshake protocol, and the numerical value can obtain a specific voltage value through formula conversion. The MCU can further operate the digital potentiometer according to the analog-to-digital conversion chip to supply power to the FPGA chip on the development board and the chip to be detected, so that the FPGA chip on the development board and the chip to be detected are accurately regulated to a voltage to be set through the analog-to-digital conversion chip and the digital potentiometer.

In this embodiment, all communications between the MCU and the chip to be tested are based on: the MCU sends an instruction to the FPGA chip, the instruction is forwarded to the chip to be tested through the FPGA chip, and data output by the chip to be tested is also forwarded by the FPGA chip and transmitted to the MCU.

Specifically, the MCU sends an erase or program command first, after all program operations are performed after the erase operation, a read command is sent to another sector to confirm whether the last erase/program operation interferes with other areas of the memory array block, if it reads that the original "0" is changed into "1", it indicates that interference occurs, if no bit changes, it indicates that the erase/program operation does not affect the read sector, if it is interfered, a high level is generated, and thus if it further wants to know more interfered information, the MCU sends a command to the FPGA chip to read the read result of the chip to be tested, and if the generated level signal is always at a low level, the MCU knows that no interference occurs.

As is obvious from the above explanation, the MCU determines whether erasure interference occurs and does not need to send the erasure interference to the FPGA chip, and only when more interference information is desired, the MCU sends the instruction for reading the reading result of the chip to be tested to the FPGA chip again.

The testing method provided in the embodiment includes that level signals are generated by comparing in the FPGA chip, specifically, the level signals generated in the FPGA chip are connected to the pin of the error _ flag interacting between the MCU and the FPGA chip, and the MCU can know whether erasure interference occurs without sending an operation instruction, so that the task load of the MCU is greatly reduced, and finally, the information whether the erasure interference occurs to the chip to be tested is efficiently obtained.

In a fourth aspect, the present application further provides an executing apparatus, including:

a first obtaining module 510, configured to obtain an operation instruction of the main control module 100 on the chip to be tested;

the first processing module 520 is configured to analyze the operation instruction and send the analyzed instruction to the chip to be tested, so that the chip to be tested performs an erase operation or a program operation or a read operation;

a second processing module 530, configured to compare results of the read operation to generate a level signal;

through the above technical solution, the first obtaining module 510 first obtains an operation instruction for a chip to be tested, where the operation instruction includes an instruction for the chip to be tested to perform an erase operation, an instruction for performing a programming operation, and an instruction for performing a read operation, and then the first processing module 520 parses the operation instruction and forwards the operation instruction to the chip to be tested, so that the chip to be tested performs the erase operation or performs the programming operation or performs the read operation.

Compared with the traditional method for testing a chip by using the MCU, the method can greatly reduce the load of the MCU, the main control module 100 can know whether erasing interference exists only according to the level of the level signal, the MCU in the existing scheme is not required to read the reading result of the chip to be tested at each time, and the overall testing efficiency is effectively improved.

In a fifth aspect, an execution apparatus is provided, including:

the third processing module 610 is configured to send an operation instruction for the chip to be tested to the FPGA module 200, so that the FPGA module 200 sends an operation related instruction to the chip to be tested, and further the chip to be tested performs an erasing operation or a programming operation or a reading operation;

the second obtaining module 620 is configured to obtain a level signal generated by comparing the reading operation result after the FPGA module 200 performs the reading operation on the chip to be tested;

the fourth processing module 630 is configured to determine whether there is erasure interference according to the level signal.

Through the technical scheme, the third processing module 610 sends an operation instruction for the chip to be tested to the FPGA module 200, the operation instruction includes an instruction for the chip to be tested to perform an erasing operation, an instruction for performing a programming operation, and an instruction for performing a reading operation, the FPGA module 200 parses the instructions, then forwards the parsed instructions to the chip to be tested, so that the chip to be tested performs the erasing operation or the programming operation or the reading operation, after the chip to be tested performs the reading operation, the FPGA module 200 registers the reading result, compares the reading result, generates a level signal according to the comparison result, then the second obtaining module 620 obtains the level signal, the fifth processing module 630 can judge whether the chip to be tested has the erasing interference condition according to the level signal, if the level signal is high level, the comparison result is inconsistent, that is, the occurrence of the erasure is confirmed, and if the level is low, the comparison result is consistent, that is, the occurrence of the erasure is not confirmed.

Compared with the means of testing a chip by using an MCU in the existing scheme, the testing method can know whether the erasing interference exists or not only according to the level signal, and does not need to read the reading result of the chip to be tested every time like the MCU in the existing scheme, and then compares the reading result to judge whether the erasing interference occurs or not, so that the overall testing efficiency is effectively improved by using the scheme of the application.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.