1. A method for suppressing over-erasure of a Flash memory, which is used for suppressing over-erasure of a memory cell in Nor Flash, the method comprising: when reading or verifying data operation is carried out on a selected memory cell with an over-erasing problem in a chip, negative voltage is applied to a Bulk end of the selected memory cell and/or negative voltage is applied to a word line end of an unselected memory cell on the same bit line and/or positive voltage is applied to a source end of the selected memory cell.

2. The method of claim 1, wherein the negative pressure applied to the Bulk terminal of the selected memory cell is-0.75 to-0.25V.

3. The method of claim 1, wherein the negative voltage applied to the word line terminals of the unselected memory cells on the same bit line is-0.75V to-0.25V.

4. The method of claim 1, wherein the positive voltage applied to the source of the selected memory cell is 0.25-0.75V.

5. The method of claim 1, wherein when a negative voltage is applied to the Bulk terminal of the selected memory cell, a negative voltage is applied to the word line terminal of the unselected memory cell on the same bit line, and a positive voltage is applied to the source terminal of the selected memory cell, the magnitude of the voltage of the negative voltage applied to the Bulk terminal of the selected memory cell is equal to the magnitude of the voltage of the negative voltage applied to the word line terminal of the unselected memory cell on the same bit line, and the absolute value of the voltage of the negative voltage applied to the word line terminal of the unselected memory cell on the same bit line is equal to the absolute value of the voltage of the positive voltage applied to the source terminal of the selected memory cell.

6. The method of claim 1, wherein the gate trigger voltage of the memory cell with over-erase problem is lower than or equal to 0V after applying negative voltage to the Bulk terminal of the selected memory cell and/or applying negative voltage to the word line terminal of the unselected memory cells on the same bit line and/or applying positive voltage to the source terminal of the selected memory cell.

7. An apparatus for suppressing over-erase of a Flash memory, wherein the apparatus is used for suppressing over-erase of a memory cell in Nor Flash, and comprises:

the acquisition module is used for reading or verifying data of the storage unit in the chip;

the voltage operation module is used for applying voltage to a storage unit terminal line in the chip;

the voltage operation module can apply negative voltage to the Bulk end of the selected memory cell and/or apply negative voltage to the word line end of unselected memory cells on the same bit line and/or apply positive voltage to the source end of the selected memory cell when the acquisition module performs reading or verifying data operation on the selected memory cell with the over-erasure problem in the chip.

8. The apparatus according to claim 7, wherein the voltage operation module comprises a first voltage module, a second voltage module, and a third voltage module, and when the obtaining module performs a read or verify data operation on a selected memory cell in the chip, which has an over-erase problem, the first voltage module, the second voltage module, and the third voltage module simultaneously apply a negative voltage to a Bulk terminal of the selected memory cell, a negative voltage to a word line terminal of an unselected memory cell on the same bit line, and a positive voltage to a source terminal of the selected memory cell, respectively.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-6.

10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-6.

Background

When the Nor flash performs an erase operation, due to inconsistent erase difficulty of the memory cells, some memory cells are still erased after the erase operation is completed, so that an over-erase phenomenon is caused, the threshold voltage of the over-erased memory cells is particularly low, and in the process of reading data of the memory cells, several cells have leakage under a non-selection gate voltage (usually 0V), so that the problem that correct data cannot be read on a word line is caused, and particularly, after multiple erase cycles, the uncertainty of the threshold voltage is increased.

Therefore, in order to save these over-erased memory cells, in the conventional nor flash, in order to compromise the performance and reliability of the erase operation, over-erase checking and repairing processes are generally added at the end stage of the erase operation, which results in a complicated algorithm flow of the erase operation, and also sacrifices a part of data retention capability.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method, an apparatus, an electronic device, and a storage medium for suppressing over-erasure of a flash memory, so as to suppress a leakage behavior of an over-erased memory cell during a reading process, and further enable the erased memory cell to be normally used without repair.

In a first aspect, an embodiment of the present application provides a method for suppressing over-erase of a Flash memory, which is used for suppressing an over-erase phenomenon of a memory cell in Nor Flash, and the method includes: when reading or verifying data operation is carried out on a selected memory cell with an over-erasing problem in a chip, negative voltage is applied to a Bulk end of the selected memory cell and/or negative voltage is applied to a word line end of an unselected memory cell on the same bit line and/or positive voltage is applied to a source end of the selected memory cell.

The method for inhibiting the over-erasing of the flash memory is characterized in that the negative pressure applied to the Bulk end of the selected memory cell is-0.75 to-0.25V.

The method for inhibiting the over-erasing of the flash memory is characterized in that the negative pressure applied to the word line end of the unselected memory unit on the same bit line is-0.75 to-0.25V.

The method for inhibiting the flash memory from being over-erased is characterized in that positive voltage applied to the source end of the selected memory cell is 0.25-0.75V.

When negative voltage is applied to the Bulk end of a selected memory cell, negative voltage is applied to the word line end of an unselected memory cell on the same bit line, and positive voltage is applied to the source end of the selected memory cell at the same time, the voltage value of the negative voltage applied to the Bulk end of the selected memory cell is equal to the voltage value of the negative voltage applied to the word line end of the unselected memory cell on the same bit line, and the absolute voltage value of the negative voltage applied to the word line end of the unselected memory cell on the same bit line is equal to the absolute voltage value of the positive voltage applied to the source end of the selected memory cell.

After negative voltage is applied to the Bulk end of the selected memory cell and/or negative voltage is applied to the word line end of unselected memory cells on the same bit line and/or positive voltage is applied to the source end of the selected memory cell, the gate trigger voltage of the memory cell with the over-erase problem is lower than or equal to 0V.

In a second aspect, an embodiment of the present application further provides an apparatus for suppressing over-erase of a Flash memory, for suppressing an over-erase phenomenon of a memory cell in Nor Flash, including:

the acquisition module is used for reading or verifying data of the storage unit in the chip;

the voltage operation module is used for applying voltage to a storage unit terminal line in the chip;

the voltage operation module can apply negative voltage to the Bulk end of the selected memory cell and/or apply negative voltage to the word line end of unselected memory cells on the same bit line and/or apply positive voltage to the source end of the selected memory cell when the acquisition module performs reading or verifying data operation on the selected memory cell with the over-erasure problem in the chip.

When the acquisition module performs reading or data verification operation on a selected memory cell with an over-erasure problem in a chip, the first voltage module, the second voltage module and the third voltage module simultaneously and respectively apply negative voltage to a Bulk end of the selected memory cell, apply negative voltage to a word line end of an unselected memory cell on the same bit line and apply positive voltage to a source end of the selected memory cell.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.

In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program runs the steps in the method provided in the first aspect when executed by a processor.

As can be seen from the above, the method, the device, the electronic device, and the storage medium for suppressing the over-erase of the flash memory provided in the embodiments of the present application provide three basic processing manners, namely "applying a negative voltage to the Bulk terminal of a selected memory cell, applying a negative voltage to the word line terminal of an unselected memory cell on the same bit line, and applying a positive voltage to the source terminal of the selected memory cell", to suppress the leakage behavior of the over-erased memory cell during data read/verify, so that the erased memory cell can be normally used without repair, and the three basic processing manners can be used independently or in any combination, and have a diversity characteristic.

Drawings

Fig. 1 is a schematic usage diagram of some embodiments of a method for suppressing over-erase of a flash memory according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of some embodiments of an apparatus for suppressing over-erase of a flash memory according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of some embodiments of an electronic device according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, in a first aspect, fig. 1 is a method for suppressing over-erase of a Flash memory in some embodiments of the present application, for suppressing over-erase of a memory cell in Nor Flash, the method including: when reading or verifying data operation is carried out on a selected memory cell with an over-erasing problem in a chip, negative voltage is applied to a Bulk end of the selected memory cell and/or negative voltage is applied to a word line end of an unselected memory cell on the same bit line and/or positive voltage is applied to a source end of the selected memory cell.

The reason why the over-erased memory cell cannot hold data is that the threshold voltage is too low, so that the gate trigger voltage Vgt is greater than 0, and thus leakage occurs during a data reading or verifying operation, thereby causing a data reading error.

Specifically, a negative voltage is applied to the Bulk terminal of the selected memory cell, and due to a back-gate effect (the effect of the change in the threshold voltage Vt caused by the substrate voltage, i.e., the Bulk voltage, not being 0 is called a back gate effect), the threshold voltage Vt of the memory cell is about to be increased by a voltage value corresponding to half of the absolute value of the negative voltage value, and if the negative voltage applied to the Bulk terminal is-1V, the threshold voltage Vt of the corresponding memory cell is about to be increased by 0.5V due to the back gate effect; on the basis, as the threshold voltage rises, the corresponding gate trigger voltage Vgt can drop by a corresponding magnitude, negative voltage is applied to the Bulk end by the over-erased storage unit, so that the threshold voltage Vt rises and the gate trigger voltage Vgt drops, when the gate trigger voltage Vgt drops to be lower than 0V, the problem of electric leakage of the storage unit can not be caused when data reading or verifying operation is carried out, and the data reading or verifying can be ensured to be correct data; therefore, by applying negative pressure to the Bulk end of the selected memory cell in the method for inhibiting over-erasure of the flash memory according to the embodiment of the present application, the problem that the over-erased memory cell in the flash memory generates error data due to the leakage of the memory cell in data reading or data verification can be effectively inhibited.

Specifically, a negative voltage is applied to a Word Line (Word Line) end of an unselected memory cell on the same bit Line, so that a corresponding negative voltage is applied to a source electrode of the memory cell which is connected with the unselected memory cell on the same bit Line and has an over-erase problem, and a voltage Vgs (hereinafter referred to as a gate-source voltage) between a gate electrode and a source electrode of the selected memory cell having the over-erase problem is reduced, and if a voltage of-1V is applied to the Word Line end of the unselected memory cell on the same bit Line, the gate-source voltage Vgs of the selected memory cell which is connected with the memory cell on the same bit Line and has the over-erase problem is correspondingly reduced by 1V, so that a corresponding gate trigger voltage Vgt is reduced by 1V; applying negative voltage to the word line end of the unselected memory unit on the same bit line of the over-erased memory unit can reduce the gate trigger voltage Vgt of the over-erased memory unit, and when the gate trigger voltage Vgt is reduced to be below 0V, the problem of electric leakage of the memory unit can not be caused when data reading or verifying operation is carried out, so that the data reading or verifying is correct; therefore, by applying negative voltage to the word line end of the unselected memory cell on the same bit line in the method for inhibiting the flash memory from over-erasing according to the embodiment of the present application, the problem that the over-erased memory cell in the flash memory generates error data due to memory cell leakage in data reading or data verification can be effectively inhibited, that is, the method for inhibiting the flash memory from over-erasing can inhibit the over-erased memory cell leakage to ensure accurate data reading without repairing the over-erased cell.

More specifically, Vgt = Vgs-Vt, and therefore the gate trigger voltage Vgt coincides with the variation amount of the gate voltage Vgs without variation of the threshold voltage Vt.

Specifically, a positive voltage is applied to the source end of the selected storage unit, and since the voltage on the gate of the selected storage unit is 0V, the gate voltage Vgs of the over-erased storage unit is reduced by the voltage value applied by the corresponding source end after the source end of the over-erased storage unit is additionally applied with the positive voltage, that is, when the source end applies a positive 1V voltage, the gate voltage Vgs of the storage unit is correspondingly reduced by 1V, so that the corresponding gate trigger voltage Vgt is reduced by 1V, the gate trigger voltage Vgt of the over-erased storage unit can be reduced by applying the positive voltage to the source end of the over-erased storage unit, and when the gate trigger voltage Vgt is reduced to be lower than 0V, the problem of electric leakage of the storage unit cannot be caused when data reading or verifying is performed, so that data reading or verifying is correct data; therefore, by applying positive pressure to the source end of the selected memory cell in the method for inhibiting over-erasure of the flash memory according to the embodiment of the present application, the problem that the over-erased memory cell in the flash memory generates error data due to leakage of the memory cell in data reading or data verification can be effectively inhibited.

In the method for inhibiting the flash memory from being over-erased, three basic processing modes of applying negative voltage to the Bulk end of the selected memory cell, applying negative voltage to the word line end of the unselected memory cell on the same bit line and applying positive voltage to the source end of the selected memory cell are provided, so that the leakage behavior of the over-erased memory cell during data reading and checking is inhibited, the erased memory cell can be normally used without being repaired, and the three basic processing modes can be used independently or in any matching mode, so that the method has the characteristic of diversity.

More specifically, since the absolute value of the voltage required by each of the three processing methods is large when the three processing methods are used individually, in some embodiments, it is preferable to use the three processing methods in combination so that the absolute value of the voltage applied to each portion is smaller than the absolute value of the voltage applied when the three processing methods are used individually, thereby effectively reducing power consumption, where fig. 1 shows the case of using the three processing methods in combination.

In some preferred embodiments, the negative pressure applied to the Bulk end of the selected memory cell is-0.75 to-0.25V; specifically, the negative voltage value can increase the threshold voltage Vt of the selected memory cell by 0.125V-0.375V, and accordingly decrease the gate trigger voltage Vgt by 0.125V-0.375V.

In this embodiment, a voltage of-0.5V is preferably applied to the Bulk terminal of the selected memory cell.

In some preferred embodiments, the negative voltage applied to the word line end of the unselected memory cell on the same bit line is-0.75 to-0.25V; specifically, the negative voltage value can reduce the gate voltage Vgs of the selected memory cell by 0.25 to-0.75V, so that the gate trigger voltage Vgt is correspondingly reduced by 0.25 to-0.75V.

In this embodiment, a voltage of-0.5V is preferably applied to the word line terminals of unselected memory cells on the same bit line.

In some preferred embodiments, the positive voltage applied to the source end of the selected memory cell is 0.25-0.75V; specifically, the positive voltage value can reduce the gate voltage Vgs of the selected memory cell by 0.25 to-0.75V, so that the gate trigger voltage Vgt is correspondingly reduced by 0.25 to-0.75V.

In this embodiment, a voltage of +0.5V is preferably applied to the source terminal of the selected memory cell.

In some preferred embodiments, when a negative voltage is applied to the Bulk terminal of the selected memory cell, a negative voltage is applied to the word line terminal of the unselected memory cell on the same bit line, and a positive voltage is applied to the source terminal of the selected memory cell at the same time, the three voltage values can be freely selected and matched, in this embodiment, the voltage value of the negative voltage applied to the Bulk terminal of the selected memory cell is equal to the voltage value of the negative voltage applied to the word line terminal of the unselected memory cell on the same bit line, and the absolute voltage value of the negative voltage applied to the word line terminal of the unselected memory cell on the same bit line is equal to the absolute voltage value of the positive voltage applied to the source terminal of the selected memory cell.

Specifically, the absolute values of the three voltages are equal, so that an excessive absolute value of one voltage can be avoided, and the power consumption of the method for inhibiting the flash over-erasing in the embodiment can be effectively reduced.

In some preferred embodiments, after applying a negative voltage to the Bulk terminal of a selected memory cell and/or applying a negative voltage to the word line terminal of an unselected memory cell on the same bit line and/or applying a positive voltage to the source terminal of the selected memory cell, the gate trigger voltage of the memory cell having the over-erase problem is lower than or equal to 0V.

Specifically, by adopting one or any combination of the three processing modes, as long as the gate trigger voltage Vgt is pulled down to 0V or below, the problem of leakage caused by continuous shutdown of the word line end of the memory cell with the over-erase problem during data reading due to the fact that the applied voltage is 0V and the gate trigger voltage Vgt is greater than 0 can be effectively avoided, and the problems of data reading errors and influence on reading of other area data caused by the leakage of the over-erase memory cell can be effectively avoided.

Referring to fig. 2, in a second aspect, fig. 2 is a device for suppressing over-erase of a Flash memory according to some embodiments of the present application, for suppressing over-erase of a memory cell in Nor Flash, including:

the acquisition module is used for reading or verifying data of the storage unit in the chip;

the voltage operation module is used for applying voltage to a storage unit terminal line in the chip;

the voltage operation module can apply negative voltage to the Bulk end of the selected memory cell and/or apply negative voltage to the word line end of unselected memory cells on the same bit line and/or apply positive voltage to the source end of the selected memory cell when the acquisition module performs reading or verifying data operation on the selected memory cell with the over-erasure problem in the chip.

Specifically, the voltage operation module may perform one or any combination of three operation methods of "applying a negative voltage to the Bulk terminal of the selected memory cell, applying a negative voltage to the word line terminal of the unselected memory cell on the same bit line, and applying a positive voltage to the source terminal of the selected memory cell", and may pull down the gate trigger voltage Vgt of the memory cell having the over-erase problem by less than 0V.

According to the device for inhibiting the flash memory from being over-erased, when the acquisition module reads data or verifies the data of the storage unit in the chip, the voltage operation module is used for performing one or any combination of three operations, so that the gate trigger voltage Vgt of the storage unit with the over-erase problem is lowered, the electric leakage behavior of the over-erase storage unit during data reading and verifying is inhibited, and the erase storage unit can be normally used under the condition of no repair.

In some preferred embodiments, the voltage operation module includes a first voltage module, a second voltage module, and a third voltage module, and when the obtaining module performs a read or verify data operation on a selected memory cell in the chip, where the memory cell has an over-erase problem, the first voltage module, the second voltage module, and the third voltage module simultaneously and respectively apply a negative voltage to a Bulk terminal of the selected memory cell, a negative voltage to a word line terminal of an unselected memory cell on the same bit line, and a positive voltage to a source terminal of the selected memory cell.

Specifically, according to design or use requirements, the first voltage module, the second voltage module and the third voltage module can be selected to operate individually or simultaneously in a plurality of modes so as to inhibit the leakage behavior of the over-erased memory cell during data reading and verifying.

In a third aspect, referring to fig. 3, fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.

In a fourth aspect, the present application provides a storage medium, and when being executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In summary, the method, the device, the electronic device, and the storage medium for suppressing the over-erase of the flash memory provided in the embodiments of the present application provide three basic processing manners, "applying a negative voltage to the Bulk terminal of a selected memory cell, applying a negative voltage to the word line terminal of an unselected memory cell on the same bit line, and applying a positive voltage to the source terminal of the selected memory cell", to suppress the leakage behavior of the over-erased memory cell during data read/verify, so that the erased memory cell can be normally used without being repaired, and the three basic processing manners can be used independently or in any combination, and have a diversity characteristic.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.