1. An erasing time obtaining method is used for obtaining the erasing time of Nor Flash, and is characterized by comprising the following steps:

performing a predetermined number of periodic cyclic operations of pre-programming, checking, erasing, over-erasing repairing and data repairing on the chip;

continuously reading a current enabling signal in each sector in the chip during the period of the periodic cycle operation;

according to the read enable signals, recording the duration of each enable signal in each sector until the end of the periodic cycle operation.

2. The method for acquiring erase time of claim 1, further comprising the steps of: and drawing and outputting a change trend chart of the time of each processing operation relative to the number of the periodic cycle operations.

3. The method of claim 2, wherein a trend graph of each sector, each block, and a whole chip is plotted.

4. The method of claim 1, wherein the enable signal comprises one of pre-programming enable, check enable, erase enable, over-erase detection repair enable, and data repair enable.

5. The method of claim 4, wherein the process of obtaining the enable signal is to sequentially determine whether the current enable signal is a pre-programming enable signal, a check enable signal, an erase enable signal, an over-erase detection repair enable signal, and a data repair enable signal.

6. The method of claim 1, wherein the determination of the duration of the enable signal is based on whether the enable signal is turned off or whether the current enable signal changes.

7. The method for acquiring erase time of claim 1, further comprising the steps of: the average or total time of each operation in a periodic loop operation is calculated for each sector, each block and the whole slice, respectively.

8. An apparatus for acquiring an erase time of Nor Flash, comprising:

the cyclic operation module is used for performing cyclic operation of preprogramming, checking, erasing, over-erasing repairing and data repairing on the chip;

the reading module is used for continuing the current enabling signal of each sector in the chip;

the computing module is used for computing the duration of the enabling signal;

the recording module is used for recording the duration of the enabling signal;

the reading module can read the current enabling signal of each sector of the chip in the periodic cycle operation, and the calculating module can calculate the duration of the current enabling signal and record and output the duration of the enabling signal by the recording module.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-7.

10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-7.

Background

The Erase operation of the Nor Flash Chip includes Sector Erase (a minimum unit of Erase, 512 bytes is one Sector), Block Erase (Block Erase, generally 64K units), and full Erase (Chip Erase). The sector erase time is typically 45ms, but as the number of erase operations continues to increase, the sector erase time also continues to increase.

The erasing Cycle (preprogramming-checking-erasing-overerasing-data repairing, Cycle) of the memory unit can be supported for 10 ten thousand times generally, and according to the erasing standard of a chip, the sector erasing time in the whole Cycle process cannot exceed 300 ms.

In the prior art, whether the erasing operation is finished or not can be judged only by inquiring a Busy signal (Busy signal) inside Nor Flash, and the method is used

Generally, the external part queries Busy signal inside Nor Flash to determine whether the erasing operation is finished by sending query command. The method can only know the time of the whole erasing operation, cannot obtain the time distribution of each operation stage in the whole cycle process, can only obtain the erasing time of the whole operation object, cannot distinguish the operation time corresponding to a specific area, but the data can be used as an important adjustment reference in the design and manufacture of the chip.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method and an apparatus for obtaining erase time, an electronic device and a storage medium, so as to obtain operation time of each stage in an erase-write cycle of a specific area in a chip.

In a first aspect, an embodiment of the present application provides a method for obtaining erase time, where the method is used to obtain erase time of Nor Flash, and the method includes the following steps:

performing a predetermined number of periodic cyclic operations of pre-programming, checking, erasing, over-erasing repairing and data repairing on the chip;

continuously reading a current enabling signal in each sector in the chip during the period of the periodic cycle operation;

according to the read enable signals, recording the duration of each enable signal in each sector until the end of the periodic cycle operation.

The method for acquiring the erasing time further comprises the following steps: and drawing and outputting a change trend chart of the time of each processing operation relative to the number of the periodic cycle operations.

The method for acquiring the erasing time comprises the step of respectively drawing a change trend graph of each sector, each block and the whole chip.

The method for acquiring the erasing time comprises the steps of enabling pre-programming, enabling checking, enabling erasing, enabling over-erasing detection and repair, and enabling data repair.

The method for acquiring the erasing time comprises the step of sequentially judging whether a current enabling signal is a pre-programming enabling signal, a checking enabling signal, an erasing enabling signal, an over-erasing detection repairing enabling signal and a data repairing enabling signal.

In the method for acquiring erase time, the reference for determining the duration of the enable signal is whether the enable signal is turned off or whether the current enable signal is changed.

The method for acquiring the erasing time further comprises the following steps: the average or total time of each operation in a periodic loop operation is calculated for each sector, each block and the whole slice, respectively.

According to the method for acquiring the erasing time, the enabling signal duration of each sector in the chip in the periodic cycle operation is read, so that the time of each sector corresponding to each stage in the periodic cycle operation can be acquired and used as an important basis for chip design and debugging, and chip development and manufacturing are facilitated.

In a second aspect, an embodiment of the present application further provides an apparatus for obtaining erase time, where the apparatus is used to obtain erase time of Nor Flash, and includes:

the cyclic operation module is used for performing cyclic operation of preprogramming, checking, erasing, over-erasing repairing and data repairing on the chip;

the reading module is used for continuing the current enabling signal of each sector in the chip;

the computing module is used for computing the duration of the enabling signal;

the recording module is used for recording the duration of the enabling signal;

the reading module can read the current enabling signal of each sector of the chip in the periodic cycle operation, and the calculating module can calculate the duration of the current enabling signal and record and output the duration of the enabling signal by the recording module.

According to the device for acquiring the erasing time, the cyclic operation module is used for carrying out the cyclic operation of programming, checking, erasing, over-erasing repairing and data repairing on the chip, in the process of the cyclic operation, the reading module is used for reading the enabling signal continuous condition of each sector in the chip in the cyclic operation, and then the computing module is matched with the recording module to acquire the use time of each sector in the corresponding cyclic operation period, so that the device can be used as an important basis for chip design and debugging, and chip development and manufacturing are facilitated.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.

In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program runs the steps in the method provided in the first aspect when executed by a processor.

As can be seen from the above, the method, the apparatus, the electronic device, and the storage medium for acquiring erase time provided in the embodiments of the present application provide that, in the acquisition method, the duration of the enable signal of each sector in the chip in the periodic cycle operation is read, so as to acquire the time of each sector corresponding to each stage in the periodic cycle operation, which can be used as an important basis for chip design and debugging, and is beneficial to chip development and manufacturing.

Drawings

Fig. 1 is a flowchart of a method for acquiring an erase time according to an embodiment of the present disclosure.

Fig. 2 is a logic diagram of enabling signal reading in an erase time obtaining method according to an embodiment of the present application.

Fig. 3 is a schematic structural diagram of an apparatus for acquiring erase time according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

In a first aspect, please refer to fig. 1, fig. 1 is a method for obtaining an erase time of Nor Flash in some embodiments of the present application, where the method includes the following steps:

performing a predetermined number of periodic cyclic operations of pre-programming, checking, erasing, over-erasing repairing and data repairing on the chip;

specifically, the operations of pre-programming, checking, erasing, over-erasing repairing and data repairing are one Cycle, and various types of test operations of the flash memory chip generally use a plurality of cycles as an operation unit.

Specifically, the predetermined number of times is 100k to 1000k times, that is, the erasing time acquisition calculation performed in the present application is performed by Cycle operation of 100k times or more.

Specifically, the pre-programming operation is to write preset data into the memory cells in the chip, and the memory cells are represented as 1 when in an erasing state, so the pre-programming is preferably all-0 programming, and it is ensured that all the memory cells containing the programmed data can be erased in the subsequent erasing operation, which is beneficial to the acquisition and calculation of the erasing time, so that the acquired erasing time is more representative.

Specifically, the checking process is used for checking whether the memory cells are all written with the pre-programmed data, and if an unprogrammed area is found, the chip is programmed again to ensure that the pre-programmed data covers the whole chip.

Specifically, the erasing operation is to repeatedly erase the chip, and directly erase all the data in the memory cells in the chip, i.e. erase all the data 0 to 1 in this embodiment.

Specifically, due to the different difficulty of erasing different memory cells, during repeated erase operations, partially over-erased memory cells may be generated, which temporarily cannot be used normally, and thus the over-erased memory cells need to be repaired by repair.

In particular, data repair is used for data in memory cells where special anomalies in the data representation occur.

Continuously reading a current enabling signal in each sector in the chip during the period of the periodic cycle operation;

specifically, the chip needs to send out corresponding specific enabling signals to execute different stages during the Cycle operation, so that reading the current enabling signal in the chip can know which stage in the Cycle the chip is in.

More specifically, during the operation of the chip, the specific operation condition of each sector is independently acquired by respectively acquiring the enable signal in each sector in the unit of operation of a block or a sector.

According to the read enable signals, recording the duration of each enable signal in each sector until the end of the periodic cycle operation.

Specifically, since the enable signal in the sector is read in a continuous acquisition manner, the duration of each phase in the Cycle can be calculated in a differentiated manner by the change of the enable signal, so that the time of each sector in each operation in the Cycle can be accurately acquired.

According to the method for acquiring the erasing time, the enabling signal duration of each sector in the chip in the periodic cycle operation is read, so that the time of each sector corresponding to each stage in the periodic cycle operation can be acquired and used as an important basis for chip design and debugging, and chip development and manufacturing are facilitated.

In some preferred embodiments, the status register is accessed through the I/O interface to read the enable signal; the state register which does not belong to the flash memory chip originally is accessed through the I/O interface, and the change condition of the enabling signal can be accurately detected and recorded by the state register which is accessed from the outside under the condition of not changing the normal operation of the chip, so that the obtaining method of the embodiment of the application is ensured not to influence the operation performance of the chip, the reading process is prevented from influencing the Cycle duration of the chip, and the obtaining time of the obtaining method is more accurate and representative.

In some preferred embodiments, the method further comprises the steps of: and drawing and outputting a change trend chart of the time of each processing operation relative to the number of the periodic cycle operations.

Specifically, each cycle operation includes a whole erasing operation stage, that is, the number of cycle operations represents the erasing number, and the erasing operation is the most important factor causing the performance change of the memory cells in the chip, so that the cycle operation number which is the same as the erasing number is used as the abscissa of the change trend graph to draw the change trend graph, the relationship between the erasing number of the chip and the time consumption of each stage in the cycle operation can be intuitively reflected, and the change trend graph can be used as an important basis for chip design and debugging.

In some preferred embodiments, the trend graph is plotted for each sector, each block, and the whole chip.

Specifically, the change trend graph of each sector can be drawn to intuitively reflect the change situation of the erasing performance of the sectors at different positions in the same block, the change trend graph of each block can be drawn to intuitively reflect the change situation of the erasing performance of the blocks at different addresses in the chip, and the change situation of the erasing performance of the test chip about Cycle times can be seen by drawing the change trend graph of the whole chip.

In some preferred embodiments, programming data at the pre-programming stage of the similar or opposite periodic cycle operation can be designed, and the comparison analysis can be performed on the same type of flash memory chip, so that the influence of writing different types of data on the whole chip, block and sector of the chip can be observed.

In some preferred embodiments, the enable signal includes pre-program enable, check enable, erase enable, over-erase detect repair enable, data repair enable.

Specifically, each phase of the periodic cycle operation turns on a different enable signal in one-to-one correspondence with the operation of the corresponding phase, so that the enable signals include pre-programming enable, check enable, erase enable, over-erase detection repair enable, data repair enable.

In some preferred embodiments, the obtaining the enable signal process is to sequentially determine whether the current enable signal is a pre-programming enable, a check enable, an erase enable, an over-erase detection repair enable, or a data repair enable.

In particular, the sequential judgment logic is arranged, so that the omission of the enable signal can be effectively prevented.

In other embodiments, the determination sequence may be designed according to the average duration of different enable signals in the normal state, for example, the longest programming time is scheduled to be the last determination.

In some preferred embodiments, the enable signal duration is determined based on whether the enable signal is off or whether a transition of the current enable signal occurs.

Specifically, the enable signal transitions to represent the previous stage enable signal being turned off and the next stage enable signal being turned on, which indicates the end of the previous operation in the cyclic operation and the start of the next operation.

Specifically, when the corresponding enable signal is turned on, the corresponding processing operation is started to be performed on the memory cell in the chip, when the corresponding enable signal is turned off, the corresponding processing operation is finished on the memory cell in the chip, for example, when the erase enable signal is turned on, the erase operation is performed on the memory cell, and when the erase enable signal is turned off, the erase operation on the memory cell is finished; therefore, in the present embodiment, the time duration of the corresponding operation can be calculated by monitoring the turn-on time point and the turn-off time point of the read enable signal.

In some preferred embodiments, the method further comprises the steps of: the average or total time of each operation in a periodic loop operation is calculated for each sector, each block and the whole slice, respectively.

Specifically, the block is composed of a plurality of sectors, and the whole slice is composed of a plurality of blocks, so that after calculating the average time or total time of each sector with respect to each operation, data on the block and the whole slice can be sequentially scaled based on the calculation result of the sector.

More specifically, the average time or total time of each operation is obtained, the performance differences of the cycles between the sectors located at different positions can be analyzed and reflected intuitively, similarly, the performance differences of the cycles between the blocks with different addresses and the performance conditions of the cycles on the whole can be analyzed and reflected, the Cycle capability relationship between the blocks and the sectors contained in the blocks can also be analyzed and reflected, and the data can be used as important bases for chip design and development.

In some preferred embodiments, the detection enable is configured to be turned on, i.e. started to continuously read the current enable signal in the sector in the chip, at the beginning or during the operation of the cycle.

More specifically, if a norflash to be tested is periodically cycled, the read logic for each operation phase of the sector of the norflash is as shown in fig. 2, the detection enable tcnt _ enable is turned on, which of the currently turned-on enable signals corresponds to the signals f _ pp _ start, f _ rd start, f _ era _ start, f _ tmv _ start, f _ tdata _ start for pre-programming enable, check enable, erase enable, over-erase detection repair enable, data repair enable, the enable signals are turned on, when the corresponding enable signals are identified, the enable signals are started to be clocked, and whether the enable signals are turned off is continuously read, when the enable signals are turned off, the phase squeezing timing is ended, when the timing result is recorded as the corresponding operation in the periodic cycling operation of the round, the current enable signal of the sector is read again, the timing of the next operation is performed, signals corresponding to pre-program enable, check enable, erase enable, over-erase detection repair enable, data repair enable off are f _ pp _ end, f _ rd end, f _ era _ end, f _ tmv _ end, f _ tdata _ end.

Referring to fig. 3, fig. 3 is a device for acquiring erase time in norflash according to some embodiments of the present application, including:

the cyclic operation module is used for performing cyclic operation of preprogramming, checking, erasing, over-erasing repairing and data repairing on the chip;

the reading module is used for continuing the current enabling signal of each sector in the chip;

the computing module is used for computing the duration of the enabling signal;

the recording module is used for recording the duration of the enabling signal;

the reading module can read the current enabling signal of each sector of the chip in the periodic cycle operation, and the calculating module can calculate the duration of the current enabling signal and record and output the duration of the enabling signal by the recording module.

According to the device for acquiring the erasing time, the cyclic operation module is used for carrying out the cyclic operation of programming, checking, erasing, over-erasing repairing and data repairing on the chip, in the process of the cyclic operation, the reading module is used for reading the enabling signal continuous condition of each sector in the chip in the cyclic operation, and then the computing module is matched with the recording module to acquire the use time of each sector in the corresponding cyclic operation period, so that the device can be used as an important basis for chip design and debugging, and chip development and manufacturing are facilitated.

In some preferred embodiments, the system further comprises a drawing module for drawing a variation trend graph about each sector, each block and the whole chip according to the data recorded by the recording module.

Specifically, the change trend graph of each sector drawn by the drawing module can intuitively reflect the change situation of the erasing performance of the sectors at different positions in the same block, the change trend graph of each block can intuitively reflect the change situation of the erasing performance of the blocks at different addresses in the chip, and the change situation of the erasing performance of the test chip about Cycle times can be seen by drawing the change trend graph of the whole chip.

In some preferred embodiments, the system further comprises a statistical module for calculating an average or total time of each sector, each block and the whole slice in each operation of the periodic loop operation, respectively.

Specifically, after the average time or the total time of each sector with respect to each operation is calculated by the statistical module, the data on the blocks and the whole slice may be sequentially scaled based on the calculation result of the sector.

More specifically, the average time or total time of each operation is obtained, the performance differences of the cycles between the sectors located at different positions can be analyzed and reflected intuitively, similarly, the performance differences of the cycles between the blocks with different addresses and the performance conditions of the cycles on the whole can be analyzed and reflected, the Cycle capability relationship between the blocks and the sectors contained in the blocks can also be analyzed and reflected, and the data can be used as important bases for chip design and development.

In a third aspect, referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.

In a fourth aspect, the present application provides a storage medium, and when being executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In summary, embodiments of the present application provide a method and an apparatus for obtaining erase time, an electronic device and a storage medium, where the obtaining method obtains a duration of an enable signal of each sector in a chip in a periodic cycle operation by reading the duration of the enable signal of each sector in the chip in the periodic cycle operation, and the duration of each sector corresponding to each stage in the periodic cycle operation can be used as an important basis for chip design and debugging, thereby facilitating chip development and manufacturing.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.