1. An erase method with low erase damage for NOR FLASH erase operations, the method comprising: when the NOR FLASH is subjected to the erasing operation, the establishment time point and/or the release time point of the positive high voltage and the negative high voltage for carrying out the erasing operation on the storage unit in the chip are staggered.

2. The erasing method with low erasing damage as claimed in claim 1, wherein the process of staggering the set-up time points of the positive high voltage and the negative high voltage for the erasing operation of the memory cell in the chip comprises the steps of:

a1, configuring and turning on an erasing enable signal;

a2, establishing a positive high voltage and a negative high voltage for erasing the memory cells in the chip, wherein the establishment time point of the positive high voltage is earlier than the establishment time point of the negative high voltage;

and A3, performing an erasing operation on the corresponding memory cell by using the positive high voltage and the negative high voltage after the stabilization is established.

3. An erase method with low erase damage as claimed in claim 2, wherein in step a2, said erase enable signal is asserted while said positive high voltage is established.

4. An erase method with low erase damage as claimed in claim 1, wherein said positive high voltage and said negative high voltage are applied to the erased cells selected and the erased cells unselected, respectively.

5. The erasing method with low erasing damage as claimed in claim 1, wherein the process of staggering the releasing time points of the positive high voltage and the negative high voltage for the erasing operation of the memory cell in the chip comprises the steps of:

b1, discharging the negative high voltage at the end stage of the NOR FLASH erasing and before the erasing enable signal fails;

b2, discharging the Bulk voltage of the Bulk end of the memory cell for the first time;

b3, end erase enable signal to raise the positive high voltage to the supply voltage, and discharge the Bulk voltage a second time to 0V.

6. An erase method with low erase damage as claimed in claim 5, wherein the Bulk voltage is first discharged to the same value as the supply voltage.

7. An erase method with low erase damage as claimed in claim 5, wherein the negative high voltage is discharged to 0V.

8. An erase apparatus with low erase damage for NOR FLASH erase operations, comprising:

the enabling signal module is used for configuring, opening and closing an erasing enabling signal;

the voltage module is used for providing various voltages required by the erasing operation for the memory unit;

a staggering module for staggering the establishment time point and/or the release time point of the positive high voltage and the negative high voltage of the erasing operation;

the erasing operation can be correspondingly started or ended according to the on or off of the erasing enabling signal of the enabling signal module, and the staggering module is matched with the establishment time point and the release time point of the positive high voltage and the negative high voltage provided by the voltage module in the corresponding operation stage.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-7.

10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-7.

Background

In the read-write erasing operation of the NOR FLASH chip, because the voltage difference used in the erasing operation process is the highest, particularly when the erasing operation is established, the positive and negative high voltages in the chip are established, because of the functions similar to capacitive coupling, a higher voltage difference can be generated instantly, high-voltage devices in the chip can be damaged, the standby power consumption of the chip can be increased, the functions and the performance of the chip can be affected seriously, and the problem is more obvious particularly after the technological feature size of the NOR FLASH chip is gradually reduced. Although the chip that may have the problem can be screened out by the pressure test in the test before the product is shipped, the test yield loss is brought, the cost of the chip is increased, and therefore, a design method for solving the problem from the source is urgent.

Specifically, when the NOR FLASH chip is erased, corresponding voltages are applied to the selected erased storage unit and the unselected erased storage unit through word lines to perform targeted erasing, the corresponding Bulk end of the storage unit also has a voltage Vbulk of 7-10V, namely, Bulk voltage and negative high voltage are applied to the selected erased storage unit, Bulk voltage and positive high voltage are applied to the unselected erased storage unit, as shown in fig. 1, in the process of erasing the storage unit, in the NOR FLASH word line decoding circuit, positive high voltage VPP _ WL and negative high voltage Vneg are added to the source and drain ends of high voltage nmos (mos) and high voltage pmos (hv pmos) of the word line decoding circuit; in the process of establishing the erasing voltage, the positive high-voltage VPP _ WL is coupled and increased to a voltage value higher than the target voltage along with the Vbulk voltage increasing establishment in the initial establishing stage, and because the positive high-voltage VPP _ WL and the negative high-voltage Vneg are simultaneously established, when the negative high-voltage Vneg reaches the lowest voltage value, the positive high-voltage VPP _ WL still does not drop to the target voltage, the voltage difference between the positive high-voltage VPP _ WL and the negative high-voltage Vneg is the largest, the voltage difference value is close to or exceeds the breakdown voltage of the high-voltage MOS device, the high-voltage MOS device is damaged, and the NOR Flash erasing programming cycle number is greatly reduced.

In addition, during the end of the erasing voltage, an equivalent capacitance is arranged between the positive high voltage Vneg of the word line end of the memory cell and the Bulk voltage Vbulk, and during the power generation of the erasing voltage, Vneg is coupled to a more negative voltage along with the rapid discharge of the Vbulk voltage until the end of the Vbulk discharge. The positive high voltage VPP _ WL is also coupled to a lower voltage due to the discharge of the Bulk voltage Vbulk, but the capacitance between the positive high voltage VPP _ WL and the Bulk voltage Vbulk is large, the voltage difference between the coupled VPP _ WL is not large as the voltage difference between the coupled VPP _ WL and the coupled Vbulk, and in addition, the speed of switching the positive high voltage VPP _ WL to the voltage value of the supply voltage VCC is generally high, so that the voltage difference between the positive high voltage VPP _ WL and the negative high voltage Vbulk is increased instantaneously at the end of the erase voltage, the voltage difference is close to or exceeds the breakdown voltage of the high voltage MOS device, the damage is caused to the high voltage MOS device, and the NOR Flash erase programming cycle number is greatly reduced.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide an erasing method and apparatus with low erasing damage, an electronic device, and a storage medium, which effectively reduce the damage of the erasing voltage to the high voltage MOS device.

In a first aspect, an embodiment of the present application provides an erasing method with low erase damage, which is used for a NOR FLASH erase operation, and the method includes: when the NOR FLASH is subjected to the erasing operation, the establishment time point and/or the release time point of the positive high voltage and the negative high voltage for carrying out the erasing operation on the storage unit in the chip are staggered.

The erasing method with low erasing damage comprises the following steps of:

a1, configuring and turning on an erasing enable signal;

a2, establishing a positive high voltage and a negative high voltage for erasing the memory cells in the chip, wherein the establishment time point of the positive high voltage is earlier than the establishment time point of the negative high voltage;

and A3, performing an erasing operation on the corresponding memory cell by using the positive high voltage and the negative high voltage after the stabilization is established.

The erasing method with low erasing damage is described, wherein, in the step A2, the establishment of the positive high voltage is started at the same time when the erasing enable signal is activated.

The erasing method with low erasing damage is characterized in that the positive high voltage and the negative high voltage respectively correspond to the memory cells which are erased in a selected mode and the memory cells which are not erased in a selected mode.

The erasing method with low erasing damage comprises the following steps of:

b1, discharging the negative high voltage at the end stage of the NOR FLASH erasing and before the erasing enable signal fails;

b2, discharging the Bulk voltage of the Bulk end of the memory cell for the first time;

b3, end erase enable signal to raise the positive high voltage to the supply voltage, and discharge the Bulk voltage a second time to 0V.

In the erasing method with low erasing damage, the Bulk voltage is discharged for the first time to the equivalent value of the power supply voltage.

The erasing method with low erasing damage is characterized in that negative high voltage is discharged to 0V.

In a second aspect, an embodiment of the present application further provides an erasing apparatus with low erase damage, which is used for a NOR FLASH erase operation, and includes:

the enabling signal module is used for configuring, opening and closing an erasing enabling signal;

the voltage module is used for providing various voltages required by the erasing operation for the memory unit;

a staggering module for staggering a setup time point and a release time point of the positive high voltage and the negative high voltage of the erase operation;

the erasing operation can be correspondingly started or ended according to the on or off of the erasing enabling signal of the enabling signal module, and the staggering module is matched with a setting time point and/or a releasing time point of the positive high voltage and the negative high voltage provided by the voltage module in the corresponding operation stage.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.

In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program runs the steps in the method provided in the first aspect when executed by a processor.

As can be seen from the above, the erasing method, the erasing device, the electronic device and the storage medium with low erasing damage provided by the embodiments of the present application, wherein the method includes two stages of operations to reduce the damage of the erasing operation, and the two stages of operations can be used independently or simultaneously, and can effectively prevent the MOS device from being damaged due to an excessive voltage difference between the positive high voltage and the negative high voltage, so that the damage of the device in the NOR FLASH erasing process can be effectively reduced.

Drawings

FIG. 1 is a schematic diagram of a NOR FLASH wordline decoding circuit.

Fig. 2 is a flowchart illustrating staggering the time points of the positive high voltage and the negative high voltage during the erase voltage setup phase in an erase method with low erase damage in some embodiments provided by the present application.

Fig. 3 is a graph of voltage variation staggering the time points at which positive and negative high voltages are established.

Fig. 4 is a flowchart illustrating an erase method with low erase damage in some embodiments of the present application, wherein the erase voltage is set up in a staggered manner.

Fig. 5 is a flowchart illustrating staggering release time points of a positive high voltage and a negative high voltage in an erase voltage setup phase in an erase method with low erase damage according to an embodiment of the disclosure.

Fig. 6 is a graph of voltage changes staggered at the release time points of positive and negative high voltages.

Fig. 7 is a flowchart illustrating an erase method with low erase damage in some embodiments according to the present application, wherein the erase voltage release time is staggered.

FIG. 8 is a schematic structural diagram of an erasing apparatus with low erase damage in some embodiments provided by the embodiments of the present application.

FIG. 9 is a schematic diagram of an apparatus for reducing erase damage during an erase voltage set-up phase.

FIG. 10 is a schematic diagram of an apparatus for reducing erase damage during the erase voltage release phase.

FIG. 11 is a schematic diagram of the structure of a selected erased cell and an unselected erased cell during NOR FLASH memory array erase.

Fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms first, second, etc. are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

In a first aspect, please refer to fig. 4 and 7, fig. 4 and 7 are erase methods with low erase damage for NOR FLASH erase operations in some embodiments of the present application, the method comprising: when the NOR FLASH is subjected to the erasing operation, the establishment time point and/or the release time point of the positive high voltage and the negative high voltage for carrying out the erasing operation on the storage unit in the chip are staggered.

The erasing method with low erasing damage comprises two stages of operation to reduce the damage of erasing operation, and the two stages of operation can be used independently or simultaneously to effectively avoid the damage of MOS devices caused by overlarge pressure difference between positive high voltage and negative high voltage, so that the damage of the devices in the NOR FLASH erasing process can be effectively reduced.

More specifically, an erasing method with low erasing damage according to the embodiment of the present application includes two methods for reducing erasing damage, and the two methods are respectively used in the erasing voltage establishing stage and the erasing voltage ending stage.

In some preferred embodiments, the method for reducing the erase damage in the erase voltage establishing stage is shown in fig. 2, and the process of staggering the establishing time points of the positive high voltage and the negative high voltage for the erase operation of the memory cells in the chip comprises the following steps:

a1, configuring and turning on an Erase enable signal Erase _ en;

specifically, the Erase enable signal Erase _ en is asserted to indicate that the chip is connected to the supply voltage VCC.

A2, establishing a positive high voltage VPP _ WL and a negative high voltage Vneg for carrying out erasing operation on the memory cells in the chip, wherein the establishment time point of the positive high voltage VPP _ WL is earlier than the establishment time point of the negative high voltage Vneg;

specifically, in the process of establishing the positive high-voltage VPP _ WL, the positive high-voltage VPP _ WL is coupled and rapidly pulled up along with the rising of Vbulk voltage, and then gradually falls to the preset and stable positive high-voltage VPP _ WL; during the establishment of the negative high voltage Vneg, the negative high voltage Vneg is reduced from 0V to a preset and stable negative high voltage Vneg.

More specifically, as can be seen from fig. 1, in the NOR FLASH word line decoding circuit, when erasing a NOR FLASH specific memory cell, a positive high voltage VPP _ WL and a negative high voltage Vneg are applied to two ends of a source drain of an HV NMOS (high voltage NMOS) and an HV PMOS (high voltage PMOS), and as shown in fig. 3, since a time point of establishing the positive high voltage VPP _ WL is earlier than a time point of establishing the negative high voltage Vneg, it is possible to effectively prevent the HV NMOS and the HV PMOS from being damaged or damaged due to an excessive voltage difference generated when the two are established and exceeding or approaching to breakdown voltages of the HV NMOS and the HV PMOS.

And A3, performing an erasing operation on the corresponding memory cell by using the stabilized positive high voltage VPP _ WL and the negative high voltage Vneg.

Specifically, during a memory cell Erase, the memory cell has a Bulk voltage Vbulk that is established when the Erase enable signal Erase _ en is asserted.

According to the method for reducing the erasing damage, the positive high-voltage VPP _ WL is established earlier than the negative high-voltage Vneg by staggering the establishing time points of the positive high-voltage VPP _ WL and the negative high-voltage Vneg, and the phenomenon that the differential pressure of the source and the drain of the HV NMOS and the HV PMOS exceeds the close breakdown voltage to damage or damage the MOS device due to the fact that the excessive differential pressure is generated between the positive high-voltage VPP _ WL and the negative high-voltage Vneg due to the fact that the positive high-voltage VPP _ WL is pulled under the capacitive coupling effect is avoided, and therefore the damage of the device in the NOR FLASH erasing process can be effectively reduced.

In some preferred embodiments, in step a2, the establishment of the positive high voltage VPP _ WL is started simultaneously with the assertion of the Erase enable signal Erase _ en;

specifically, since the Bulk voltage Vbulk also starts to be established at the same time when the Erase enable signal Erase _ en is asserted, because there is a large equivalent capacitance between the positive high voltage VPP _ WL and the Bulk voltage Vbulk, the positive high voltage VPP _ WL is coupled and rises as the Bulk voltage Vbulk rises, and the positive high voltage VPP _ WL does not stop rising until the Bulk voltage Vbulk does not rise any more, and then the set target voltage (Vtarget) can be obtained by discharging the positive high voltage VPP _ WL.

In order to ensure the erasing speed, the establishment time of the positive high-voltage VPP _ WL and the Bulk voltage Vbulk is established according to the effective erasing enable signal Erase _ en, the establishment time point of the negative high-voltage Vneg is changed only in a staggered mode, and the maximum pressure difference generated at the source and the drain ends of the MOS device in the erasing process can be reduced under the condition that the erasing efficiency of the storage unit is not influenced as much as possible.

In some preferred embodiments, the negative high voltage Vneg is established after the positive high voltage VPP _ WL has been established stable.

Specifically, as shown in fig. 3, the time required for the positive high-voltage VPP _ WL to reach the stable target voltage through the discharging manner is much longer than the time required for the negative high-voltage Vneg to drop from 0V to the stable target voltage, and if the negative high-voltage Vneg is established in the discharging process of the positive high-voltage VPP _ WL, a large voltage difference is generated across the MOS device.

The staggering of the setup time points of the positive high voltage VPP _ WL and the negative high voltage Vneg may be implemented by a conditional instruction or a delay instruction, and since the conditional instruction involves many devices and has relatively complicated logic, in some preferred embodiments, the staggering of the setup time points of the positive high voltage VPP _ WL and the negative high voltage Vneg is implemented by a delay instruction in step a 2.

Specifically, a delay value is given to the delay command, and when the time point of the establishment of the positive high voltage VPP _ WL passes the time of the delay value, the establishment of the negative high voltage Vneg is started.

More specifically, the delay value is set according to an average value of the positive high voltage VPP _ WL obtained through simulation or actual multiple tests from the time of establishment to the time of stabilization to the target voltage, and may be directly set as the average value or set by shifting the average value by a certain value.

In some preferred embodiments, the positive high voltage VPP _ WL and the negative high voltage Vneg correspond to a selected erased memory cell and an unselected erased memory cell, respectively.

Specifically, the NOR FLASH erase process includes some selected memory cells that need to be erased and some unselected memory cells that do not need to be erased, and accordingly, the selected erased memory cells need to be erased by applying the negative high voltage Vneg, and the unselected erased memory cells need to be erased by applying the positive high voltage VPP _ WL to avoid being erased.

In some preferred embodiments, the positive high voltage VPP _ WL and the negative high voltage Vneg are both word line voltages.

Specifically, the positive high voltage VPP _ WL and the negative high voltage Vneg are both supplied with voltages through the word lines.

Specific examples of the method for reducing the erase damage are as follows:

figure 3 shows the voltage ramp during the erase voltage set-up for a NOR FLASH erase, wherein, the Erase enable signal Erase _ en is generated after the Erase enable is turned on to apply the input voltage VCC to the NOR FLASH, meanwhile, the Bulk voltage Vbulk and the positive high voltage VPP _ WL applied to the unselected erased memory cells in the NOR FLASH start to be established, the positive high voltage VPP _ WL is pulled up to a T1 position by the Bulk voltage Vbulk due to the capacitive coupling effect, at which time the Bulk voltage Vbulk reaches a preset voltage stabilization output, and then the positive high voltage VPP _ WL then starts to discharge and fall, after a preset delay value time, the positive high voltage VPP _ WL reaches its target voltage for stable output, and then establishing a negative high voltage Vneg for the selected memory unit needing to be erased in the NOR FLASH through the word line, and quickly reducing the negative high voltage Vneg to a target voltage to start erasing the selected erased memory unit.

In this embodiment, the Bulk voltage Vbulk is 7V to 10V, the target voltage of the positive high voltage VPP _ WL is 2V, the target voltage of the negative high voltage Vneg is-9V, and the breakdown voltage at the source and drain ends of the general high voltage MOS device is 12.5V to 13V, as shown in fig. 3, in this embodiment, after the maximum voltage difference generated between the positive high voltage VPP _ WL and the negative high voltage Vneg reaches the target voltage, the voltage difference is 11V, which is less than 12.5V to 13V, and thus damage to the source and drain ends of the high voltage MOS device can be effectively avoided.

Wherein, the positive high voltage VPP _ WL and the negative high voltage Vneg are both provided through the Word Line.

In some preferred embodiments, the method for reducing the erase damage in the end stage of the erase voltage is as shown in fig. 5, and the process of staggering the release time points of the positive high voltage and the negative high voltage for the erase operation of the memory cells in the chip includes the following steps:

b1, discharging the negative high voltage Vneg at the end stage of the NOR FLASH erasing and before the Erase _ en of the erasing enable signal fails;

specifically, when the NOR FLASH is erased, a positive high voltage VPP _ WL, a negative high voltage Vneg, and a Bulk voltage Vbulk are applied to a memory cell in the NOR FLASH chip based on an open Erase enable signal Erase _ en to perform Erase processing, and the existing Erase processing process is generally finished according to the Erase enable signal Erase _ en to reset the corresponding voltage; in the embodiment of the present application, before the end of the enable signal, the discharge processing of the negative high voltage Vneg is performed.

Specifically, the NOR FLASH Erase end phase refers to a phase in which the selected erased memory cell completes data Erase but the Erase enable signal Erase _ en has not yet failed.

B2, discharging the Bulk voltage Vbulk at the Bulk end of the memory cell for the first time;

specifically, after the first discharge of the Bulk voltage Vbulk, the voltage value is higher than 0V, i.e., the complete discharge is not performed.

B3, the end Erase enable signal Erase _ en raises the positive high voltage VPP _ WL to the supply voltage VCC and discharges the Bulk voltage Vbulk to 0V for the second time.

In the method for reducing the Erase damage, at the end stage of NOR FLASH Erase and before the Erase enable signal Erase _ en fails, the negative high voltage Vneg is discharged to reduce the voltage difference between the negative high voltage Vneg and the positive high voltage VPP _ WL, so that the situation that the voltage difference between the negative high voltage Vneg and the positive high voltage VPP _ WL is too large due to the fact that the negative high voltage Vneg is coupled and pulled down rapidly because of the subsequent Bulk voltage Vbulk discharge, and the HV NMOS and the HV PMOS are damaged or damaged due to the fact that the voltage difference exceeds or is close to the breakdown voltage of the HV NMOS and the HV PMOS is avoided; in addition, the embodiment of the application also divides Bulk voltage Vbulk discharge into two times, wherein the second discharge process is finished instantly after the Erase enable signal Erase _ en is finished, and compared with the original one-time discharge process, the discharge process has smaller discharge amount, and the voltage change values of negative high voltage Vneg and negative high voltage Vneg caused by the discharge amount are smaller, so that the voltage change fluctuation is smaller when the Erase operation is finished, and the damage of a high-voltage MOS device is effectively avoided.

Specifically, when the Erase enable signal Erase _ en is ended, the second discharge of the Bulk voltage Vbulk and the rising of the positive high voltage VPP _ WL are simultaneously started.

In some preferred embodiments, the Bulk voltage Vbulk is first discharged to the equivalent magnitude of the supply voltage VCC.

Specifically, the Bulk voltage Vbulk is discharged for the first time as an active discharge, as shown in fig. 6, the discharge process is relatively stable and is not completed as the second discharge in an instant manner, so that the voltage change of the negative high voltage Vneg and the positive high voltage VPP _ WL is not caused under the coupling effect.

More specifically, the Bulk voltage Vbulk is discharged for the first time to the equivalent size of the power supply voltage VCC, so that the regulation of stable point output of a chip circuit is facilitated, and the rising regulation of the positive high voltage VPP _ WL to the power supply voltage VCC is facilitated.

In some preferred embodiments, the negative high voltage Vneg is discharged to 0V, i.e., the negative high voltage Vneg on the corresponding memory cell is removed, and the negative high voltage Vneg is gradually discharged to 0V, i.e., the negative high voltage Vneg is completely discharged.

In some preferred embodiments, the first discharge of the Bulk voltage Vbulk is performed after the negative high voltage Vneg is discharged to a steady state.

In the actual operation process, during the discharge rising process of the negative high voltage Vneg, the Bulk voltage Vbulk can fluctuate upwards instantaneously due to the coupling effect; therefore, in the embodiment of the application, after the negative high voltage Vneg is discharged to a stable state, the Bulk voltage Vbulk is discharged for the first time, so that after the negative high voltage Vneg is completely discharged to 0V and is stable, the voltage change of the Bulk voltage Vbulk caused by the coupling effect of the change of the negative high voltage Vneg is also stable, and the voltage value which is abnormally changed under the mutual coupling effect of the negative high voltage Vneg and the Bulk voltage Vbulk is avoided.

The time point of the negative high-voltage Vneg discharge and the first discharge of the Bulk voltage Vbulk can be staggered in a condition instruction or delay instruction mode, and because the condition instruction has more related devices and relatively complex logic, in some preferred embodiments, the time point of the negative high-voltage Vneg discharge and the first discharge of the Bulk voltage Vbulk is staggered in the delay instruction.

Specifically, a delay value is given to the delay instruction, and after the time of the delay value passes from the time point when the negative high voltage Vneg starts to discharge, the first discharge of the Bulk voltage Vbulk is started.

More specifically, the delay value is set according to an average value of the positive and negative high voltages Vneg from the beginning of discharge to the time when the positive and negative high voltages Vneg are stabilized to 0V, which can be directly set as the average value, or set by offsetting a certain value on the average value.

In some preferred embodiments, a time point at which the Erase enable signal Erase _ en ends may be set by setting another delay value through a delay instruction at a time point at which the Bulk voltage Vbulk is first discharged.

In some preferred embodiments, the positive high voltage VPP _ WL and the negative high voltage Vneg correspond to a selected erased memory cell and an unselected erased memory cell, respectively.

Specifically, the NOR FLASH erase process includes some selected memory cells that need to be erased and some unselected memory cells that do not need to be erased, and accordingly, the selected erased memory cells need to be erased by applying the negative high voltage Vneg, and the unselected erased memory cells need to be erased by applying the positive high voltage VPP _ WL to avoid being erased.

In some preferred embodiments, the positive high voltage VPP _ WL and the negative high voltage Vneg are both word line voltages.

Specific examples of the method for reducing the erase damage are as follows:

fig. 6 shows a voltage variation process when the Erase voltage is finished in the NOR FLASH Erase process, wherein the left side in the diagram is the voltage status of each voltage at the end stage of the NOR FLASH Erase, that is, the Erase enable signal Erase _ en is the power supply voltage VCC, the Bulk voltage Vbulk is 7-10V (specifically selected according to the design requirement), the negative high voltage Vneg is-9V, and the positive high voltage VPP _ WL is 2V.

When the erasing operation is started to be finished, the negative high voltage Vneg is firstly discharged and gradually raised to 0V, in the process of raising the negative high voltage Vneg, the Bulk voltage Vbulk is slightly raised due to the coupling effect of the equivalent capacitor and then is lowered to the original voltage value to keep stable, then the delay value is delayed, the negative high voltage Vneg is ensured to be stabilized at 0V, the Bulk voltage Vbulk is discharged for the first time, the first discharging process is more stable relative to the raising of the negative high voltage Vneg, and therefore the voltage changes of the negative high voltage Vneg and the positive high voltage VPP _ WL are hardly caused; after the Bulk voltage Vbulk is discharged and stabilized to be equal to the power supply voltage VCC, the Erase enable signal Erase _ en is removed to be invalid, the positive high-voltage VPP _ WL and the Bulk voltage Vbulk instantly lose the Erase enable signal Erase _ en to rapidly change the power supply voltage VCC value and 0V respectively, the Bulk voltage Vbulk instantly completing the second discharge enables the negative high-voltage Vneg and the positive high-voltage VPP _ WL to instantly and slightly fall under the coupling action, however, the negative high-voltage Vneg completes the discharge firstly and the Bulk voltage Vbulk discharges a larger amount, the voltage difference between the positive high-voltage VPP _ WL and the negative high-voltage Vneg is far smaller than the breakdown voltage of the high-voltage MOS device (the breakdown voltage at the source and drain ends of the common high-voltage MOS device is between 12.5V and 13V), the maximum voltage difference between the positive high-voltage VPP _ WL and the negative high-voltage Vneg is 11V at the beginning of the Erase end stage of the FLASH, and damage to the source and drain ends of the high-voltage MOS device can be effectively avoided.

Specifically, when the erasing method with low erasing damage in the embodiment of the present application individually selects the establishment time points of the positive high voltage and the negative high voltage for performing the erasing operation on the memory cell in the chip in a staggered manner, as shown in fig. 4, the specific operation steps are as follows:

c1, selecting the storage unit to be erased;

specifically, according to the use requirement or the preset instruction, the memory cell needing to be erased in the NOR FLASH is set, and the memory cell needing to be erased is marked as selected erase.

C2, configuring and turning on an erasing enable signal, and establishing a positive high-voltage VPP _ WL, a negative high-voltage Vneg and Bulk voltages for erasing the memory cells in the chip, wherein the establishment time of the positive high-voltage VPP _ WL is earlier than the establishment time point of the negative high-voltage Vneg;

c3, releasing the positive high voltage VPP _ WL, the negative high voltage Vneg and the Bulk voltage Vbulk;

specifically, after the erase operation is completed, the corresponding voltage is released to complete the erase process of the selected erase storage unit.

And C4, performing over-erasure detection and repair on the memory cells after the erasure processing.

Specifically, since a part of the memory cells is in an over-erased state after being erased, and the part of the memory cells fails, the NOR FLASH needs to be subjected to over-erase detection to identify whether the memory cells in the over-erased state exist therein, and if the memory cells exist, the NOR FLASH needs to be repaired in time to ensure that the NOR FLASH can be normally used.

As shown in fig. 11, the memory cells of the NOR FLASH are selected to be erased, and the remaining memory cells are unselected erased, in the low-damage erasing method of the present embodiment, Bulk voltage Vbulk is applied to the memory cells on word line 0, negative high voltage Vneg is applied to the selected erased memory cells on word line 0, and positive high voltage VPP _ WL is applied to the unselected erased memory cells on corresponding word lines for protection to prevent erasure.

Therefore, according to the erasing method with low erasing damage provided by the embodiment of the application, the establishment time points of the positive high-voltage VPP _ WL and the negative high-voltage Vneg are staggered in the stage of establishing the erasing voltage, so that the positive high-voltage VPP _ WL is established earlier than the negative high-voltage Vneg, and the situation that the excessive voltage difference is generated between the positive high-voltage VPP _ WL and the negative high-voltage Vneg due to the fact that the voltage difference between the source and the drain of the HV NMOS and the source and the drain of the HV PMOS exceeds the approximate breakdown voltage to damage or damage an MOS device under the capacitive coupling action is avoided, and therefore the damage generated by the device in the NOR FLASH erasing process can be effectively reduced.

Specifically, when the erasing method with low erasing damage in the embodiment of the present application separately selects the releasing time points of the positive high voltage and the negative high voltage for performing the erasing operation on the memory cells in the chip in a staggered manner, as shown in fig. 7, the specific operation steps are as follows:

d1, selecting the storage unit to be erased;

specifically, according to the use requirement or the preset instruction, the memory cell needing to be erased in the NOR FLASH is set, and the memory cell needing to be erased is marked as selected erase.

D2, configuring and opening an erasing enable signal Erase _ en, and establishing Bulk voltage Vbulk, positive high voltage VPP _ WL and negative high voltage Vneg for erasing the chip memory unit;

specifically, a negative high voltage Vneg and a Bulk voltage Vbulk are applied to the memory cells selected for erasing processing, and a positive high voltage VPP _ WL and a Bulk voltage Vbulk are applied to the memory cells unselected for erasing for protection.

As shown in fig. 11, the memory cells of the NOR FLASH are selected to be erased, and the remaining memory cells are unselected erased, in the low-damage erasing method of the present embodiment, Bulk voltage Vbulk is applied to the memory cells on word line 0, negative high voltage Vneg is applied to the selected erased memory cells on word line 0, and positive high voltage VPP _ WL is applied to the unselected erased memory cells on corresponding word lines for protection to prevent erasure.

D3, discharging the negative high voltage Vneg;

specifically, after the erase of the selected and erased memory cell is completed, the negative high voltage Vneg applied to the selected and erased memory cell is discharged.

D4, discharging the Bulk voltage Vbulk at the Bulk end of the memory cell for the first time;

specifically, after the delay instruction, after the negative high voltage Vneg is completely discharged, the Bulk voltage Vbulk is discharged for the first time, so that the Bulk voltage Vbulk is discharged to the voltage value of the power supply voltage VCC.

D5, ending the Erase enable signal Erase _ en to raise the positive high voltage VPP _ WL to the supply voltage VCC and to discharge the Bulk voltage Vbulk to 0V for the second time;

specifically, the end of the Erase enable signal Erase _ en is ended after the Bulk voltage Vbulk completes the first discharge.

And D6, performing over-erasure detection and repair on the memory cell after the erasure processing.

Specifically, since a part of the memory cells is in an over-erased state after being erased, and the part of the memory cells fails, the NOR FLASH needs to be subjected to over-erase detection to identify whether the memory cells in the over-erased state exist therein, and if the memory cells exist, the NOR FLASH needs to be repaired in time to ensure that the NOR FLASH can be normally used.

According to the low-damage erasing method provided by the embodiment of the application, at the end stage of NOR FLASH erasing and before the Erase _ en of the Erase enable signal fails, the negative high voltage Vneg is discharged firstly, so that the pressure difference between the negative high voltage Vneg and the positive high voltage VPP _ WL when the Erase enable signal Erase _ en fails is reduced, and the situation that the pressure difference between the negative high voltage Vneg and the positive high voltage VPP _ WL is too large and the HV NMOS and the HV PMOS are damaged or damaged due to the fact that the negative high voltage Vneg is coupled and rapidly pulled down due to the discharging of the subsequent Bulk voltage Vbulk, and the breakdown voltage of the HV NMOS and the HV PMOS is exceeded or close to the breakdown voltage of the HV NMOS and the HV PMOS is avoided.

More specifically, when the erasing method with low erase damage in the embodiment of the present application simultaneously adopts two methods for reducing erase damage, the specific operation steps are as follows:

e1, selecting the storage unit to be erased;

e2, configuring and turning on an erasing enable signal, and establishing a positive high-voltage VPP _ WL, a negative high-voltage Vneg and Bulk voltages for performing erasing operation on a memory cell in the chip, wherein the establishment time of the positive high-voltage VPP _ WL is earlier than the establishment time point of the negative high-voltage Vneg;

e3, releasing the positive high voltage VPP _ WL, the negative high voltage Vneg and the Bulk voltage Vbulk;

e4, before the erasing stage is finished, discharging the negative high voltage Vneg;

specifically, after the erase of the selected and erased memory cell is completed, the negative high voltage Vneg applied to the selected and erased memory cell is discharged.

E5, discharging the Bulk voltage Vbulk at the Bulk end of the memory cell for the first time;

e6, ending the Erase enable signal Erase _ en to raise the positive high voltage VPP _ WL to the supply voltage VCC, and discharging the Bulk voltage Vbulk to 0V for the second time;

and E7, performing over-erasure detection and repair on the memory cell after the erasure processing.

In a second aspect, please refer to fig. 8, fig. 8 is a block diagram of an erase apparatus with low erase damage for NOR FLASH erase operation according to some embodiments of the present application, including:

the enabling signal module is used for configuring, opening and closing an erasing enabling signal;

the voltage module is used for providing various voltages required by the erasing operation for the memory unit;

a staggering module for staggering a setup time point and a release time point of the positive high voltage and the negative high voltage of the erase operation;

the erasing operation can be correspondingly started or ended according to the on or off of the erasing enabling signal of the enabling signal module, and the staggering module is matched with the establishment time point and/or the release time point of the positive high voltage and the negative high voltage provided by the voltage module in the corresponding operation stage.

Therefore, the erasing device with low erasing damage provided by the embodiment of the application can effectively reduce the erasing damage.

More specifically, the present application provides two methods for reducing the erase damage in some embodiments, which are used for the NOR FLASH erase operation to reduce the damage when the erase voltage is established and the damage when the erase voltage is ended.

The device for reducing erase damage for reducing damage during erase voltage setup, as shown in fig. 9, includes:

the enabling signal module is used for configuring and opening an erasing enabling signal;

the positive high voltage establishing module is used for establishing a positive high voltage VPP _ WL for erasing the memory unit according to the erasing enabling signal;

the negative high voltage establishing module is used for establishing a negative high voltage Vneg for erasing the storage unit according to the erasing enabling signal;

the time staggering module is used for staggering the establishment time point of the positive high voltage VPP _ WL and the establishment time point of the negative high voltage Vneg;

after the enabling signal module is opened to erase the enabling signal, the positive high-voltage establishing module and the negative high-voltage establishing module establish a positive high-voltage VPP _ WL and then establish a negative high-voltage Vneg under the action of the time staggering module.

The device for reducing the erasing damage configures an erasing enable signal according to the memory cells which are erased in a selected mode and are not erased in a selected mode through an enable signal module and turns on the erasing enable signal, a positive high voltage establishing module and a negative high voltage establishing module are respectively used for applying a positive high voltage VPP _ WL to the memory cells which are not erased in the NOR FLASH and applying a negative high voltage Vneg to the memory cells which are erased in the selected mode when the erasing enable signal is turned on, the delay values are set by the time staggering module to stagger the positive high voltage VPP _ WL and the negative high voltage Vneg set-up time points, so that the positive high voltage VPP _ WL is established earlier than the negative high voltage Vneg, and excessive pressure difference between the positive high voltage VPP _ WL and the negative high voltage Vneg caused by the pull of the rope under the capacitive coupling action is avoided, and the voltage difference between the source and the drain of the HV NMOS and the HV PMOS exceeds the breakdown voltage to damage or damage the MOS device, thereby effectively reducing the damage generated by the device in the NOR FLASH erasing process.

The device for reducing the erase damage for reducing the damage at the end of the erase voltage, as shown in fig. 10, includes:

an enable signal module for ending the Erase enable signal Erase _ en;

the negative high-voltage discharging module is used for discharging the negative high voltage Vneg applied to the storage unit;

the Bulk voltage discharging module is used for discharging a Bulk voltage Vbulk applied to the storage unit;

a positive high voltage regulating module for regulating a positive high voltage VPP _ WL applied to the memory cell;

the time staggering module is used for staggering the discharge time points;

when the memory unit erased in the NOR FLASH is erased, the negative high-voltage discharge module discharges the negative high voltage Vneg applied to the memory unit erased in the selection mode, the Bulk voltage discharge module discharges the Bulk voltage Vbulk for the first time after the time-staggered module delay interval, and the enable signal module finishes erasing the enable signal Erase _ en after the time-staggered module delays the interval again, so that the Bulk voltage discharge module discharges for the second time and the positive high-voltage regulation module regulates the positive high voltage VPP _ WL applied to the unselected Erase unit to the power supply voltage VCC.

The device for reducing the erasing damage utilizes the negative high-voltage discharging module to discharge the negative high voltage Vneg at the end stage of NOR FLASH erasing and before the erasing enable signal Erase _ en fails so as to reduce the pressure difference between the negative high voltage Vneg and the positive high voltage VPP _ WL when the erasing enable signal Erase _ en is ended by the enable signal module, and avoid that the pressure difference between the negative high voltage Vneg and the positive high voltage VPP _ WL is too large due to the fact that the negative high voltage Vneg is coupled and rapidly pulled down because of the subsequent Bulk voltage Vbulk discharging, and the voltage exceeds or is close to the breakdown voltage of HV NMOS and HV PMOS to cause damage or damage to the HV NMOS and the HV PMOS.

In a third aspect, referring to fig. 12, fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.

In a fourth aspect, the present application provides a storage medium, and when being executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.