1. A programming method, wherein a programming circuit and a program verification circuit each use independent data lines, the method comprising the steps of:

acquiring a multi-block programming instruction sent by a user;

controlling the corresponding two blocks to execute a programming operation or a programming verification operation according to the multi-block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, wherein the two blocks are a block 0 and a block 1;

and selecting to execute the programming operation according to the programming verification result until all blocks pass the programming verification.

2. The method according to claim 1, wherein the step of controlling the corresponding two blocks to perform the program operation or the program verify operation according to the multi-block program command, such that the program operation and the program verify operation between the two blocks are alternately performed in synchronization comprises:

performing a program verify operation on the block 0;

a program operation is performed on the block 0 while a program verify operation is performed on the block 1.

3. The method according to claim 1, wherein the step of controlling the corresponding two blocks to perform the program operation or the program verify operation according to the multi-block program command, such that the program operation and the program verify operation between the two blocks are alternately performed in synchronization comprises:

performing a program verify operation on the block 0 while performing a program operation on the block 1;

a program operation is performed on the block 0 while a program verify operation is performed on the block 1.

4. The method according to claim 1, wherein the step of controlling the corresponding two blocks to perform the program operation or the program verify operation according to the multi-block program command comprises:

generating a pgm _ en [1:0] control signal and a verify _ en [1:0] control signal by a logic circuit according to the multi-block programming instruction;

programming data to a corresponding block through a programming circuit according to the pgm _ en [1:0] control signal;

and outputting the program verification data of the corresponding block to a program verification circuit according to the verify _ en [1:0] control signal to execute the program verification operation.

5. The method of claim 4, wherein said step of programming data to the corresponding block through the programming circuit according to the pgm _ en [1:0] control signal comprises:

programming data is programmed onto the corresponding block through the programming circuit using the separate data line.

6. The programming method according to claim 4, wherein the step of outputting the program verification data of the corresponding block to the program verification circuit according to the verify _ en [1:0] control signal to perform the program verification operation comprises:

and outputting the program verification data of the corresponding block to a program verification circuit by using a separate data line to execute the program verification operation.

7. A memory circuit structure, comprising:

the storage module comprises a plurality of blocks for storage;

the logic circuit module is electrically connected with the storage module and is used for transmitting a multi-block programming instruction, a programming signal and a programming verification signal to the storage module;

a programming module electrically connected to the memory module using a separate data line for programming data into the corresponding block;

and the programming verification module is electrically connected with the storage module by using a single data line and is used for receiving programming verification data so as to perform programming verification on the blocks.

8. A programming apparatus, comprising:

the first acquisition module is used for acquiring a multi-block programming instruction sent by a user;

the first processing module is used for controlling the corresponding two blocks to execute programming operation or programming verification operation according to the multi-block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, wherein the two blocks are a block 0 and a block 1;

and the second processing module is used for selecting and executing the programming operation according to the programming verification result until all blocks pass the programming verification.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method according to any one of claims 1 to 7.

10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-7.

Background

However, in the internal circuit structure of the NOR FLASH memory, the programming circuit and the verifying circuit cannot work together, so that blocks can only be programmed in sequence when the memory needs to be programmed, and the conventional programming mode is shown in fig. 5, which causes a large amount of waiting time to be consumed for subsequent blocks to be programmed, and thus, the overall programming efficiency is seriously slowed down.

In view of the above problems, improvements are needed.

Disclosure of Invention

Embodiments of the present disclosure provide a programming method, a memory circuit structure, an apparatus, an electronic device, and a storage medium, which have the advantage of high programming efficiency.

In a first aspect, an embodiment of the present application provides a programming method, and a technical solution is as follows: the programming circuit and the programming verification circuit use independent data lines respectively, and the method comprises the following steps:

acquiring a multi-block programming instruction sent by a user;

controlling the corresponding two blocks to execute a programming operation or a programming verification operation according to the multi-block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, wherein the two blocks are a block 0 and a block 1;

and selecting to execute the programming operation according to the programming verification result until all blocks pass the programming verification.

Further, in this embodiment of the present application, the step of controlling the corresponding two blocks to perform a program operation or a program verify operation according to the multi-block program instruction, so that the program operation and the program verify operation between the two blocks are alternately and synchronously performed includes:

performing a program verify operation on the block 0;

a program operation is performed on the block 0 while a program verify operation is performed on the block 1.

Further, in this embodiment of the present application, the step of controlling the corresponding two blocks to perform a program operation or a program verify operation according to the multi-block program instruction, so that the program operation and the program verify operation between the two blocks are alternately and synchronously performed includes:

performing a program verify operation on the block 0 while performing a program operation on the block 1;

a program operation is performed on the block 0 while a program verify operation is performed on the block 1.

Further, in this embodiment of the present application, the step of controlling the corresponding two blocks to perform a program operation or a program verify operation according to the multi-block program instruction includes:

generating a pgm _ en [1:0] control signal and a verify _ en [1:0] control signal by a logic circuit according to the multi-block programming instruction;

programming data to a corresponding block through a programming circuit according to the pgm _ en [1:0] control signal;

and outputting the program verification data of the corresponding block to a program verification circuit according to the verify _ en [1:0] control signal to execute the program verification operation.

Further, in the embodiment of the present application, the step of programming the program data onto the corresponding block through the programming circuit according to the pgm _ en [1:0] control signal comprises:

programming data is programmed onto the corresponding block through the programming circuit using the separate data line.

Further, in this embodiment of the present application, the step of outputting the program verification data of the corresponding block to the program verification circuit according to the verify _ en [1:0] control signal to perform the program verification operation includes:

and outputting the program verification data of the corresponding block to a program verification circuit by using a separate data line to execute the program verification operation.

In a second aspect, the present application further provides a memory circuit structure, including:

the storage module comprises a plurality of blocks for storage;

the logic circuit module is electrically connected with the storage module and is used for transmitting a multi-block programming instruction, a programming signal and a programming verification signal to the storage module;

a programming module electrically connected to the memory module using a separate data line for programming data into the corresponding block;

and the programming verification module is electrically connected with the storage module by using a single data line and is used for receiving programming verification data so as to perform programming verification on the blocks.

In a third aspect, the present application further provides an apparatus for improving efficiency of multi-block programming, including:

the first acquisition module is used for acquiring a multi-block programming instruction sent by a user;

the first processing module is used for controlling the corresponding two blocks to execute programming operation or programming verification operation according to the multi-block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, wherein the two blocks are a block 0 and a block 1;

and the second processing module is used for selecting and executing the programming operation according to the programming verification result until all blocks pass the programming verification.

In a fourth aspect, the present application further provides an electronic device, comprising a processor and a memory, wherein the memory stores computer readable instructions, and the computer readable instructions, when executed by the processor, perform the steps of the method as described above.

In a fifth aspect, the present application also provides a storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of the method as described above.

As can be seen from the above, in the method, the apparatus, the electronic device, and the storage medium for improving the efficiency of multi-block programming provided in the embodiments of the present application, independent data lines are respectively disposed on the programming circuit and the programming verification circuit, and then a multi-block programming instruction sent by a user is obtained; controlling the corresponding two blocks to execute programming operation or programming verification operation according to the multi-block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, wherein the two blocks are a block 0 and a block 1; and selecting to execute the programming operation according to the programming verification result until all blocks pass the programming verification, thereby having the advantage of high programming efficiency.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Fig. 1 is a flowchart of a programming method according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of a programming device according to an embodiment of the present disclosure.

Fig. 3 is a schematic view of an electronic device according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a memory circuit structure according to an embodiment of the present disclosure.

FIG. 5 is a diagram of multi-block programming versus time in a conventional programming approach.

FIG. 6 is a diagram of multi-block programming versus time provided by an embodiment of the present application.

FIG. 7 is a diagram illustrating multi-block programming and timing comparison provided by an embodiment of the present application.

In the figure: 210. a first acquisition module; 220. a first processing module; 230. a second processing module; 300. an electronic device; 310. a processor; 320. a memory; 410. a storage module; 420. a logic circuit module; 430. a programming module; 440. and programming the verification module.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1 to 7, a programming method specifically includes: the programming circuit and the programming verification circuit use independent data lines respectively, and the method comprises the following steps:

s110, acquiring a multi-block programming instruction sent by a user;

s120, controlling the corresponding two blocks to execute programming operation or programming verification operation according to the multi-block programming instruction, and enabling the programming operation and the programming verification operation between the two blocks to be executed alternately and synchronously, wherein the two blocks are a block 0 and a block 1;

and S130, selecting to execute the programming operation according to the programming verification result until all blocks pass the programming verification.

With the above technical solutions, when the block 0 and the block 1 are programmed, the conventional solution needs to wait for the block 0 or the block 1 to complete the programming successfully before the subsequent block is programmed, this is because the conventional program circuit and program verify circuit use a common data line for data transmission, and in order not to cause data collision, thus, the program operation and the program verification operation are completely separated, resulting in a moment when the program and the program verification do not work together, the application realizes the simultaneous alternate execution of the programming operation and the programming verification operation among different blocks through separating the data buses of the programming circuit and the programming verification circuit, when the block 0 and the block 1 need to be programmed, the scheme of the application can greatly shorten or even eliminate the waiting time of the other block, and greatly improves the whole programming efficiency.

It should be noted that, in theory, it is possible to control block 0 and block 1 to perform the programming operation at the same time, and also control block 0 and block 1 to perform the program verifying operation at the same time, but the limited and NOR FLASH nonvolatile memory features that this needs to be implemented, which requires an increase in the area of the memory chip, which causes a cost increase and an impact on a series of processes, so for NOR FLASH, this scheme is not practical in actual production, and this problem can be avoided by performing the programming operation and the program verifying operation alternately at the same time, so that the present application uses the program operation and the program verifying operation alternately performed on block 0 and block 1, which satisfies the requirements of actual production while improving the programming efficiency.

Specifically, in some embodiments, the step of controlling the corresponding two blocks to perform the program operation or the program verify operation according to the multi-block program instruction, so that the program operation and the program verify operation between the two blocks are alternately and synchronously performed includes:

performing a program verify operation on Block 0;

a program operation is performed on block 0 while a program verify operation is performed on block 1.

Through the technical scheme, when the block 0 and the block 1 need to be programmed, the program verification operation can be firstly executed on the block 0, which is to detect whether the data on the block 0 is the same as the program data, if so, the program operation does not need to be executed on the block 0, if not, the program operation needs to be executed on the block 0, and if not, the program verification operation is executed on the block 0, so that whether the data on the block 1 is the same as the program data can be detected, if so, the program operation does not need to be executed on the block 0, and if not, the program operation needs to be executed on the block 1, so that the unnecessary program operation can be avoided, and the program time is saved.

Specifically, as shown in fig. 6, during a time period from t0 to t1, a program verify operation is performed on block 0 while block 1 is in a wait state, and during a time period from t1 to t2, a program operation is performed on block 0 while a program verify operation is performed on block 1. Compared with the prior art, the method can save time from t18 to t10 and effectively improve the overall programming efficiency by comparing fig. 5 and fig. 6 under the same condition.

Specifically, in some other embodiments, the step of controlling the corresponding two blocks to perform the program operation or the program verify operation according to the multi-block program instruction, so that the program operation and the program verify operation between the two blocks are alternately and synchronously performed includes:

performing a program verify operation on the block 0 while performing a program operation on the block 1;

a program operation is performed on block 0 while a program verify operation is performed on block 1.

Through the technical scheme, when the block 0 and the block 1 need to be programmed, the program verification operation can be firstly executed on the block 0, meanwhile, the program operation is executed on the block 1, the program verification operation is executed on the block 0 in order to detect whether the data on the block 0 is the same as the program data, if the data on the block 0 is the same as the program data, the program operation is not required to be executed on the block 0, if the data on the block 0 is different from the program data, the program operation is executed on the block 0 immediately when the program verification of the block 0 is not passed, the program operation is directly executed on the block 1, the waiting time for executing the program verification operation on the block 0 can be saved, and when the data on the block 1 is different from the program data, the overall program efficiency can be further improved.

Specifically, as shown in fig. 7, a program verify operation is performed on block 0 and, at the same time, on block 1 during a time period from t0 to t1, and a program verify operation is performed on block 0 and, at the same time, on block 1 during a time period from t1 to t 2. Compared with the prior art, the method can save time from t18 to t9 and effectively improve the overall programming efficiency by comparing fig. 5 with fig. 7 under the same condition.

Further, in the embodiment of the present application, the step of controlling the corresponding two blocks to perform the program operation or the program verify operation according to the multi-block program instruction includes:

generating a pgm _ en [1:0] control signal and a verify _ en [1:0] control signal by a logic circuit according to a multi-block programming instruction;

programming data on the corresponding blocks through the programming circuit and the individual data lines according to a pgm _ en [1:0] control signal;

and outputting the program verification data to the program verification circuit according to a verify _ en [1:0] control signal to execute the program verification operation.

Specifically, the programming data is programmed to the corresponding block through the programming circuit and the separate data lines by using the separate data lines.

Specifically, the program verifying operation is performed by outputting the program verifying data to the program verifying circuit using a separate data line.

Through the technical scheme, after a multi-block programming instruction sent by a user is received, a related logic circuit generates a pgm _ en [1:0] control signal and a verify _ en [1:0] control signal, under the control of the pgm _ en [1:0] control signal, programming data is taken out from an SRAM, then the programming circuit programs the designated block by using a single data line, meanwhile, the verify control signal controls another corresponding block to output programming verification data from the single data line, the programming verification data is sent to the programming verification circuit to execute the programming verification operation, meanwhile, the programming verification result is fed back to the logic circuit, whether the pgm operation is continuously executed or not is determined according to the feedback result m _ en [1:0] control signal, in the process, the block executing the programming operation and the block executing the programming verification operation are continuously and alternately and simultaneously operated, until all blocks pass the program verification, the program operation and the program verification operation do not generate mutual interference because data exchange is carried out through separate data lines respectively.

Specifically, in some embodiments, when programming bank 0 and bank 1, the user sends an instruction to program bank 0 and bank 1, the logic circuit receives the instruction and generates a pgm _ en [1:0] control signal and a verify _ en [1:0] control signal, the program data is output from the SRAM to the program circuit under the pgm _ en [1:0] control signal, the program circuit is then connected to bank 0 and bank 1 through a separate data line, in some embodiments, the program circuit programs the program data onto bank 0 through a separate data line, while at the same time, under the verify [1:0] control signal, bank 1 outputs the program verify data into the program verify circuit through another separate data line, the program verify operation is performed under the program verify circuit, and the result of the program verify is returned to the logic circuit, if the program verification is not passed, then under the action of a pgm _ en [1:0] control signal, the programming circuit programs the programming data into the block 1 through a single data line, meanwhile, because the block 0 just performs one programming operation, under the action of a verify _ en [1:0] control signal, the control block 0 outputs the program verification data into the programming verification circuit through another single data line, the programming verification operation is performed through the programming verification circuit, and then the block 0 and the block 1 are continuously and alternately performed with the programming and the program verification operations.

In a second aspect, the present application further provides a memory circuit structure, as shown in fig. 4, including:

the storage module comprises a plurality of blocks for storage; such as block 0, block 1.

The logic circuit module is electrically connected with the storage module and is used for transmitting the multi-block programming command, the programming signal and the programming verification signal to the storage module;

the programming module is electrically connected with the storage module by using a single data line and is used for programming the programming data into the corresponding block;

and the programming verification module is electrically connected with the storage module by using a single data line and is used for receiving programming verification data and performing programming verification on the corresponding block.

By the technical scheme, the memory circuit structure can realize independent execution of programming operation and programming verification operation, when a block in a memory module needs to be programmed, a user sends a multi-block programming instruction, for example, a block 0 and a block 1 are programmed, a logic circuit module generates corresponding control signals after receiving the instruction, for example, a pgm _ en [1:0] control signal and a verify _ en [1:0] control signal, under the action of the pgm _ en [1:0] control signal, programming data are output to a programming module from an SRAM, then the programming module is connected with the block 0 and the block 1 through separate data lines, in some specific embodiments, the programming module programs the programming data to the block 0 through a separate data line, meanwhile, under the action of the verify _ en [1:0] control signal, the block 1 outputs the programming verification data to the programming verification module through another separate data line, and executing the programming verification operation under the programming verification module, simultaneously returning the result of the programming verification to the logic circuit module, if the programming verification is not passed, then under the action of a pgm _ en [1:0] control signal, the programming module programs the programming data into the block 1 through a single data line, meanwhile, because the block 0 just executes the programming operation once, under the action of a verify _ en [1:0] control signal, the control block 0 outputs the programming verification data into the programming verification module through another single data line, the programming verification operation is executed through the programming verification module, and then the block 0 and the block 1 are continuously and alternately executed with the programming and the programming verification operations.

In a third aspect, the present application further provides a programming apparatus, comprising:

the first acquisition module is used for acquiring a multi-block programming instruction sent by a user;

the first processing module is used for controlling the corresponding two blocks to execute programming operation or programming verification operation according to the multi-block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, and the two blocks are a block 0 and a block 1;

and the second processing module is used for selecting and executing the programming operation according to the programming verification result until all blocks pass the programming verification.

According to the technical scheme, the multi-block programming instruction sent by the user is obtained through the first obtaining module, then the first processing module controls the corresponding two blocks to execute the programming operation or the programming verification operation according to the block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, and finally the second processing module selects to execute the programming operation according to the programming verification result until all the blocks pass the programming verification. When the block 0 and the block 1 are programmed, the conventional scheme is that the programming operation can be executed on the subsequent block only after the block 0 or the block 1 is successfully programmed, because the conventional programming circuit and the programming verification circuit use a common data line for data transmission, in order to avoid data conflict, the programming operation and the programming verification operation are thoroughly separated, so that the programming and the programming verification do not work together at the moment.

In a fourth aspect, the present application further provides an electronic device, which includes a processor and a memory, where the memory stores computer-readable instructions, and the steps in the above method are executed when the computer-readable instructions are executed by the processor.

With the above technical solution, the processor and the memory are interconnected and communicate with each other through a communication bus and/or other types of connection mechanisms (not shown), the memory stores a computer program executable by the processor, and when the computing device runs, the processor executes the computer program to execute the method in any optional implementation manner of the foregoing embodiment, so as to implement the following functions: acquiring a multi-block programming instruction sent by a user; controlling the corresponding two blocks to execute programming operation or programming verification operation according to the multi-block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, wherein the two blocks are a block 0 and a block 1; and selecting to execute the programming operation according to the programming verification result until all blocks pass the programming verification.

In a fifth aspect, the present application further provides a storage medium having a computer program stored thereon, the computer program, when executed by a processor, performing the steps of the above method.

Through the technical scheme, when being executed by a processor, the computer program executes the method in any optional implementation manner of the embodiment to realize the following functions: acquiring a multi-block programming instruction sent by a user; controlling the corresponding two blocks to execute programming operation or programming verification operation according to the multi-block programming instruction, so that the programming operation and the programming verification operation between the two blocks are alternately and synchronously executed, wherein the two blocks are a block 0 and a block 1; and selecting to execute the programming operation according to the programming verification result until all blocks pass the programming verification.

The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.