1. A method for accelerating NORFLASH programming speed is characterized by comprising the following steps:

acquiring programming times A required for successful programming in the programming process of the last programming address;

and according to the programming times A, performing programming verification when programming the A-th time in the programming process of the programming address at this time, and updating the A to be the programming times required by successful programming in the programming process of the programming address at this time.

2. The method for accelerating NORFLASH programming speed as claimed in claim 1, further comprising:

the programming voltage for the first programming in the programming process of the current programming address is kept the same as the programming voltage for the first programming in the programming process of the last programming address.

3. The method of claim 1, wherein the step of obtaining the number of times A of programming required for successfully programming the last programming address comprises:

judging whether programming of a last programming address exists or not;

if yes, acquiring programming times A required by successful programming in the programming process of the last programming address;

if not, programming according to normal programming, programming verification, programming and programming verification.

4. The method for accelerating NORFLASH programming speed according to claim 3, wherein said step of programming according to normal programming, program checking, programming, program checking.

Setting a cnt counter, wherein the cnt counter = 1;

adding 1 to the cnt counter every time programming verification fails;

a = cnt counter.

5. The method of claim 1, wherein the step of updating a to be the number of times of programming required for successful programming in the programming process of the current programming address comprises:

setting a cnt counter, wherein the cnt counter = programming times A required by successful programming in the programming process of the last programming address;

adding 1 to the cnt counter every time programming verification fails;

a = cnt counter.

6. The method for accelerating NORFLASH programming speed as claimed in claim 5, further comprising:

acquiring programming times for successfully programming a plurality of programming addresses;

and adjusting the numerical value of the cnt counter according to the programming times of successfully programming the programming addresses.

7. The method of claim 6, wherein the step of adjusting the cnt counter according to the number of times of successful programming of the programming addresses comprises:

obtaining the variation of the programming times of the plurality of programming addresses successfully programmed according to the programming times of the plurality of programming addresses successfully programmed;

and adjusting the value of the cnt counter according to the variable quantity.

8. An apparatus for accelerating NORFLASH programming, comprising:

the first obtaining module is used for obtaining the programming times A required by successful programming in the programming process of the last programming address;

and the first processing module is used for carrying out programming verification when programming the A-th time in the programming process of the programming address at this time according to the programming times A and updating the A to be the programming times required by successful programming in the programming process of the programming address at this time.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method according to any one of claims 1 to 7.

Background

In the conventional NOR Flash programming, as shown in fig. 4, in order to determine whether a programmed cell reaches a threshold voltage, after each programming, a program check is performed on the programmed cell to determine whether the programmed cell has reached the threshold voltage, if the programmed cell has not reached the threshold voltage, the programming is continued, and after the programming, whether the programmed cell has reached the threshold voltage is continued until voltages of all cells to be programmed reach an expected threshold voltage, the programming check cannot be passed, and then the programming of a next address is performed.

The programming verification after each programming causes the flash programming time to be too long, and the flash programming power consumption is increased.

Improvements are needed to address the above issues.

Disclosure of Invention

Embodiments of the present application provide a method, an apparatus, and an electronic device for increasing a NOR FLASH programming speed, which have the advantages of reducing the number of redundant program verification operations in a conventional programming process and improving programming efficiency.

In a first aspect, an embodiment of the present application provides a method for accelerating a NORFLASH programming speed, where a technical scheme is as follows:

the method comprises the following steps:

acquiring programming times A required for successful programming in the programming process of the last programming address;

and according to the programming times A, performing programming verification when programming the A-th time in the programming process of the programming address at this time, and updating the A to be the programming times required by successful programming in the programming process of the programming address at this time.

Further, in the embodiment of the present application, the method further includes:

the programming voltage for the first programming in the programming process of the current programming address is kept the same as the programming voltage for the first programming in the programming process of the last programming address.

Further, in this embodiment of the present application, the step of obtaining the programming times a required for successfully programming in the process of programming the last programming address includes:

judging whether programming of a last programming address exists or not;

if yes, acquiring programming times A required by successful programming in the programming process of the last programming address;

if not, programming according to normal programming, programming verification, programming and programming verification.

Further, in this embodiment of the present application, if the program number a does not exist, the step of programming according to a normal programming, program verification, programming, program verification.

Setting a cnt counter, wherein the cnt counter = 1;

adding 1 to the cnt counter every time programming verification fails;

a = cnt counter.

Further, in this embodiment of the application, the step of updating a to the programming frequency required for successful programming in the programming process of the current programming address includes:

setting a cnt counter, wherein the cnt counter = programming times A required by successful programming in the programming process of the last programming address;

adding 1 to the cnt counter every time programming verification fails;

a = cnt counter.

Further, in the embodiment of the present application, the method further includes:

acquiring programming times for successfully programming a plurality of programming addresses;

and adjusting the numerical value of the cnt counter according to the programming times of successfully programming the programming addresses.

Further, in this embodiment of the present application, the step of adjusting the value of the cnt counter according to the number of times of successfully programming the plurality of programming addresses includes:

obtaining the variation of the programming times of the plurality of programming addresses successfully programmed according to the programming times of the plurality of programming addresses successfully programmed;

and adjusting the value of the cnt counter according to the variable quantity.

In a second aspect, the present application further provides an apparatus for increasing the norlay programming speed, including:

the first obtaining module is used for obtaining the programming times A required by successful programming in the programming process of the last programming address;

and the first processing module is used for carrying out programming verification when programming the A-th time in the programming process of the programming address at this time according to the programming times A and updating the A to be the programming times required by successful programming in the programming process of the programming address at this time.

In a third aspect, the present application further provides an electronic device, comprising a processor and a memory, where the memory stores computer readable instructions, and the computer readable instructions, when executed by the processor, perform the steps of the method as described above.

In a fourth aspect, the present application also provides a storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of the method as described above.

As can be seen from the above, the method, the apparatus, the electronic device and the storage medium for increasing the NOR FLASH programming speed provided by the embodiment of the present application obtain the number of program verification times required for successful programming in the previous address programming process; and then, programming verification is carried out after the programming of the programming verification times in the current address programming process according to the programming verification times, and the programming verification times required by the current address programming process are recorded, so that the redundant programming verification times in the traditional programming process are reduced, and the beneficial effect of improving the programming efficiency is achieved.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Fig. 1 is a flowchart of a method for increasing the norlay programming speed according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of an apparatus for increasing the norlay programming speed according to an embodiment of the present disclosure.

Fig. 3 is a schematic view of an electronic device according to an embodiment of the present application.

Fig. 4 is a flowchart of conventional programming.

In the figure: 210. a first acquisition module; 220. a first processing module; 300. an electronic device; 310. a processor; 320. a memory.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1 to 4, a method for increasing the NORFLASH programming speed specifically includes:

s110, acquiring programming times A required by successful programming in the programming process of the last programming address; the successful programming refers to that the voltage of a programming unit reaches a threshold voltage, and then through program verification, when a programming address is programmed, the threshold voltage is not always reached at one time, so that multiple times of programming are needed.

And S120, according to the programming times A, performing programming verification during the A-th programming in the programming process of the current programming address, and updating A to be the programming times required by successful programming in the programming process of the current programming address.

According to the technical scheme, the programming frequency A required by successful programming in the programming process of the previous programming address is used as a reference for the programming frequency of the current programming address, programming verification is started when the programming of the current programming address is performed for the A-th time, programming verification is not performed before the programming for the A-th time, programming verification is performed in each programming after the A-th time, and finally the programming frequency required by successful programming in the programming process of the current programming address is recorded. Compared with the traditional method that each programming must be accompanied by programming verification, the scheme of the application can effectively reduce redundant programming verification steps in the programming process, so that the programming time is shortened, and the more programming addresses are sent along with one complete programming instruction, the more verification times are saved, and the more obvious the effect of saving the programming time is.

For example, in some embodiments, in the programming process of the previous address, a total of 5 times of programming and 5 times of program verification are passed, then a equals 5, in the programming of the current program address, 5 times of programming are directly performed, then the 1 st time of program verification is performed in the 5 th time of programming, if the program verification passes, the next program address is programmed, if the program verification does not pass, the program address is continuously programmed, and program verification is performed in each of the 6 th time of programming and the 7 th time of programming until the program verification succeeds, for example, the program verification after the 10 th time of programming passes, then a is updated to 10, that is, when the next program address is programmed, the program verification is not performed when the 10 th time of programming is performed.

In other embodiments, a may not be updated, for example, if a is equal to 5 after a total of 5 times of programming and 5 times of program verification have passed in the programming process of the previous address, then 5 times of programming are directly performed in the programming of the current programming address, then the 1 st program verification is performed after the 5 th programming, and the program verification is still performed at the 5 th programming when the next programming address or even the subsequent programming address is programmed.

Further, in some of the embodiments, the method further comprises:

the programming voltage for the first programming in the programming process of the current programming address is kept the same as the programming voltage for the first programming in the programming process of the last programming address.

Through the technical scheme, the reason that the first programming voltage for each programming address is kept the same is to control variables, and the adjustment of the voltage and the reduction of the programming verification times are in two dimensions to improve the programming speed.

For example, when a first program address is programmed, the first program voltage is 1.5v, 2v is a threshold voltage, each program increases by 0.1v, and program verification is successful after 5 times of programming, when a second program address is programmed, if the first program voltage is 1.0v, 2v is a threshold voltage, each program increases by 0.1v, program verification is successful after 10 times of programming is required, and a is updated to 10, and if the holding voltages are the same, a is 5, so that if the first program voltage is not guaranteed to be the same, the subsequent program times are disordered.

Further, in some embodiments, the step of obtaining the programming times a required for successful programming in the programming process of the last programming address comprises:

judging whether programming of a last programming address exists or not;

if yes, acquiring programming times A required by successful programming in the programming process of the last programming address;

if not, programming according to normal programming, programming verification, programming and programming verification.

Through the technical scheme, if the first programming address is programmed, the last programming address does not exist, programming is performed according to a traditional programming mode, programming verification is performed once after each programming until the programming is successful, then the programming times A required by successful programming are recorded, and then the programming times A required by successful programming can be obtained in the programming process of the first programming address when the second programming address is programmed.

Further, in some embodiments, if the program is not present, the step of programming according to a normal programming, program checking, programming, program checking.

Setting a cnt counter, wherein the cnt counter = 1;

adding 1 to the cnt counter every time programming verification fails;

a = cnt counter.

Through the technical scheme, when the first programming address is programmed, the programming times are counted through the cnt counter. For example, if the 5 th program is successful, and there are 4 program verify failures, then a = cnt counter =1+1+1+ 1= 5.

Further, in some embodiments, the step of updating a to the programming number required for successful programming in the programming process of the current programming address includes:

setting a cnt counter, wherein the cnt counter = programming times A required by successful programming in the programming process of the last programming address;

adding 1 to the cnt counter after each programming verification failure;

a = cnt counter.

Through the technical scheme, when the programming address is programmed, the programming times are counted through the cnt counter. For example, when the first programming address is programmed, the 5 th programming is successful, and when the second programming address is programmed, the 7 th programming is successful, and the 2-time programming verification fails, the cnt counter = 5; cnt counter =5+1+1= 7; a = 7.

It is noted that, for a mature and stable process product, the fluctuation range of the threshold voltages of most program cells will be very small, i.e. the threshold voltages of the program cells are the same or similar, so that the scheme of the present application can effectively reduce the redundant program verify steps in the programming process, thereby shortening the programming time.

However, similarly, there may be a case where the difference in the threshold voltages of the program cells is large, and when the program cell having a large threshold voltage is at the previous program address, there may be a case where the number of program verifies is increased.

Further, in some of the embodiments, the method further comprises:

acquiring programming times for successfully programming a plurality of programming addresses;

the value of the cnt counter is adjusted according to the number of times of programming that was successfully performed for the plurality of program addresses.

Specifically, the variation of the programming times of the plurality of programming addresses for successful programming is obtained according to the programming times of the plurality of programming addresses for successful programming;

and adjusting the value of the cnt counter according to the variation.

For example, N program addresses with the same program times occur in succession, and the cnt counter is decremented by 1, and the threshold voltages of the program cells are the same or similar for a mature and stable process product, i.e., the cnt counter is decremented by 1 is corrected back quickly.

For example, when the programming frequency of the first programming address for successful programming is 10, the programming frequency of the second programming address for successful programming is 10, the programming frequency of the third programming address for successful programming is 10, and the programming frequency of the fourth programming address for successful programming is 10, the actual programming frequency of the second programming address, the actual programming frequency of the fourth programming address may be 10, or may be less than 10, and therefore the value of the cnt counter needs to be adjusted according to the programming frequency of the programming addresses for successful programming.

For example, when the programming times of multiple programming addresses are the same, the case of too high programming times may occur, at this time, the cnt counter may be decreased by 1 to adjust the value a, for example, the programming times of the first programming address, the second programming address, the third programming address, and the fourth programming address are all 10, 4 programming addresses with the same programming times continuously occur, the cnt counter may be decreased by 1, when the fifth programming address is programmed, the program verification may be performed at the 9 th programming time, and similarly, the same operation may be performed on subsequent programming addresses.

In some embodiments, it is assumed that ten program addresses are required to be programmed in sequence in one program instruction, and the ten program addresses are A₁~A₁₀To address A₁The programming is performed in the same flow as the conventional programming but requires the cnt counter to record the programming A₁The number of programming times required for successful programming, assuming cnt counter =5, represents a₁The number of programming passes required for successful programming is 5, program verify passes, and program A begins₂Directly to A₂Programming and verifying the cnt times, and if the verification fails, continuing to verify the A₂Programming, and verifying after programming until A₂The program verification passes, if the program verification passes, the program verification is carried out by A₂The programming flow of (A) is respectively₃~A₁₀Programming is performed.

For example, in a conventional programming flow, pair A₁~A₁₀Programming addresses require 5 times of programming and 5 times of program verification, which requires 50 times of programming time and 50 times of program verification time in total.

By the scheme provided by the application, the step A₁The number of programming is 5, the number of program verify is 5, for A₂~A₁₀The number of programming times of (2) is 9 × 5=45, for a₂~A₁₀Is 9 times, i.e., a total of 5+45=50 program times and 5+9=14 program verify times is required.

In summary, the conventional programming flow program A₁~A₁₀The programming and verifying time is required 50 times and 50 times, while the programming and verifying time is only required 50 times and 14 times, so that the programming and verifying times are greatly reduced, if more addresses are sent by one-time programming instructions, the more verifying times are saved, and the more the effect of saving the complete programming time isIs obvious.

In a second aspect, the present application further provides an apparatus for increasing the programming speed of a NOR FLASH, comprising:

a first obtaining module 210, configured to obtain a programming frequency a required for successfully programming in a programming process of a previous programming address;

the first processing module 220 is configured to perform program verification when programming the address of the current time for the programming a-th time in the programming process according to the programming frequency a, and update the programming frequency a to the programming frequency required for successful programming in the programming process of the programming address of the current time.

Through the above technical solution, the first obtaining module 210 uses the programming frequency a required for successfully programming in the programming process of the previous programming address as a reference for the programming frequency of the current programming address, in the programming of the current programming address, the first processing module 220 starts to perform the programming verification when performing the programming of the a-th time according to the programming frequency a, does not perform the programming verification before the programming of the a-th time, performs the programming verification for each programming after the a-th time, and finally records the programming frequency required for successfully programming in the programming process of the current programming address. Compared with the traditional method that each programming must be accompanied by programming verification, the scheme of the application can effectively reduce redundant programming verification steps in the programming process, so that the programming time is shortened, and the more programming addresses are sent along with one complete programming instruction, the more verification times are saved, and the more obvious effect of saving the programming time is

In a third aspect, the present application further provides an electronic device 300, comprising a processor 310 and a memory 320, wherein the memory 320 stores computer readable instructions, and the computer readable instructions, when executed by the processor 310, perform the steps of the method as described above.

By the above technical solution, the processor 310 and the memory 320 are interconnected and communicate with each other through a communication bus and/or other form of connection mechanism (not shown), and the memory 320 stores a computer program executable by the processor 310, and when the computing device runs, the processor 310 executes the computer program to execute the method in any optional implementation manner of the foregoing embodiment to implement the following functions: acquiring programming times A required for successful programming in the programming process of the last programming address; and according to the programming times A, performing programming verification when programming the A-th time in the programming process of the programming address at this time, and updating the programming times required by successful programming in the programming process of the programming address at this time to be A.

In a fourth aspect, the present application also provides a storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of the method as described above.

Through the technical scheme, when being executed by a processor, the computer program executes the method in any optional implementation manner of the embodiment to realize the following functions: acquiring programming times A required for successful programming in the programming process of the last programming address; and according to the programming times A, performing programming verification when programming the A-th time in the programming process of the programming address at this time, and updating the programming times required by successful programming in the programming process of the programming address at this time to be A.

The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.