1. A memory erase method, comprising:

acquiring voltage information in the process of executing an erasing operation and a weak programming operation;

determining whether the state machine jumps to a weak programming state according to the voltage information; the working states of the state machine at least comprise an idle state, a jump to a weak programming state and a jump to an end state.

2. The memory erasing method according to claim 1, wherein the voltage information at least includes information on whether the voltage fluctuates.

3. A memory erasing method according to claim 2, further comprising:

and when the state machine jumps to the weak programming state, the weak programming operation is executed again from the initial address of the erasing area.

4. A memory erasing method according to claim 1, further comprising:

acquiring an erasing instruction;

inspecting an erasing area according to the erasing instruction to obtain an inspection result;

and carrying out erasing operation or jumping to an end state according to the verification result.

5. The method of claim 4, wherein the verification result comprises that the erase region has memory cells in a programmed state and all of the memory cells in the erase region are in an erased state.

6. The method as claimed in claim 5, wherein the step of performing an erase operation or jumping to an end state according to the verification result comprises:

performing an erase operation if the verification result is that the erase region has memory cells in a programmed state;

and if the verification result is that all the storage units in the erasing area are in the erasing state, jumping to the ending state.

7. The method of claim 6, further comprising after the step of performing an erase operation if the verification result indicates that the erase region has memory cells in a programmed state:

performing a weak programming operation;

inspecting the erasing area to obtain a secondary inspection result;

and performing erasing operation or jumping to an end state according to the secondary inspection result.

8. A memory erasing apparatus, comprising:

the first acquisition module is used for acquiring voltage information in the processes of executing an erasing operation and a weak programming operation;

the first processing module is used for determining whether the state machine jumps to a weak programming state according to the voltage information; the working states of the state machine at least comprise an idle state, a jump to a weak programming state and a jump to an end state.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method according to any one of claims 1 to 7.

10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-7.

Background

In the NOR FLASH, the state of each memory cell may be divided into a program (program) state and an erase (erase) state according to the voltage value of the floating gate (floating gate), and the specific distribution is shown in fig. 4. During the erase operation of the chip, it is necessary to reduce the voltage value of the floating gate of the memory cell from a higher program to erase, as shown in fig. 5, but during this erase operation, the voltage value of the floating gate of some memory cells is reduced to 1V or even lower, which is called over-erase (over-erase). In the subsequent read operation, since the memory cells in the NOR FLASH are distributed as shown in fig. 6, the drains of one column of memory cells share one path in the vertical direction, which is called BL, and the gates of one row of memory cells share one path in the horizontal direction, which is called WL. In a read operation, a voltage of about 5.5V is applied to selected WL0, a voltage of 0.8V is applied to BL0, and the state of the memory cell is read by determining whether a current is present in BL 0.

However, for the unselected memory cell, since the drain is shared with the selected memory cell, a small voltage is applied to the drain, but since the floating gate has a low voltage, the memory cell is easily turned on, and a current is generated at BL0, which causes a read error in the read operation of the selected memory cell.

The current method is to add a weak programming operation (SSP) after each erase operation, i.e. to complete a program operation with a lower voltage, to raise the floating gate voltage of the memory cell with a voltage lower than the threshold, thereby avoiding the occurrence of errors in the subsequent read operation and the repair of the hidden troubles caused by over-erase. However, this method has certain limitations, and when the voltage fluctuation occurs in the chip, a signal is generated to interrupt the current operation, and if the voltage fluctuation occurs in the erase stage or the ssp stage of the erase operation, the over-erase cannot be repaired, which may cause the subsequent read operation to be in error.

In view of the above, a new memory erase scheme is needed.

Disclosure of Invention

Embodiments of the present disclosure provide a memory erasing method, a memory erasing device, an electronic device, and a storage medium, which have the advantage of reducing read errors in subsequent read operations caused by over-erasing.

In a first aspect, an embodiment of the present application provides a memory erasing method, which includes:

the method comprises the following steps:

acquiring voltage information in the process of executing an erasing operation and a weak programming operation;

determining whether the state machine jumps to a weak programming state according to the voltage information; the working states of the state machine at least comprise an idle state, a jump to a weak programming state and a jump to an end state.

Further, in the embodiment of the present application, the voltage information at least includes information whether the voltage fluctuates.

Further, in the embodiment of the present application, the method further includes:

and when the state machine jumps to the weak programming state, the weak programming operation is executed again from the initial address of the erasing area.

Further, in the embodiment of the present application, the method further includes:

acquiring an erasing instruction;

inspecting an erasing area according to the erasing instruction to obtain an inspection result;

and carrying out erasing operation or jumping to an end state according to the verification result.

Further, in the embodiment of the present application, the verification result includes that the erase region has memory cells in a programmed state, and all the memory cells of the erase region are in an erased state.

Further, in this embodiment of the present application, the step of performing an erase operation or jumping to an end state according to the verification result includes:

performing an erase operation if the verification result is that the erase region has memory cells in a programmed state;

and if the verification result is that all the storage units in the erasing area are in the erasing state, jumping to the ending state.

Further, in the embodiment of the present application, after the step of performing an erase operation if the verification result indicates that the erase region has a memory cell in a programmed state, the method further includes:

performing a weak programming operation;

inspecting the erasing area to obtain a secondary inspection result;

and performing erasing operation or jumping to an end state according to the secondary inspection result.

In a second aspect, the present application also provides a memory erasing apparatus, including:

the first acquisition module is used for acquiring voltage information in the processes of executing an erasing operation and a weak programming operation;

the first processing module is used for determining whether the state machine jumps to a weak programming state or not according to the voltage information; the working states of the state machine at least comprise an idle state, a jump to a weak programming state and a jump to an end state.

In a third aspect, the present application further provides an electronic device, which includes a processor and a memory, where the memory stores computer readable instructions, and when the computer readable instructions are executed by the processor, the steps in the method are executed.

In a fourth aspect, the present application also provides a storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of the method as described above.

As can be seen from the above, in the memory erasing method, the memory erasing device, the electronic device and the storage medium provided in the embodiments of the present application, the voltage information during the erasing operation and the weak programming operation is obtained; determining the working state of the state machine according to the voltage information; the working states of the state machine comprise an idle state, a jump to a weak programming state and a jump to an end state, and the method has the beneficial effect of reducing reading errors in subsequent reading operation caused by over-erasing.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Fig. 1 is a flowchart of a memory erasing method according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of a memory erasing apparatus according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

FIG. 4 is a schematic diagram of voltage distribution in a memory cell.

FIG. 5 is a voltage level diagram of a memory cell in an over-erased state after an erase operation.

FIG. 6 is a schematic diagram of the distribution of memory cells in NOR FLASH.

Fig. 7 is a flowchart of a memory erasing method according to an embodiment of the present disclosure.

In the figure: 210. a first acquisition module; 220. a first processing module; 300. an electronic device; 310. a processor; 320. a memory.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1 to 7, a memory erasing method includes:

s110, acquiring voltage information in the processes of executing an erasing operation and a weak programming operation; the voltage information at least comprises information whether the voltage fluctuates.

S120, determining whether the state machine jumps to a weak programming state or not according to the voltage information; the working states of the state machine at least comprise an idle state, a jump to a weakly programmed state and a jump to an end state.

According to the technical scheme, the working state of the state machine is determined according to voltage information, when voltage does not fluctuate, the state machine in the chip is in an idle state, at the moment, erasing operation is normally carried out, when voltage fluctuates, the state machine jumps to a weak programming state, weak programming operation is carried out once, and then the state machine jumps to an end state. In the scheme of the application, after the voltage fluctuation occurs, the state machine directly jumps to the weak programming state to repair the possibly existing memory cells in the over-erasing state, and then jumps to the ending state, so that the memory cells in the over-erasing state are repaired to the maximum extent, and errors are avoided during subsequent data reading.

Further, in some of the embodiments, the method further comprises:

when the state machine jumps to the weak programming state, the weak programming operation is executed again from the initial address of the erasing area.

Through the technical scheme, when voltage fluctuation occurs, the state machine jumps to weak programming, and performs weak programming once again from the initial address of the erasing area, so that the erasing area can be screened in a full coverage mode, and all storage units in an over-erasing state can be repaired as far as possible.

Further, in some of the embodiments, the method further comprises:

acquiring an erasing instruction;

inspecting the erasing area according to the erasing instruction to obtain an inspection result;

and performing erasing operation or jumping to an end state according to the verification result.

The verification result at least comprises memory cells in a programming state in an erasing area and all the memory cells in the erasing area in an erasing state.

Specifically, in some embodiments, if the verification result is that the erase region has a memory cell in a programmed state, an erase operation is performed;

specifically, in some other embodiments, if all the memory cells in the erase region are in the erase state as a result of the verification, the end state is jumped to.

Through the technical scheme, after an erasing instruction is received, the erasing area is checked firstly, if the memory cells in the programming state exist in the erasing area, the verifying is not passed, the erasing operation is required, if all the memory cells in the erasing area are in the erasing state, the verifying is passed, the erasing operation is not required, and therefore the user can directly jump to the ending state.

Further, in some embodiments, if the verification result is that the erase region has memory cells in a programmed state, the step of performing the erase operation further comprises:

performing a weak programming operation;

inspecting the erasing area to obtain a secondary inspection result;

and performing erasing operation or jumping to an end state according to the secondary verification result.

According to the technical scheme, after the erasing operation is carried out, the grid voltage of part of the storage units is lowered to cause the storage units to be in an over-erasing state, so that the weak programming operation needs to be carried out on the storage units subjected to the erasing operation, the programming operation is completed by using a low voltage, the grid voltage value of the storage units with the voltage lower than the threshold value is raised to avoid the storage units from being in the over-erasing state, due to the weak programming, the erasing area needs to be verified again, and the corresponding operation is executed according to the secondary verification result.

And when the memory cells in the programmed state exist in the erased area, the step of skipping to the erasing operation again is needed to carry out the erasing operation, then the weak programming operation is completed, the verification is carried out again, and the process is continuously repeated.

If all the memory cells in the erased area are in the erased state, the system can jump to the end state.

Specifically, referring to fig. 7, in some specific embodiments, after receiving an erase instruction, an erase region is verified, if a memory cell in a programmed state exists in the erase region, the verification fails, if all the memory cells in the erase region are in the erase state, the verification passes, the verification directly jumps to an end state, and if the verification fails, the verification jumps to an erase operation, after the erase operation is completed, in order to avoid an over-erase condition, a weak program operation needs to be performed on the region in which the erase operation is completed, since the weak program operation is completed, the erase region needs to be verified again, if a memory cell in a programmed state exists in the erase region, the verification fails, if all the memory cells in the erase region are in the erase state, the verification passes, if the verification passes, it jumps directly to the end state and if the verification fails, it enters the erase operation and loops through the above process.

In the process, voltage information in the process of executing the erasing operation and the weak programming operation is obtained, the voltage information at least comprises information whether the voltage fluctuates, if the voltage does not fluctuate, the steps are normally executed, if the voltage fluctuates, a state machine in the storage chip directly jumps to the step of the weak programming operation, weak programming is executed once again from the initial address of an erasing area, and the storage unit which is possibly in an over-erasing state is repaired.

In the conventional erasing method, after voltage fluctuation, the state machine directly enters an end state, however, even if the power is suddenly cut off, the whole circuit is not instantly powered off, a certain time interval exists in the process, the time interval is ignored in the conventional scheme at present, the time interval can complete a weak programming operation, and the possible memory cells in an over-erased state are repaired by re-executing a weak programming from the start address of an erasing area, so that the problem that in the conventional technical means, over-erasing cannot be repaired due to voltage fluctuation, and further subsequent reading errors occur can be effectively solved.

In a second aspect, the present application also provides a memory erasing apparatus, including:

a first obtaining module 210 for obtaining voltage information during performing an erase operation and a weak program operation; wherein the voltage information at least includes information whether the voltage fluctuates.

A first processing module 220, configured to determine whether the state machine jumps to a weak programming state according to the voltage information; the working states of the state machine at least comprise an idle state, a jump to a weakly programmed state and a jump to an end state.

Through the above technical solution, the voltage information during the erase operation and the weak program operation is acquired through the first acquisition module 210, the first processing module 220 then determines the operating state of the state machine according to the voltage information, when the voltage does not fluctuate, the state machine in the chip is in an idle state, at this time, the erasing operation is performed normally, when voltage fluctuation occurs, the state machine jumps to a weak programming state to carry out a weak programming operation, and then jumps to the end state, whereas in the conventional scheme, if a voltage fluctuation occurs, a signal is generated to interrupt the current operation, so that the state machine directly jumps to the end state, if the voltage fluctuation occurs in the erase phase or the weak program phase, the over-erase generated during the erase process cannot be repaired and directly enters the receiving state, and the over-erase is preserved, which may cause errors in the subsequent read operation. In the scheme of the application, after the voltage fluctuation occurs, the state can jump to the weak programming state, the possibly existing memory cell in the over-erasing state is repaired, and then the state jumps to the ending state, so that the memory cell in the over-erasing state is repaired to the maximum extent, and errors are avoided during subsequent data reading.

In a third aspect, the present application further provides an electronic device 300, which includes a processor 310 and a memory 320, where the memory 320 stores computer readable instructions, and the computer readable instructions, when executed by the processor 310, perform the steps in the method as described above.

By the above technical solution, the processor 310 and the memory 320 are interconnected and communicate with each other through a communication bus and/or other form of connection mechanism (not shown), and the memory 320 stores a computer program executable by the processor 310, and when the computing device runs, the processor 310 executes the computer program to execute the method in any optional implementation manner of the foregoing embodiment to implement the following functions: acquiring voltage information in the process of executing an erasing operation and a weak programming operation; determining the working state of the state machine according to the voltage information; the working states of the state machine at least comprise an idle state, a jump to a weakly programmed state and a jump to an end state.

In a fourth aspect, the present application also provides a storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of the method as described above.

Through the technical scheme, when being executed by a processor, the computer program executes the method in any optional implementation manner of the embodiment to realize the following functions: acquiring voltage information in the process of executing an erasing operation and a weak programming operation; determining the working state of the state machine according to the voltage information; the working states of the state machine at least comprise an idle state, a jump to a weakly programmed state and a jump to an end state.

The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.