1. A method for improving programming efficiency is characterized by comprising the following steps:

receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed;

reading the program data buffered in the at least one latch;

judging whether the bit number of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth or not, and obtaining a judgment result;

and executing programming operation on the address corresponding to the programming data in the chip according to the judgment result.

2. The method according to claim 1, wherein the step of performing a program operation on an address corresponding to the program data in the chip according to the determination result comprises the following steps: if the bit number of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth, dividing the programming data into a plurality of sections according to the bit number of the data needing to be programmed in the address corresponding to the programming data in the chip, and executing programming operation on the address corresponding to the programming data in the chip one by one according to the programming instruction and each section of programming data until all the addresses corresponding to the programming data in the chip are programmed, wherein the bit number of the data needing to be programmed in the address corresponding to each section of the programming data in the chip is not larger than the programming bandwidth; and if the bit number of data needing programming in the address corresponding to the programming data in the chip is not more than the programming bandwidth, executing one-time programming operation on the address corresponding to the programming data in the chip according to the programming instruction and the programming data, and completely programming the address corresponding to the programming data in the chip.

3. The method for improving programming efficiency according to claim 1, wherein the programming instruction comprises a programming operation instruction and an address to be programmed.

4. The method according to claim 1, wherein the data to be programmed is buffered by the following steps: and the data to be programmed are respectively cached in at least one data latch in the flash according to the data width.

5. The method for improving programming efficiency according to claim 1, further comprising the following steps after the data to be programmed is buffered: reading data of an address corresponding to the address of the programming instruction in the flash; and comparing the data of the address corresponding to the inside of the flash with the cached data needing programming, obtaining the bit number of the address needing programming corresponding to the address of the programming instruction in the flash according to the comparison, and recording the address needing programming in the flash.

6. The method for improving programming efficiency according to claim 1, further comprising the following steps after all the addresses corresponding to the programming data in the chip are programmed:

judging whether the data needing to be programmed is read completely,

if yes, ending the programming operation;

otherwise, jumping to the program data in the read cache again.

7. An apparatus for improving programming efficiency, comprising:

the receiving module is used for receiving a programming instruction and data needing to be programmed and caching the data needing to be programmed;

the reading module reads the programming data cached in the at least one latch;

the judging module is used for judging whether the number of bits of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth or not to obtain a judging result;

and the programming module executes programming operation on the address corresponding to the programming data in the chip according to the judgment result.

8. The apparatus for improving programming efficiency according to claim 7, wherein the determining module determines whether a number of bits of data to be programmed in an address corresponding to the programming data in the chip is greater than a programming bandwidth, and obtains and outputs a data segment index; and the segmented programming module or the single-time programming module segments the programming data according to the segmented index.

9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 6.

10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 6 by calling the computer program stored in the memory.

Background

As shown in FIG. 1, for the Nor flash programming process, a programming command and data are received, then the data are verified and the address required to be programmed is recorded, and then programming is performed.

To ensure programming efficiency, data of a multi-bit address is typically programmed at one time (referred to as programming bandwidth, i.e., the maximum number of data bits that a chip can perform per programming). As shown in fig. 1, the programming data is buffered in the data latch (the buffered data width is generally larger than the programming bandwidth), the Nor flash reads data with a programming bandwidth from the buffered data for programming each time, even if only 1-bit address in a programming bandwidth range needs to be programmed, the controller will perform the programming once according to the predetermined flow, for example, the buffered data width is 32-bit, the programming bandwidth is 8-bit, and the Nor flash reads data with 8-bit from the buffered data for programming each time, which needs to perform 4 times according to the predetermined flow. If only 1-bit address needs to be programmed in each programming bandwidth, but still needs to be executed once according to a given flow, the efficiency of programming is seriously affected, and the situation (namely, only 1-bit address needs to be programmed in each programming bandwidth) is easier to occur after the Nor flash is subjected to multiple program erasures.

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

The invention aims to provide a method, a device, a storage medium and a terminal for improving programming efficiency, and aims to solve the problem that the existing flash programming only programs address data of programming bandwidth each time and is low in programming efficiency.

The technical scheme of the invention is as follows: the technical scheme provides a method for improving programming efficiency, which specifically comprises the following steps:

receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed;

reading the program data buffered in the at least one latch;

judging whether the bit number of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth or not, and obtaining a judgment result;

and executing programming operation on the address corresponding to the programming data in the chip according to the judgment result.

In the technical scheme, the programming data cached in at least one latch is read each time, then whether the data bit number needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth or not is judged, and the corresponding address in the chip is programmed according to the judgment result; compared with the method of reading data with a programming bandwidth from the cached data every time for programming in the prior art, the method not only ensures the normal operation of chip programming, but also improves the programming efficiency.

Further, executing a programming operation on an address corresponding to the programming data in the chip according to the judgment result, specifically comprising the following processes: if the bit number of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth, dividing the programming data into a plurality of sections according to the bit number of the data needing to be programmed in the address corresponding to the programming data in the chip, and executing programming operation on the address corresponding to the programming data in the chip one by one according to the programming instruction and each section of programming data until all the addresses corresponding to the programming data in the chip are programmed, wherein the bit number of the data needing to be programmed in the address corresponding to each section of the programming data in the chip is not larger than the programming bandwidth; and if the bit number of data needing programming in the address corresponding to the programming data in the chip is not more than the programming bandwidth, executing one-time programming operation on the address corresponding to the programming data in the chip according to the programming instruction and the programming data, and completely programming the address corresponding to the programming data in the chip.

Further, the programming instruction comprises a programming operation instruction and an address needing to be programmed.

Further, the data to be programmed is cached, and the specific process is as follows: and the data to be programmed are respectively cached in at least one data latch in the flash according to the data width.

Further, after the data to be programmed is cached, the following process is also included: reading data of an address corresponding to the address of the programming instruction in the flash; and comparing the data of the address corresponding to the inside of the flash with the cached data needing programming, obtaining the bit number of the address needing programming corresponding to the address of the programming instruction in the flash according to the comparison, and recording the address needing programming in the flash.

Further, after all the addresses corresponding to the programming data in the chip are programmed, the method further includes the following steps:

judging whether the data needing to be programmed is read completely,

if yes, ending the programming operation;

otherwise, jumping to the program data in the read cache again.

This technical scheme still provides a device for improving programming efficiency, includes:

the receiving module is used for receiving a programming instruction and data needing to be programmed and caching the data needing to be programmed;

the reading module reads the programming data cached in the at least one latch;

the judging module is used for judging whether the number of bits of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth or not to obtain a judging result;

and the programming module executes programming operation on the address corresponding to the programming data in the chip according to the judgment result.

Further, the judging module judges whether the number of bits of data to be programmed in the address corresponding to the programming data in the chip is greater than the programming bandwidth, and obtains and outputs a data segment index; and the segmented programming module or the single-time programming module segments the programming data according to the segmented index.

The present invention also provides a storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute any one of the methods described above.

The technical solution also provides a terminal, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used for executing any one of the methods by calling the computer program stored in the memory.

As can be seen from the above, the programming data cached in the at least one latch is read each time, the number of data bits to be programmed in the address corresponding to the cached programming data read at one time in the chip is compared with the programming bandwidth, and if the number of the data bits to be programmed is smaller than the programming bandwidth, the address corresponding to the cached programming data read at one time in the chip is directly programmed at one time, regardless of whether the distribution of the addresses to be programmed in the cached data is concentrated or scattered, the whole programming time is greatly shortened, and the effect of improving the programming efficiency is obvious; if the number of data bits needing to be programmed is larger than the programming bandwidth, dividing the programming data into a plurality of sections according to the number of the data bits needing to be programmed in the corresponding address in the chip, and executing programming operation on the corresponding address in the chip one by one according to the programming instruction and each section of the programming data until all the addresses corresponding to the segmented programming data in the chip are programmed; because the programming capability of the chip is only limited by the bit number of the address actually required to be programmed when programming is executed each time, not the data bit number crossed when programming is executed each time, the chip can execute the programming as long as the bit number of the address actually required to be programmed when programming is executed each time is within the programming bandwidth, the normal operation of chip programming is ensured, and the programming efficiency is improved.

Drawings

FIG. 1 is a diagram illustrating a programming process of a Nor flash in the prior art.

FIG. 2 is a flowchart of the steps of a method of improving programming efficiency in the present invention.

FIG. 3 is a schematic diagram of an apparatus for improving programming efficiency according to the present invention.

Fig. 4 is a schematic diagram of a terminal in the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 2, a method for improving programming efficiency is applicable to Nor flash, and specifically includes the following steps:

s1: receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed.

Wherein the programming instruction comprises a programming operation instruction and an address needing to be programmed.

And the data to be programmed are respectively cached in at least one data latch in the flash according to the data width.

Wherein, for the data to be programmed buffered in the data latch, the following verification process is further included:

s 11: reading data of an address corresponding to the address of the programming instruction in the flash;

s 12: and comparing the data of the address corresponding to the inside of the flash with the cached data needing programming, obtaining the bit number of the address needing programming corresponding to the address of the programming instruction in the flash according to the comparison, and recording the address needing programming in the flash.

If the data of the address corresponding to the address of the programming instruction in the flash is 0, the address corresponding to the flash does not need to be programmed. If the data of the address corresponding to the address of the programming instruction in the flash is 1 and the data needing to be programmed is 0, the address corresponding to the flash in the flash needs to be programmed; if the data to be programmed is 1, the corresponding address in the flash does not need to be programmed.

S2: the program data buffered in the at least one latch is read.

Wherein the program data in at least one data latch in the flash is read each time. The data latches can generally buffer program data larger than the program bandwidth, for example, one data latch can buffer program data of 32 bits or 64 bits, and the program bandwidth is 8 bits.

S3: and judging whether the number of data bits needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth, if so, jumping to S4, and otherwise, jumping to S5.

In the programming data that one data latch can buffer, the number of data bits that need to be programmed may be larger than the programming bandwidth, or may be smaller than the programming bandwidth. For example, 32 bits of program data can be buffered in a data latch, but the number of data bits to be programmed in the buffered 32-bit program data is only 8 bits or less than 8 bits, or the number of data bits to be programmed in the buffered 32-bit program data is more than 8 bits.

S4: dividing the programming data into a plurality of sections according to the data bit number to be programmed in the corresponding address in the chip, and executing programming operation on the corresponding address in the chip one by one according to the programming instruction and each section of programming data until the address corresponding to the programming data in the chip is completely programmed, wherein the data bit number to be programmed in the address corresponding to each section of programming data in the chip is not more than the programming bandwidth;

when the data bit number required to be programmed of the programming data is larger than the programming bandwidth, the programming data is divided into a plurality of sections according to the data bit number required to be programmed, for example, in the 32-bit programming data, the data bit number required to be programmed is 16 bits, the 32-bit programming data is divided into 2 sections, each section of programming data comprises 8 bits of data bit number required to be programmed, the corresponding address in the chip is programmed according to the programming instruction and the first section of programming data, the corresponding address in the chip is programmed according to the programming instruction and the second section of programming data, and the programming operation is executed for two times; or in the 32-bit programming data, if the data bit number to be programmed is 12 bits, dividing the 32-bit programming data into 2 sections, wherein the first section of programming data comprises 8 bits of data bit number to be programmed, and the second section of programming data comprises 4 bits of data bit number to be programmed, programming the corresponding address in the chip according to the programming instruction and the first section of programming data, and then programming the corresponding address in the chip according to the programming instruction and the second section of programming data, and totally executing two programming operations; or in the 32-bit programming data, if the data bit number to be programmed is 26 bits, dividing the 32-bit programming data into 4 segments, wherein the first segment of programming data comprises 8-bit data bits to be programmed, the second segment of programming data comprises 8-bit data bits to be programmed, the third segment of programming data comprises 8-bit data bits to be programmed, the fourth segment of programming data comprises 2-bit data bits to be programmed, programming the corresponding address in the chip according to the programming instruction and the first segment of programming data, then programming the corresponding address in the chip according to the programming instruction and the second segment of programming data, programming the corresponding address in the chip according to the programming instruction and the third segment of programming data, and finally programming the corresponding address in the chip according to the programming instruction and the fourth segment of programming data to execute four programming operations; and so on.

S5: and executing one-time programming operation on the corresponding address in the chip according to the programming instruction and the programming data, so that all the addresses in the chip corresponding to the programming data are programmed.

In the prior art, only one piece of cache data with the length of the programming bandwidth is read each time, if the number of data bits to be programmed (no matter how many bits, even if only 1 bit of data bits needs to be programmed) exists in the cache data, the system performs one-time programming operation, which results in the cache data (i.e. cache data with the same length) stored in one data latch, the length of the programming time depends on the distribution of the data bits to be programmed, if the distribution of the data bits to be programmed is relatively concentrated (i.e. the data bits to be programmed are distributed in the same read programming bandwidth), the number of times of programming is small, the programming time is short, otherwise, if the distribution of the data bits to be programmed is dispersed, the system needs to strictly perform reading one piece of data with the programming bandwidth each time and programming the data bits to be programmed, resulting in a long programming time. In the technical scheme, the cache data in at least one latch is directly read each time, and as long as the number of data bits needing to be programmed in the cache data is less than the programming bandwidth, the system can finish the processing of the read cache data through one-time programming operation, regardless of whether the distribution of the number of data bits needing to be programmed in the cache data is concentrated or scattered, so that the whole programming time is greatly shortened, and the effect of improving the programming efficiency is obvious.

After the step S4 or S5, the following steps are further included:

s6: judging whether the data needing to be programmed is read completely, if so, jumping to S7, otherwise, jumping to S2;

s7: the programming operation is complete.

Because in actual operation, assuming that the number of data bits to be programmed in the 32-bit programming data is 12 bits, in the prior art, the 32-bit programming data is divided into 4 segments of read, which are respectively the 1 st segment, the 2 nd segment, the 3 rd segment and the 4 th segment, the number of data bits to be programmed in the address corresponding to the 1 st segment of programming data in the chip is 2 bits, the number of data bits to be programmed in the address corresponding to the 2 nd segment of programming data in the chip is 3 bits, the number of data bits to be programmed in the address corresponding to the 3 rd segment of programming data in the chip is 4 bits, the number of data bits to be programmed in the address corresponding to the 4 th segment of programming data in the chip is 3 bits, according to the conventional method (in order to avoid the number of data bits of the address actually to be programmed in each time of executing programming exceeding the programming bandwidth, the number of data bits spanned by each executing programming is strictly controlled to be 8 bits), for these 32 bits of programming data, 4 programming operations are required to complete. In the application, the 32-bit programming data is directly divided into 2 sections, the first section of programming data comprises 8-bit data bits needing to be programmed, the second section of programming data comprises 4-bit data bits needing to be programmed, the corresponding address in the chip is programmed according to the programming instruction and the first section of programming data, the corresponding address in the chip is programmed according to the programming instruction and the second section of programming data, and the programming operation is completed by executing two times of programming operation, so that the programming speed is greatly improved.

In the technical scheme, the programming data cached in at least one latch is read every time, the number of data bits needing to be programmed in the address corresponding to the cached programming data read once in the chip is compared with the programming bandwidth, if the number of the data bits needing to be programmed is smaller than the programming bandwidth, the address corresponding to the cached programming data read once in the chip is directly programmed once, and the distribution of the addresses needing to be programmed in the cached data is concentrated or scattered, so that the whole programming time is greatly shortened, and the effect of improving the programming efficiency is obvious; if the number of data bits needing to be programmed is larger than the programming bandwidth, dividing the programming data into a plurality of sections according to the number of the data bits needing to be programmed in the corresponding address in the chip, and executing programming operation on the corresponding address in the chip one by one according to the programming instruction and each section of the programming data until all the addresses corresponding to the segmented programming data in the chip are programmed; because the programming capability of the chip is only limited by the bit number of the address actually required to be programmed when programming is executed each time, not the data bit number crossed when programming is executed each time, the chip can execute the programming as long as the bit number of the address actually required to be programmed when programming is executed each time is within the programming bandwidth, the normal operation of chip programming is ensured, and the programming efficiency is improved.

As shown in fig. 3, an apparatus for improving programming efficiency includes:

the receiving module 101 is used for receiving a programming instruction and data needing to be programmed and caching the data needing to be programmed;

a reading module 102 for reading the program data buffered in the at least one latch;

the judging module 103 is used for judging whether the bit number of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth or not to obtain a judging result;

and the programming module 104 is used for executing programming operation on the address corresponding to the programming data in the chip according to the judgment result.

In this technical solution, the determining module 103 determines whether the number of bits of data to be programmed in the address corresponding to the programming data in the chip is greater than the programming bandwidth, and outputs a "completion flag" after the determination is completed, and the programming controller enables the determining module 103 to output the data segment index according to the "completion flag" and updates the "completion flag"; the segmented programming module 104 or the one-time programming module 105 segments the programming data according to the segmented index (the segmented programming module 104 segments the programming data into a plurality of segments according to the segmented index, and the one-time programming module 105 segments the programming data into 1 segment according to the segmented index), and then the segmented programming module 104 or the one-time programming module 105 performs a programming operation on the corresponding address in the chip according to the segmented programming data and the programming instruction (i.e. applies a programming voltage to the corresponding address in the chip to realize programming).

Referring to fig. 4, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.

In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed; reading the program data buffered in the at least one latch; judging whether the bit number of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth or not, and obtaining a judgment result; and executing programming operation on the address corresponding to the programming data in the chip according to the judgment result.

Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.

An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed; reading the program data buffered in the at least one latch; judging whether the bit number of data needing to be programmed in the address corresponding to the programming data in the chip is larger than the programming bandwidth or not, and obtaining a judgment result; and executing programming operation on the address corresponding to the programming data in the chip according to the judgment result. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.