1. A method for reducing programming power consumption is characterized by specifically comprising the following steps:

s1: receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed;

s2: acquiring data from the cached data to obtain actual programming data, wherein the length of the actual programming data is not more than the maximum programming length of the chip;

s3: and when the number of address bits needing to be programmed in the address corresponding to the actual programming data in the chip is matched with the maximum driving current capacity of the bit line charge pump in the chip, executing programming operation on the address corresponding to the actual programming data in the chip.

2. The method for reducing programming power consumption of claim 1, further comprising the following verification process for the cached data needing to be programmed:

s 11: reading data of an address corresponding to the address of the programming instruction in the core;

s 12: and comparing the data of the address corresponding to the chip with the cached data needing to be programmed, obtaining the bit number needing to be programmed of the address corresponding to the address of the programming instruction in the chip according to the comparison, and recording the address needing to be programmed in the chip.

3. The method of claim 1, wherein the maximum driving current capability of the on-chip bit line charge pump is a maximum number of programming current that the on-chip bit line charge pump can apply to memory cells of different addresses that are required to perform a programming operation during each programming pulse sent by the programming module.

4. The method for reducing programming power consumption of claim 1, wherein the maximum programming length of the chip is a maximum address length that the chip can span each time the chip performs a programming operation.

5. The method for reducing programming power consumption of claim 1, wherein the programming operation is performed on an address corresponding to the actual programming data in a chip by the following specific process: and sending a programming pulse through the programming module, wherein the bit line charge pump in the chip applies a programming current to the memory cell of the address corresponding to the actual programming data in the chip during the pulse, and the programming operation is executed.

6. The method of claim 5, wherein the on-chip bit line charge pump comprises at least 2bit line charge pump cells, and wherein the drive current capability of all bit line charge pump cells is equal to the maximum drive current capability of the bit line charge pump.

7. The method for reducing programming power consumption of claim 5, wherein the step of performing the programming operation on the address corresponding to the actual programming data in the chip comprises the following steps:

s 31: the programming module sends a programming pulse, and the bit line charge pump in the chip applies a programming current to a memory cell of an address corresponding to the actual programming data in the chip during the pulse to execute programming operation;

s 32: judging whether the memory cell of the address corresponding to the actual programming data in the chip is successfully programmed, if so, jumping to s33, otherwise, jumping to s 31;

s 33: judging whether the data needing to be programmed is read completely, if so, jumping to S34, otherwise, jumping to S2;

s 34: the programming operation is complete.

8. An apparatus for reducing programming power consumption, comprising:

the data receiving module is used for receiving a programming instruction and data needing to be programmed and caching the data needing to be programmed;

the data reading module is used for acquiring data from the cached data to obtain actual programming data, and the length of the actual programming data is not more than the maximum programming length of the chip;

and the programming module is used for executing programming operation on the address corresponding to the actual programming data in the chip when the number of address bits needing programming in the address corresponding to the actual programming data in the chip is matched with the maximum driving current capacity of the bit line charge pump in the chip.

9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 7.

10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 7 by calling the computer program stored in the memory.

Background

The conventional programming flow is shown in fig. 1:

(1) inputting a programming command and data to be programmed;

(2) reading data in an area with the length of 4bytes (4 bytes is equal to 32 bits) in an area needing programming operation in a chip each time, and checking whether data bits needing programming exist in the data in the area:

if the data bit needing to be programmed does not exist, the programming operation is not needed, and the following programming flow is skipped;

if the data bit needing to be programmed exists in the checked area, the programming operation is needed, and the step (3) is carried out;

(3) each time a programming pulse is sent for an area of 4bytes in length to be programmed, the programming operation is started according to the following sequence: sending a programming pulse-checking if programming is successful:

if successful, finishing the programming operation;

if not, continue sending programming pulses to the 4bytes long area- -check if programming is successful:

(4) this process is repeated until it is checked that all areas within the chip that need to be programmed are successfully programmed, ending the programming operation.

Fig. 2 shows a flash memory cell requiring a program operation, and fig. 3 shows a bit line charge pump commonly used in a circuit for supplying current to the memory cell to be programmed. When programming operation is carried out, the grid electrode of the memory cell in the flash is connected with the output of the word line charge pump, the drain electrode of the memory cell in the flash is connected with the output of the bit line charge pump, if all the memory cells in the region with the length of 4bytes need to be programmed, the bit line charge pump needs to be capable of providing current required by programming of all the memory cells, and therefore the bit line charge pump needs to be designed according to the maximum driving current capacity. However, for data in each 4bytes long region, the bit line charge pump does not need to provide the current required for programming all the memory cells at a time, and for data in some 4bytes long regions, if only a few memory cells (e.g., only a few bits (e.g., 1 bit, 2 bits, etc.) in 32 bits of data) need to be programmed, the bit line charge pump that meets the maximum current requirement is obviously over-designed (in practice, the bit line charge pump only needs to provide the programming current for a few memory cells that need to perform the programming operation, and the other redundant driving capability of the bit line charge pump is wasted). In addition, the output ripple and power consumption of the bit line charge pump with the maximum driving capability are also relatively large.

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

An object of the present invention is to provide a method, an apparatus, a storage medium, and a terminal for reducing programming power consumption, which are directed to solving one or more problems in the prior art.

The technical scheme of the invention is as follows: the technical scheme provides a method for reducing programming power consumption, which specifically comprises the following steps:

s1: receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed;

s2: acquiring data from the cached data to obtain actual programming data, wherein the length of the actual programming data is not more than the maximum programming length of the chip;

s3: and when the number of address bits needing to be programmed in the address corresponding to the actual programming data in the chip is matched with the maximum driving current capacity of the bit line charge pump in the chip, executing programming operation on the address corresponding to the actual programming data in the chip.

Further, for the cached data needing to be programmed, the following verification process is also included:

s 11: reading data of an address corresponding to the address of the programming instruction in the core;

s 12: and comparing the data of the address corresponding to the chip with the cached data needing to be programmed, obtaining the bit number needing to be programmed of the address corresponding to the address of the programming instruction in the chip according to the comparison, and recording the address needing to be programmed in the chip.

Further, the maximum driving current capability of the on-chip bit line charge pump refers to the maximum number of memory cells of different addresses, which need to perform a programming operation, in the on-chip bit line charge pump during a programming pulse sent by the programming module each time the programming pulse is sent.

Further, the maximum programming length of the chip refers to the maximum address length that the chip can span each time the chip performs a programming operation.

Further, a program operation is performed on an address corresponding to the actual program data in the chip, and the specific process is as follows: and sending a programming pulse through the programming module, wherein the bit line charge pump in the chip applies a programming current to the memory cell of the address corresponding to the actual programming data in the chip during the pulse, and the programming operation is executed.

Further, the on-chip bit line charge pump comprises at least 2bit line charge pump units, and the driving current capacity of all the bit line charge pump units is equal to the maximum driving current capacity of the bit line charge pump.

Further, the step of executing a programming operation on an address corresponding to the actual programming data in the chip specifically includes the steps of:

s 31: s 31: the programming module sends a programming pulse, and the bit line charge pump in the chip applies a programming current to a memory cell of an address corresponding to the actual programming data in the chip during the pulse to execute programming operation;

s 32: judging whether the memory cell of the address corresponding to the actual programming data in the chip is successfully programmed, if so, jumping to s33, otherwise, jumping to s 31;

s 33: judging whether the data needing to be programmed is read completely, if so, jumping to S34, otherwise, jumping to S2;

s 34: the programming operation is complete.

This technical scheme still provides a device for reducing programming power consumption, includes:

the data receiving module is used for receiving a programming instruction and data needing to be programmed and caching the data needing to be programmed;

the data reading module is used for acquiring data from the cached data to obtain actual programming data, and the length of the actual programming data is not more than the maximum programming length of the chip;

and the programming module is used for executing programming operation on the address corresponding to the actual programming data in the chip when the number of address bits needing programming in the address corresponding to the actual programming data in the chip is matched with the maximum driving current capacity of the bit line charge pump in the chip.

The present invention also provides a storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute any one of the methods described above.

The technical solution also provides a terminal, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used for executing any one of the methods by calling the computer program stored in the memory.

As can be seen from the above, if the memory cell of the address corresponding to the programming data in the chip needs to be programmed, no matter how many bits the memory cell needs to be programmed, the programming module will send a programming pulse, and the bit line charge pump will need to start to provide the programming current in the pulse, which results in larger power consumption when the number of the memory cells needs to be programmed is small; in the technical scheme, after reading programming data with a certain length, the number of addresses needing to be programmed in the addresses corresponding to the programming data in the chip is judged, if the number of the addresses is enough, a programming module sends a programming pulse, and a bit line charge pump is started in the pulse to provide programming current; if the number of the addresses is not enough, reading the programming data with a certain length, and sending a programming pulse by the programming module until the number of the addresses needing to be programmed in the addresses corresponding to the read actual programming data in the chip is enough and the length of the read actual programming data is not more than the maximum programming length of the chip, and starting the bit line charge pump in the pulse to provide programming current, so that the power consumption of the bit line charge pump can be greatly reduced; and the bit line charge pump is divided into a plurality of bit line charge pump units with smaller driving current capability, and the number of the bit line charge pump units is controlled to be opened and closed according to the number of addresses required to be programmed each time, so that the output ripple is reduced and the energy consumption is further reduced.

Drawings

Fig. 1 is a programming flow diagram in the prior art.

FIG. 2 is a diagram of a flash memory cell requiring a program operation in the prior art.

FIG. 3 is a schematic diagram of a bit line charge pump used in a circuit of the prior art to provide current to a memory cell to be programmed.

FIG. 4 is a flow chart of steps of a method of reducing programming power consumption in the present invention.

FIG. 5 is a schematic diagram of an apparatus for reducing programming power consumption in the present invention.

Fig. 6 is a schematic diagram of a terminal in the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 4, a method for reducing programming power consumption is applied to a flash chip, and specifically includes the following steps:

s1: receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed.

Wherein the programming instruction comprises a programming operation instruction and an address needing to be programmed.

And the data to be programmed are respectively cached in at least one data latch in the flash according to the data width.

Wherein, for the data to be programmed buffered in the data latch, the following verification process is further included:

s 11: reading data of an address corresponding to the address of the programming instruction in the core;

s 12: and comparing the data of the address corresponding to the chip with the cached data needing to be programmed, obtaining the bit number needing to be programmed of the address corresponding to the address of the programming instruction in the chip according to the comparison, and recording the address needing to be programmed in the chip.

If the data of the address corresponding to the address of the programming instruction in the flash is 0, the address corresponding to the flash does not need to be programmed. If the data of the address corresponding to the address of the programming instruction in the flash is 1 and the data needing to be programmed is 0, the address corresponding to the flash in the flash needs to be programmed; if the data to be programmed is 1, the corresponding address in the flash does not need to be programmed.

S2: and acquiring data from the cached data to obtain actual programming data, wherein the length of the actual programming data is not more than the maximum programming length of the chip.

The maximum programming length of the chip refers to the maximum address length that the chip can span each time the chip performs a programming operation, and is generally 256bytes (1 byte is equal to 8 bits).

S3: and when the number of address bits needing to be programmed in the address corresponding to the actual programming data in the chip is matched with the maximum driving current capacity of the bit line charge pump in the chip, executing programming operation on the address corresponding to the actual programming data in the chip.

Wherein, the S3 specifically includes the following processes: and judging whether the address bit number needing programming in the address corresponding to the actual programming data in the chip corresponds to the maximum driving current capability of the bit line charge pump in the chip, if so, executing programming operation on the address corresponding to the actual programming data in the chip, and otherwise, jumping to S2.

The maximum driving current capability of the on-chip bit line charge pump refers to the maximum number of programming currents which can be applied by the on-chip bit line charge pump to memory cells of different addresses which need to execute programming operation in the chip during a programming pulse sent by the programming module every time. According to different requirements (considering different areas, driving capacities and the like), the maximum driving current capacity of the in-chip bit line charge pump can be as follows: each time the programming module sends a programming pulse, the bit line charge pump in the chip can apply programming current to the memory cells of 8bit (8 bit) memory cells in the chip which need to execute programming operation in the pulse period; or the programming module sends a programming pulse every time, the on-chip bit line charge pump can apply a programming current to the 32-bit (32 bit) memory cell in the chip during the pulse.

For example, each time 32 bits of programming data are read from the buffered programming data, whether the number of address bits to be programmed in the address corresponding to the 32 bits of programming data in the chip reaches 32 bits is judged, if the number of address bits reaches 32 bits, the programming module sends a programming pulse, and controls the bit line charge pump in the chip to apply a programming current to the memory cell of the address corresponding to the 32 bits of programming data in the chip during the pulse period so as to execute the programming operation; if the length of the read actual programming data (namely the actual programming data added after the 32-bit programming data are read for multiple times) is judged whether to be equal to 256bytes (at the moment, the number of the address bits needing to be programmed in the address corresponding to the read actual programming data in the chip is less than 32 bits), if so, the programming module sends a programming pulse, and a bit line charge pump in the chip is controlled to apply programming current to a storage unit of the address needing to be programmed in the address corresponding to the read actual programming data in the chip during the pulse period, so that the programming operation is executed; if the read actual program data does not reach 256bytes, the 32-bit program data is continuously read from the buffered program data, and the process goes to S4 until the number of bits of the address to be programmed in the address corresponding to the read actual program data in the chip reaches 32 bits or the length of the read actual program data is equal to 256 bytes.

In S3, the programming module sends a programming pulse, and applies a programming current to the memory cell of the address corresponding to the actual programming data in the chip through the on-chip bit line charge pump to perform a programming operation.

Wherein, the S3 specifically includes the following steps:

s 31: the programming module sends a programming pulse, and the bit line charge pump in the chip applies a programming current to a memory cell of an address corresponding to the actual programming data in the chip during the pulse to execute programming operation;

s 32: judging whether the memory cell of the address corresponding to the actual programming data in the chip is successfully programmed, if so, jumping to s33, otherwise, jumping to s 31;

s 33: judging whether the data needing to be programmed is read completely, if so, jumping to S34, otherwise, jumping to S2;

s 34: the programming operation is complete.

The on-chip bit line charge pump comprises at least 2bit line charge pump units, the maximum driving current capacity of each bit line charge pump unit is set according to different requirements (according to different considerations of area, driving capacity and the like), and the maximum driving current capacities of the bit line charge pump units can be the same or different. By dividing a traditional large bit line charge pump with enough driving current capacity into a plurality of bit line charge pump units which are independent of each other, the driving current capacity of each bit line charge pump unit is weaker than that of the original large bit line charge pump, the number of the on-off of the bit line charge pump units can be controlled according to the number of the memory units which need to apply programming current when programming is executed each time, so that the output ripple (because the larger the driving current function of the bit line charge pump is, the larger the output ripple of the bit line charge pump is, and vice versa) and the power consumption of the bit line charge pump in a chip are reduced.

At s41, when the on-chip bit line charge pump applies the programming current to the memory cells at the address corresponding to the actual programming data during the first programming pulse, the bit line charge pump is activated to apply the programming current to the memory cells at the address corresponding to the actual programming data (because the number of the memory cells to be programmed in the chip is the largest, such as 32 bits), after the first programming pulse, the memory cells to be programmed in the chip may be programmed all the way or partially successfully, and partially not successfully, and then the second programming pulse is required to be sent to continue to control the application of the programming current to the memory cells which are not successfully programmed in the chip, and because the number of the memory cells which are not successfully programmed in the chip is reduced (not reached to 32 bits), some bit line charge pump cells may be selected to be activated (not all bit line charge pump cells are activated) according to the number of the memory cells which are not successfully programmed in the chip Pump unit), after each programming pulse is sent, the number of the bit line charge pump units which are started can be controlled according to the number of the storage units which are not successfully programmed in the chip until all the storage units which need to be programmed in the chip are successfully programmed. In the conventional technology, each time the programming data with the length corresponding to the maximum programming capability of the bit line charge pump is read, if the memory cell with the address corresponding to the programming data in the chip needs to be programmed, no matter how many bits the memory cell needs to be programmed, the bit line charge pump sends a programming pulse once, and when the number of the memory cells needing to be programmed is small, the power consumption is large; in the technical scheme, after reading programming data with a certain length, the number of addresses needing to be programmed in the addresses corresponding to the programming data in the chip is judged, if the number of the addresses is enough, a programming pulse is sent once, if the number of the addresses is not enough, the programming data with a certain length is read again, until the number of the addresses needing to be programmed in the addresses corresponding to the read actual programming data in the chip is enough, and the length of the read actual programming data is not more than the maximum programming length of the chip, the programming pulse is sent once, so that the power consumption of the bit line charge pump can be greatly reduced; and the bit line charge pump is divided into a plurality of bit line charge pump units with smaller driving current capability, and the number of the bit line charge pump units is controlled to be opened and closed according to the number of addresses required to be programmed each time, so that the output ripple is reduced and the energy consumption is further reduced.

As shown in fig. 5, an apparatus for reducing programming power consumption includes:

the data receiving module 101 is used for receiving a programming instruction and data needing to be programmed and caching the data needing to be programmed;

the data reading module 102 is used for acquiring data from the cached data to obtain actual programming data, wherein the length of the actual programming data is not more than the maximum programming length of the chip;

and the programming module 103 is used for executing programming operation on the address corresponding to the actual programming data in the chip when the number of address bits needing to be programmed in the address corresponding to the actual programming data in the chip is matched with the maximum driving current capability of the bit line charge pump in the chip.

Referring to fig. 6, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.

In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: s1: receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed; s2: acquiring data from the cached data to obtain actual programming data, wherein the length of the actual programming data is not more than the maximum programming length of the chip; s3: and when the number of address bits needing to be programmed in the address corresponding to the actual programming data in the chip is matched with the maximum driving current capacity of the bit line charge pump in the chip, executing programming operation on the address corresponding to the actual programming data in the chip.

Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.

An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: s1: receiving a programming instruction and data needing to be programmed, and caching the data needing to be programmed; s2: acquiring data from the cached data to obtain actual programming data, wherein the length of the actual programming data is not more than the maximum programming length of the chip; s3: and when the number of address bits needing to be programmed in the address corresponding to the actual programming data in the chip is matched with the maximum driving current capacity of the bit line charge pump in the chip, executing programming operation on the address corresponding to the actual programming data in the chip. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.