1. A memory device, comprising:

a memory cell array including a plurality of memory cells;

peripheral circuitry configured to program the plurality of memory cells to a plurality of programmed states; and

control logic configured to control the peripheral circuitry such that programming operations corresponding to the plurality of program states are performed,

wherein the control logic controls the peripheral circuitry such that during a programming operation for a target program state of the plurality of program states, memory cells to be programmed to an immediately higher program state than the target program state are programmed to the target program state.

2. The memory device of claim 1, wherein the peripheral circuitry programs memory cells of the plurality of memory cells to be programmed to the target program state and memory cells to be programmed to the immediately higher program state together to the target program state during the programming operation for the target program state.

3. The memory device of claim 2, wherein the peripheral circuitry programs memory cells to be programmed to a further higher program state than the immediately higher program state to a pre-programmed state during the program operation for the target program state.

4. The memory device of claim 3, wherein the pre-programmed state is a programmed state adjacent to and higher than the immediately higher programmed state.

5. The memory device of claim 3, wherein the peripheral circuitry performs a verify operation for the target program state and a verify operation for the pre-programmed state in sequence during the program operation for the target program state.

6. The memory device according to claim 1, wherein the peripheral circuit sequentially performs the program operations corresponding to the plurality of program states in order from a program operation corresponding to a program state in which a threshold voltage distribution is low.

7. A memory device, comprising:

a memory cell array including a plurality of memory cells;

peripheral circuitry configured to program the plurality of memory cells to a plurality of programmed states; and

control logic configured to control the peripheral circuitry such that programming operations corresponding to the plurality of program states are performed,

wherein the control logic controls the peripheral circuitry such that memory cells to be programmed to a higher program state than a target program state of the plurality of program states are programmed to a pre-programmed state during a program operation for the target program state.

8. The memory device of claim 7, wherein the pre-programmed state is a program state adjacent to and above the target program state.

9. The memory device of claim 7, wherein the peripheral circuitry programs, during the programming operation for the target program state, memory cells of the plurality of memory cells to be programmed to the target program state together with memory cells to be programmed to an immediately higher program state than the target program state to the target program state.

10. The memory device of claim 9, wherein the higher program state is a further higher program state of the plurality of program states than the immediately higher program state.

11. The memory device of claim 9, wherein the pre-programmed state is a programmed state adjacent to and higher than the immediately higher programmed state.

12. The memory device of claim 7, wherein the peripheral circuitry performs a verify operation for the target program state and a verify operation for the pre-programmed state in sequence during the program operation for the target program state.

13. The memory device according to claim 7, wherein the peripheral circuit sequentially performs the program operations corresponding to the plurality of program states in order from a program operation corresponding to a program state in which a threshold voltage distribution is low.

14. A method of operating a memory device, comprising:

programming a first memory cell of the plurality of memory cells to be programmed to a target program state; and

programming a second memory cell of the plurality of memory cells to be programmed to an immediately higher program state than the target program state to the target program state.

15. The method of claim 14, further comprising: programming a third memory cell of the plurality of memory cells to be programmed to a further higher program state than the immediately higher program state to a pre-programmed state.

16. The method of claim 15, wherein a first program verify operation corresponding to the first memory cell and the second memory cell and a second program verify operation corresponding to the third memory cell are performed sequentially.

17. The method of claim 14, wherein the first memory cell and the second memory cell are programmed together to the target program state.

18. A method of operating a memory device having first through third groups of M-level cells, the method of operation comprising:

programming each cell within the first group to have a kth program state; and

programming each cell within the second group to have the Kth program state and programming each cell within the third group to have a pre-programmed state while programming each cell within the first group,

wherein in 2^MIn a seed programmed state, each cell within the second group is to be programmed to have a higher programmed state than the first group,

wherein in said 2^MIn a seed program state, each cell within the third group is to be programmed to have a higher program state than the second group, and

wherein M and K are natural numbers and K is less than 2^M。

19. A method of operating a memory device having a first set and a second set of M-level cells, the method of operation comprising:

programming each cell within the first group to have a kth program state; and

programming each cell within the second group to have a pre-programmed state while programming each cell within the first group,

wherein in 2^MIn a seed program state, each cell within the second group is to be programmed to have a higher program state than the first group, and

wherein M and K are natural numbers and K is less than 2^M。

20. A method of operating a memory device having first through third groups of M-level cells, the method of operation comprising:

programming each cell within the first group to have a kth program state; and

programming each cell within the second group to have one of a first set of pre-programmed states and programming each cell within the third group to have one of a second set of pre-programmed states while programming each cell within the first group,

wherein in 2^MIn a seed programmed state, each cell within the second group is to be programmed to have a higher programmed state than the first group,

wherein in said 2^MIn a seed program state, each cell within the third group is to be programmed to have a higher program state than the second group, and

wherein M and K are natural numbers and K is less than 2^M。

21. A method of operating a memory device having first through fourth groups of M-level cells, the method of operation comprising:

programming each cell within the first group to have a kth program state; and

programming each cell within the second group to have the Kth program state, programming each cell within the third group to one of the pre-programmed states within the first group of pre-programmed states, and programming each cell within the fourth group to have one of the pre-programmed states within the second group of pre-programmed states while programming each cell within the first group,

wherein in 2^MIn a seed programmed state, each cell within the second group is to be programmed to have a higher programmed state than the first group,

wherein in said 2^MIn one programmed state, each cell within the third group is to be programmed to have a higher programmed state than the second group,

wherein in said 2^MIn a seed program state, each cell within the fourth group is to be programmed to have a higher program state than the third group, and

wherein M and K are natural numbers and K is less than 2^M。

Background

More recently, the paradigm of a computer environment has transitioned to ubiquitous computing, which enables computer systems to be used at any time and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has been rapidly increasing. Generally, such portable electronic devices use a memory system employing a memory device, in other words, use a data storage device. The data storage device is used as a primary or secondary memory device for the portable electronic device.

Data storage devices using memory devices provide advantages such as improved stability and durability, higher information access speed, and low power consumption due to the absence of mechanically driven parts. As examples of the memory system having such advantages, data storage devices include Universal Serial Bus (USB) memory devices, memory cards having various interfaces, and Solid State Drives (SSDs).

Memory devices can be classified as volatile memory devices and non-volatile memory devices.

Non-volatile memory devices have relatively low write and read speeds, but retain the data stored therein even when power is interrupted. Thus, the non-volatile memory device is used to store data to be retained regardless of whether power is supplied. Representative examples of non-volatile memory devices include Read Only Memory (ROM), mask ROM (mrom), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory, phase change random access memory (PRAM), magnetic ram (mram), resistive ram (rram), ferroelectric ram (fram), and the like. Flash memories are classified into NOR type and NAND type.

Disclosure of Invention

Various embodiments of the present disclosure relate to a memory device and a method of operating the memory device, which may improve a range of threshold voltage distributions of memory cells during a program operation of the memory device.

Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory cell array including a plurality of memory cells, peripheral circuitry configured to program the plurality of memory cells to a plurality of program states, and control logic configured to control the peripheral circuitry such that program operations corresponding to the plurality of program states are performed, wherein the control logic controls the peripheral circuitry such that during a program operation for a target program state of the plurality of program states, memory cells to be programmed to an immediately higher program state than the target program state are programmed to the target program state.

Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory cell array including a plurality of memory cells, peripheral circuitry configured to program the plurality of memory cells to a plurality of program states, and control logic configured to control the peripheral circuitry such that program operations corresponding to the plurality of program states are performed, wherein the control logic controls the peripheral circuitry such that during a program operation for a target program state of the plurality of program states, memory cells to be programmed to a higher program state than the target program state are programmed to a pre-programmed state.

Embodiments of the present disclosure may provide a method of operating a memory device. The method can comprise the following steps: programming a first memory cell of the plurality of memory cells to be programmed to a target program state; and programming a second memory cell of the plurality of memory cells to be programmed to an immediately higher program state than the target program state to the target program state.

Drawings

FIG. 1 is a schematic diagram illustrating a memory system according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram illustrating the memory device of FIG. 1.

FIG. 3 is a schematic diagram illustrating the memory block of FIG. 2.

Fig. 4 is a schematic diagram illustrating an example of a memory block having a 3D structure.

FIG. 5 is a threshold voltage distribution diagram used to describe the programmed state of a programmed memory cell.

FIG. 6 is a flow chart illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure.

Fig. 7 is a threshold voltage distribution diagram of a memory cell for describing a program operation for a first program state.

Fig. 8 is a threshold voltage distribution diagram of memory cells for describing a program operation for a second program state.

Fig. 9 is a schematic diagram for describing a programming mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Fig. 10 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Fig. 11 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Fig. 12 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Fig. 13 is a schematic diagram for describing a programming mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Fig. 14 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Fig. 15 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

FIG. 16 is a schematic diagram illustrating an embodiment of a memory system.

FIG. 17 is a schematic diagram illustrating an embodiment of a memory system.

FIG. 18 is a schematic diagram illustrating an embodiment of a memory system.

FIG. 19 is a schematic diagram illustrating an embodiment of a memory system.

Detailed Description

The specific structural or functional descriptions in the embodiments of the present disclosure that are incorporated in this specification or application are merely examples describing the embodiments of the present disclosure. Various embodiments of the present disclosure may be practiced in various forms and should not be construed as limited to the embodiments set forth in the specification or application.

Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, so that those skilled in the art can easily practice the technical spirit of the present disclosure.

FIG. 1 is a schematic diagram illustrating a memory system according to an embodiment.

Referring to fig. 1, a memory system 1000 may include a memory device 1100 to store data, and a memory controller 1200 to control the memory device 1100 under the control of a host 2000.

The host 2000 is capable of communicating with the memory system 1000 using an interface protocol, such as peripheral component interconnect-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), parallel ATA (PATA), or Serial Attached SCSI (SAS). In addition, the interface protocol between the host 2000 and the memory system 1000 is not limited to the above example, and may be one of various interface protocols, such as Universal Serial Bus (USB), Multi Media Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

The memory controller 1200 may control the overall operation of the memory system 1000 and may control data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 may program or read data by controlling the memory device 1100 in response to a request received from the host 2000. During a program operation, the memory controller 1200 may transmit a command CMD, an address ADD, and DATA to be programmed corresponding to the program operation to the memory device 1100. Further, during a read operation, the memory controller 1200 may receive DATA read from the memory device 1100, may temporarily store the DATA, and may transmit the temporarily stored DATA to the host 2000.

The memory device 1100 may perform a program operation, a read operation, or an erase operation under the control of the memory controller 1200.

In an embodiment, memory device 1100 may include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate fourth generation (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, Rambus DRAM (RDRAM), or flash memory.

During a program operation, the memory device 1100 according to an embodiment of the present disclosure may sequentially perform program operations corresponding to a plurality of program states. During a program operation for a target program state, the memory device 1100 may program memory cells to be programmed to an immediately higher program state than the target program state to the target program state, and may program memory cells to be programmed to a further higher program state to a pre-programmed state or a pre-state (pre-state). The pre-programmed state may be a program state adjacent to and higher than the target program state.

FIG. 2 is a schematic diagram illustrating the memory device of FIG. 1.

Referring to fig. 2, a memory device 1100 may include a memory cell array 100 storing data. The memory device 1100 may include a peripheral circuit 200, the peripheral circuit 200 being configured to perform a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The memory device 1100 may include control logic 300 that controls the peripheral circuitry 200 under the control of a memory controller (e.g., 1200 of fig. 1).

Memory cell array 100 may include a plurality of memory blocks MB1 through MBk 110 (where k is a positive integer). Local Line (LL) and bit lines (bit line) BL1 through BLm (where m is a positive integer) may be coupled to each of memory blocks MB1 through MBk 110. For example, the local line LL may include a first selection line, a second selection line, and a plurality of word lines (word lines) arranged between the first and second selection lines. Also, the local line LL may include dummy lines disposed between the first selection line and the word line and between the second selection line and the word line. Here, the first selection line may be a source selection line, and the second selection line may be a drain selection line. For example, the local lines LL may include word lines, drain and source selection lines, and source lines SL. For example, the local line LL may further include a dummy line. For example, the local line LL may further include a pipeline. The local line LL may be coupled to each of the memory blocks MB1 through MBk 110, and the bit lines BL1 through BLm may be coupled in common to the memory blocks MB1 through MBk 110. Memory blocks MB1 through MBk 110 may each be implemented in a two-dimensional (2D) or three-dimensional (3D) structure. For example, the memory cells in the memory block 110 having the 2D structure may be horizontally arranged on the substrate. For example, memory cells in the memory block 110 having a 3D structure may be vertically stacked on a substrate.

The peripheral circuit 200 may perform program, read, and erase operations on the selected memory block 110 under the control of the control logic 300. For example, the peripheral circuit 200 may include a voltage generation circuit 210, a row (row) decoder 220, a page buffer group 230, a column (column) decoder 240, an input/output circuit 250, a pass/fail (fail) check circuit 260, and a source line driver 270.

The voltage generation circuit 210 may generate various operation voltages Vop for program, read, and erase operations in response to the operation signal OP _ CMD. Further, the voltage generation circuit 210 may selectively discharge the local line LL in response to the operation signal OP _ CMD. For example, the voltage generation circuit 210 may generate various voltages such as a program voltage, a verify voltage, and a pass voltage (pass voltage) under the control of the control logic 300.

The row decoder 220 may transfer the operation voltage Vop to the local line LL coupled to the selected memory block 110 in response to the row decoder control signal AD _ signals. For example, during a program operation, in response to the row decoder control signal AD _ signals, the row decoder 220 may apply a program voltage generated by the voltage generation circuit 210 to a selected word line of the local lines LL and may apply a pass voltage generated by the voltage generation circuit 210 to the remaining word lines, i.e., unselected word lines.

The page buffer group 230 may include a plurality of page buffers PB1 to PBm 231 coupled to bit lines BL1 to BLm. The page buffers PB1 through PBm 231 may be operated in response to page buffer control signals PBSIGNALS. For example, during a program operation, the page buffers PB1 to PBm 231 may temporarily store data to be programmed, and the potential levels of the bit lines BL1 to BLm may be adjusted based on the temporarily stored data to be programmed. In addition, the page buffers PB1 to PBm 231 may sense voltages or currents of the bit lines BL1 to BLm during a read or program verify operation. The page buffers PB1 through PBm 231 may control the corresponding bit lines BL1 through BLm to a program mode or a program inhibit mode during a program operation. The threshold voltage of the memory cell coupled to the bit line in the program mode is increased due to a program voltage applied to a word line of the memory cell during the program operation, and the threshold voltage of the memory cell coupled to the bit line in the program inhibit mode is not increased even if the program voltage is applied to the word line of the memory cell during the program operation. For example, the page buffers PB1 to PBm 231 may control the potential levels of the bit lines BL1 to BLm to the level of a program-allowable voltage (e.g., a ground voltage) in the program mode, and may control the potential levels of the bit lines BL1 to BLm to a program-inhibited voltage (e.g., a power supply voltage) in the program-inhibited mode.

The column decoder 240 may transfer data between the input/output circuit 250 and the page buffer group 230 in response to a column address CADD. For example, the column decoder 240 may exchange data with the page buffer 231 through the data line DL, or may exchange data with the input/output circuit 250 through the column line CL.

The input/output circuit 250 may transmit a command CMD and an address ADD received from a memory controller (e.g., 1200 of fig. 1) to the control logic 300, or may exchange DATA with the column decoder 240. The input/output circuit 250 may transmit bad block (bad block) information BB _ info received from the control logic 300 to an external device (e.g., the memory controller 1200 of fig. 1).

During a read operation or a program verification operation, the PASS/FAIL check circuit 260 may generate a reference current in response to the enable BIT VRY _ BIT < # >, and may compare the sensing voltage VPB received from the page buffer group 230 with the reference voltage generated by the reference current and then output a PASS signal PASS or a FAIL signal FAIL. The sensing voltage VPB may be a voltage controlled based on the number of memory cells determined to have passed the program verify operation.

The source line driver 270 may be coupled to the memory cells included in the memory cell array 100 through the source lines SL, and may control a voltage to be applied to the source lines SL. The source line driver 270 may receive a source line control signal CTRL _ SL from the control logic 300, and may control a source line voltage to be applied to the source line SL in response to the source line control signal CTRL _ SL.

Control logic 300 may control peripheral circuit 200 by: the operation signal OP _ CMD, the row decoder control signal AD _ signals, the page buffer control signals PBSIGNALS, and the enable BIT VRY _ BIT < # > are output in response to the command CMD and the address ADD. The control logic 300 may control the peripheral circuit 200 such that program operations corresponding to a plurality of program states are sequentially performed during a program operation. Also, the control logic 300 may control the peripheral circuit 200 such that memory cells to be programmed to an immediately higher program state than the target program state are programmed to the target program state during a program operation for the target program state. Further, the control logic 300 may control the peripheral circuit 200 such that memory cells to be programmed to a further higher program state than the immediately higher program state are programmed to a pre-programmed state during a program operation for a target program state.

FIG. 3 is a schematic diagram illustrating the memory block of FIG. 2.

Referring to fig. 3, a plurality of word lines arranged parallel to each other between a first selection line and a second selection line may be coupled to the memory block 110. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. In an embodiment, the memory block 110 may include a plurality of strings ST coupled between bit lines BL 1-BLm and source lines SL. The bit lines BL1 through BLm may be respectively coupled to the strings ST, and the source lines SL may be commonly coupled to the strings ST. The strings ST may be equally configured, and thus, the string ST coupled to the first bit line BL1 will be described in detail by way of example.

The string ST may include a source select transistor SST, a plurality of memory cells F1 to F16, and a drain select transistor DST coupled in series to each other between a source line SL and a first bit line BL 1. A single string ST may include at least one source select transistor SST and at least one drain select transistor DST, and more memory cells than the memory cells F1 through F16 illustrated in the drawings may be included in the string ST.

A source of the source selection transistor SST may be coupled to a source line SL, and a drain of the drain selection transistor DST may be coupled to a first bit line BL 1. The memory cells F1 through F16 may be coupled in series between a source select transistor SST and a drain select transistor DST. The gates of the source select transistors SST included in the different strings ST may be coupled to a source select line SSL, the gates of the drain select transistors DST included in the different strings ST may be coupled to a drain select line DSL, and the gates of the memory cells F1 to F16 may be coupled to a plurality of word lines WL1 to WL16, respectively. A group of memory cells coupled to the same word line among memory cells included in different strings ST may be referred to as a 'Physical Page (PPG)'. Accordingly, the memory block 110 may include a plurality of physical pages PPG as many as the number of word lines WL1 to WL 16.

Fig. 4 is a schematic diagram illustrating an example of a memory block having a 3D structure.

Referring to fig. 4, the memory cell array 100 may include a plurality of memory blocks MB1 through MBk 110. Each memory block 110 may include a plurality of strings ST 11-ST 1m and ST 21-ST 2 m. In an embodiment, each of the strings ST11 to ST1m and ST21 to ST2m may be formed in an 'I' shape or a 'U' shape. In the first memory block MB1, the m strings may be arranged along the row direction (e.g., X direction). Although two strings are illustrated as being arranged in the column direction (e.g., Y direction) in fig. 4, this embodiment is given for convenience of description, and three or more strings may be arranged in the column direction (e.g., Y direction) in other embodiments.

Each of the strings ST11 to ST1m and ST21 to ST2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

The source select transistor SST of each string may be coupled between a source line SL and the memory cells MC1 through MCn. The source select transistors of strings arranged in the same row may be coupled to the same source select line. The source select transistors of the strings ST11 to ST1m arranged in the first row may be coupled to a first source select line SSL 1. The source select transistors of the strings ST21 to ST2m arranged in the second row may be coupled to a second source select line SSL 2. In other embodiments, the source select transistors of the strings ST 11-ST 1m and ST 21-ST 2m may be commonly coupled to a single source select line.

The first to nth memory cells MC1 to MCn in each string may be coupled in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first to nth memory cells MC1 to MCn may be coupled to the first to nth word lines WL1 to WLn, respectively.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a virtual memory cell. When the dummy memory cell is provided, a voltage or a current of a corresponding string may be stably controlled. Accordingly, the reliability of the data stored in the memory block 110 can be improved.

The drain select transistor DST of each string may be coupled between the corresponding bit line and the memory cells MC1 through MCn. The drain select transistors DST of the strings arranged along the row direction may be coupled to a drain select line extending along the row direction. The drain select transistors DST of the strings ST 11-ST 1m in the first row may be coupled to a first drain select line DSL 1. The drain select transistors DST of the strings ST21 to ST2m in the second row may be coupled to a second drain select line DSL 2.

FIG. 5 is a threshold voltage distribution diagram used to describe the programmed state of a programmed memory cell.

In an embodiment of the present disclosure, a description will be made based on a three-level cell (TLC) programming scheme in which the number of threshold voltage distributions of the memory cells is eight (e.g., PV0 to PV7) by way of example.

Referring to fig. 5, during a program operation, each memory cell may be programmed to an erased state PV0 and any one of a plurality of program states PV1 through PV 7. Before performing the program operation, the memory cells included in the memory block may have a threshold voltage corresponding to the erased state PV 0.

During a program operation, a program operation may be sequentially performed on the memory cells in the erase state PV0 in order from a program state having a low threshold voltage distribution among the plurality of program states PV1 to PV 7. For example, a program operation for the first program state PV1, a program operation for the second program state PV2, and a program operation for the third program state PV3, · a program operation for the seventh program state PV7 may be performed sequentially.

During a program operation, a selected program state is defined as a target program state, and a program state adjacent to and higher than the target program state is defined as a pre-program state.

For example, during a program operation for the first program state PV1, the target program state may be the first program state PV1 and the pre-programmed state may be the second program state PV 2.

FIG. 6 is a flow chart illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure.

A method of operating a memory device according to an embodiment of the present disclosure will be described with reference to fig. 1 to 6.

When a request corresponding to a program operation is received from the host 2000, the memory controller 1200 may generate a program command CMD in response to the request from the host 2000. The memory device 1100 may receive a program command CMD, an address ADD, and DATA to be programmed from the memory controller 1200 in operation S610.

The memory device 1100 may select a memory block (e.g., MB1) on which a program operation is to be performed from among the plurality of memory blocks MB1 through MBk in response to the received program command CMD and the address ADD, program the selected memory block (e.g., MB1) on a page basis in order, and perform the program operation for a first program state PV1 having a lowest threshold voltage distribution among the plurality of program states PV1 through PV7 using an incremental step pulse (ISPP) programming (ISPP) scheme during the program operation for the selected page in operation S620.

The page buffer group 230 may temporarily store data to be programmed in response to the page buffer control signals PBSIGNALS generated by the control logic 300, and may adjust the potential levels of the bit lines BL1 to BLm based on the temporarily stored data to be programmed. For example, a program permission voltage may be applied to a bit line corresponding to a page buffer in which a plurality of pieces of data corresponding to the first to seventh program states PV1 to PV7 are temporarily stored, and a program inhibition voltage may be applied to a bit line corresponding to a page buffer in which a plurality of pieces of data corresponding to the erase state PV0 are temporarily stored.

The voltage generation circuit 210 may generate a program voltage and a pass voltage in response to the operation signal OP _ CMD. The row decoder 220 may apply the program voltage generated by the voltage generation circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to the row decoder control signal AD _ signals, and may apply the pass voltage generated by the voltage generation circuit 20 to the remaining word lines.

Thereafter, the peripheral circuit 200 may check whether the memory cells to be programmed to the first program state PV1 have been normally programmed by performing a program verify operation for the first program state PV1 in operation S630. In this case, the peripheral circuit 200 may check whether the memory cells to be programmed to the immediately higher program state PV2 than the first program state PV1 have been programmed to the first program state PV1, and may check the memory cells that have been programmed to the immediately higher program state PV2 among the memory cells to be programmed to the further higher program states PV3 to PV 7.

For example, the peripheral circuit 200 may sequentially perform a program verify operation for the first program state PV1 and a program verify operation for a pre-programmed state, which are operations of verifying memory cells to be programmed to further higher program states PV3 to PV 7.

During a program verify operation for the first program state PV1, the voltage generation circuit 210 may generate a first verify voltage and a pass voltage corresponding to the first program state PV1 in response to the operation signal OP _ CMD. The row decoder 220 may apply the first verification voltage generated by the voltage generation circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to the row decoder control signal AD _ signals, and may apply the pass voltage generated by the voltage generation circuit 20 to the remaining word lines. Further, during the program verify operation, the page buffers PB1 to PBm 231 may sense voltages or currents of the bit lines BL1 to BLm, and then may check whether memory cells to be programmed to the first program state PV1 and memory cells to be programmed to the second program state PV2 corresponding to an immediately higher program state have been programmed to the first program state PV 1.

During a program verify operation for a pre-programmed state, the voltage generation circuit 210 may generate a second verify voltage and a pass voltage corresponding to an immediately higher program state PV2 in response to the operation signal OP _ CMD. The row decoder 220 may apply the second verification voltage generated by the voltage generation circuit 210 to a word line corresponding to the selected page among a plurality of word lines of the selected memory block (e.g., MB1) in response to the row decoder control signal AD _ signals, and may apply the pass voltage generated by the voltage generation circuit 20 to the remaining word lines. Further, during the program verify operation, the page buffers PB1 to PBm 231 may sense voltages or currents of the bit lines BL1 to BLm and then check memory cells to be programmed to the third to seventh program states PV3 to PV7 that have been programmed to the immediately higher program state PV 2.

In the above-described operation S630, when the threshold voltages of some of the memory cells to be programmed to the first program state PV1 have not reached the first program state PV1, or when the threshold voltages of some of the memory cells to be programmed to the second program state PV2 have not reached the first program state PV1 (fail), the control logic 300 may reset the program voltages by increasing the program voltages by step voltages in operation S640, and may re-perform the operation from the above-described operation S620. When operation S620 is re-performed, a program-inhibit voltage may be applied to a bit line corresponding to a memory cell determined to have passed the program-verify operation for the first program state PV1 and the program-verify operation for the pre-program state among the bit lines BL1 through BLm. Also, a program permission voltage may be applied to a bit line corresponding to a memory cell determined as having failed a program verify operation for the first program state PV1 and a program verify operation for a pre-program state among the bit lines BL1 to BLm.

In the above operation S630, when the threshold voltages of the memory cells to be programmed to the first and second program states PV1 and PV2 have reached the first program state PV1 (pass), the control logic 300 may determine whether the program operation currently being performed is a program operation for the last program state PV7 in operation S650.

When it is determined in operation S650 that the program operation currently being performed is not the program operation for the last program state PV7 (in the case of no), the program operation for the immediately higher program state is performed in operation S660. For example, when the above program operation is a program operation for the first program state PV1, a program operation for the second program state PV2 may be performed.

The page buffer group 230 may adjust the potential levels of the bit lines BLl through BLm based on data to be programmed, which is temporarily stored in response to the page buffer control signals PBSIGNALS generated by the control logic 300. For example, a program permission voltage may be applied to bit lines corresponding to page buffers temporarily storing a plurality of pieces of data corresponding to the second to seventh program states PV2 to PV7, and a program inhibition voltage may be applied to bit lines corresponding to page buffers temporarily storing a plurality of pieces of data corresponding to the erase state PV0 and the first program state PV 1.

The voltage generation circuit 210 may generate a program voltage and a pass voltage in response to the operation signal OP _ CMD. The row decoder 220 may apply the program voltage generated by the voltage generation circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to the row decoder control signal AD _ signals, and may apply the pass voltage generated by the voltage generation circuit 20 to the remaining word lines.

Thereafter, the peripheral circuit 200 may check whether the memory cells to be programmed to the second program state PV2 have been normally programmed by performing a program verify operation for the second program state PV2 in operation S670. In this case, the peripheral circuit 200 may check whether the memory cells to be programmed to the immediately higher program state PV3 than the second program state PV2 have been programmed to the second program state PV2, and may check the memory cells that have been programmed to the immediately higher program state PV3 among the memory cells to be programmed to the further higher program states PV4 to PV 7. For example, the peripheral circuit 200 may sequentially perform a program verify operation for the second program state PV2 and a program verify operation for a pre-programmed state, which are verify operations for further higher program states PV4 to PV 7.

During a program verify operation for the second program state PV2, the voltage generation circuit 210 may generate a second verify voltage and a pass voltage corresponding to the second program state PV2 in response to the operation signal OP _ CMD. The row decoder 220 may apply the second verification voltage generated by the voltage generation circuit 210 to a word line corresponding to the selected page among a plurality of word lines of the selected memory block (e.g., MB1) in response to the row decoder control signal AD _ signals, and may apply the pass voltage generated by the voltage generation circuit 20 to the remaining word lines. Further, during the program verify operation, the page buffers PB1 to PBm 231 may sense the voltages or currents of the bit lines BL1 to BLm and then check whether the memory cells to be programmed to the second program state PV2 and the memory cells to be programmed to the immediately higher program state PV3 have been programmed to the second program state PV 2.

During a program verify operation for a pre-programmed state, the voltage generation circuit 210 may generate a third verify voltage and a pass voltage corresponding to an immediately higher program state PV3 in response to the operation signal OP _ CMD. The row decoder 220 may apply the third verification voltage generated by the voltage generation circuit 210 to a word line corresponding to the selected page among a plurality of word lines of the selected memory block (e.g., MB1) in response to the row decoder control signal AD _ signals, and may apply the pass voltage generated by the voltage generation circuit 20 to the remaining word lines. Further, during the program verify operation, the page buffers PB1 to PBm 231 may sense voltages or currents of the bit lines BL1 to BLm and then check memory cells to be programmed to the fourth to seventh program states PV4 to PV7 that have been programmed to the program state PV 3.

When the threshold voltages of some of the memory cells to be programmed to the second program state PV2 and the memory cells to be programmed to the immediately higher program state PV3 have not reached the second program state PV2 (fail) in the above-described operation S670, the control logic 300 may reset the program voltage by increasing the program voltage by a step voltage in operation S680 and may re-perform the operation starting from operation S660. When operation S660 is re-performed, a program-inhibit voltage may be applied to bit lines corresponding to memory cells determined to have passed the program-verify operation for the second program state PV2 and the program-verify operation for the pre-program state, among the bit lines BL1 through BLm. Also, a program permission voltage may be applied to bit lines corresponding to memory cells determined to have failed the program verify operation for the second program state PV2 and the program verify operation for the pre-program state among the bit lines BL1 to BLm.

In the above-described operation S670, when the threshold voltage of the memory cell to be programmed to the second program state PV2 has reached the second program state PV2 and the threshold voltage of the memory cell to be programmed to the immediately higher program state PV3 has reached the second program state PV2 (pass), the control logic 300 may re-perform the operation starting from operation S650 of determining whether the program operation currently being performed is a program operation for the last program state PV 7.

The aforementioned operations S650 to S680 may be repeated until it is determined in the aforementioned operation S650 that the program operation currently being performed is the last program state PV 7. That is, the program operations for the second to seventh program states PV2 to PV7 may be completed by repeating the aforementioned operations S650 to S680. Here, during the program operation for the last program state PV7, the program operation for the pre-programmed state and the verify operation for the pre-programmed state are not performed.

When it is determined in operation S650 that the program operation currently being performed is a program operation for the last program state PV7, the aforementioned operations S620 to S680 may be performed by selecting the next page of the selected memory block.

Fig. 7 is a threshold voltage distribution diagram of a memory cell for describing a program operation for a first program state.

The threshold voltage distributions of the memory cells during the program operation for the first program state PV1 will be described below with reference to fig. 7.

Referring to fig. 7, during a program operation for the first program state PV1, a target memory cell (target MC) including a memory cell to be programmed to the first program state PV1 and a memory cell to be programmed to an immediately higher program state PV2 than the first program state PV1 may be programmed to have a threshold voltage distribution corresponding to the first program state PV 1. For example, during a program voltage applying operation, a threshold voltage distribution may be increased by applying a program voltage to a word line of a target memory cell (target MC). During a program verify operation, after a first verify voltage Vver1 has been applied to a word line of a target memory cell (target MC), a potential level of a bit line may be sensed, and thus it may be determined whether the program verify operation has passed/failed. When it is determined that the program verify operation has failed due to the program verify operation, the program operation may be performed in such a manner that the program voltage increased by the step voltage is re-applied to the word line of the target memory cell (target MC). As a result, the target memory cell (target MC) may have a threshold voltage distribution corresponding to the first program state PV1, which is higher than the first verify voltage Vver 1.

During the program operation for the first program state PV1, the remaining memory cells (i.e., other MCs) intended to be programmed to the third through seventh program states PV3 through PV7 may be programmed to a pre-programmed state (i.e., a pre-state). The pre-programmed state (pre-state) may be a state in which the threshold voltage distribution is higher than that in the first programmed state PV 1. For example, until the above-described target memory cell (target MC) passes the program verify operation, the program operation may not be performed on the remaining memory cells (other MCs), and the memory cells having the threshold voltage distribution higher than the second verify voltage Vver2 corresponding to the immediately higher program state PV2 among the remaining memory cells (other MCs) may be operated in the program inhibit mode. As a result, while the target memory cell (target MC) is programmed to the first program state PV1, the remaining memory cells (other MCs) may be programmed to a pre-programmed state (pre-state) having a higher threshold voltage distribution than in the first program state PV 1.

Fig. 8 is a threshold voltage distribution diagram of memory cells for describing a program operation for a second program state.

The threshold voltage distributions of the memory cells during the program operation for the second program state PV2 will be described below with reference to fig. 8.

Similar to fig. 7 described above, after the program operation for the first program state PV1 is completed, the program operation for the second program state PV2 is performed.

Referring to fig. 8, during a program operation for the second program state PV2, a target memory cell (target MC) including a memory cell to be programmed to the second program state PV2 and a memory cell to be programmed to an immediately higher program state PV3 may be programmed to have a threshold voltage distribution corresponding to the second program state PV 2. For example, during a program voltage applying operation, a threshold voltage distribution may be increased by applying a program voltage to a word line of a target memory cell (target MC). During a program verify operation, after the second verify voltage Vver2 has been applied to the word line of a target memory cell (target MC), the potential level of the bit line may be sensed, and thus it may be determined whether the program verify operation passes/fails. When it is determined that the program verifying operation fails due to the program verifying operation, the program operation may be performed in such a manner that the program voltage increased by the step voltage is re-applied to the word line of the target memory cell (target MC). As a result, the target memory cell (target MC) may have a threshold voltage distribution corresponding to the second program state PV2, which is higher than the second verify voltage Vver 2. During the program voltage applying operation, a program-inhibit voltage may be applied to bit lines of memory cells corresponding to the erased state PV0 and memory cells that have been programmed to the first program state PV1, thereby preventing the threshold voltage of the memory cells from increasing.

During the program operation for the second program state PV2, the remaining memory cells (i.e., other MCs) intended to be programmed to the fourth through seventh program states PV4 through PV7 may be programmed to a pre-programmed state (i.e., a pre-state). The pre-programmed state (pre-state) may be a state in which the threshold voltage distribution is higher than in the second programmed state PV 2. For example, until the above-described target memory cell (target MC) passes the program verify operation, the program operation may not be performed on the remaining memory cells (other MCs), and the memory cells having the threshold voltage distribution higher than the third verify voltage Vver3 corresponding to the immediately higher program state PV3 among the remaining memory cells (other MCs) may be operated in the program inhibit mode. As a result, while the target memory cell (target MC) is programmed to the second program state PV2, the remaining memory cells (other MCs) may be programmed to a pre-programmed state (pre-state) having a higher threshold voltage distribution than that in the second program state PV 2.

Based on the programming methods described with reference to fig. 7 and 8, the remaining memory cells (other MC) except for the target memory cell (target MC) may be programmed to the pre-programmed state during the respective programming operations corresponding to the first to sixth program states PV1 to P6. Finally, during the program operation for the seventh program state PV7, only the memory cells intended to be programmed to the seventh program state PV7 may be set as target memory cells (target MCs), and then the program operation may be performed on the target memory cells.

According to an embodiment of the present disclosure, before a program operation for a target program state is performed, a threshold voltage distribution of a target memory cell may be increased to a threshold voltage range adjacent to the target program state. Accordingly, during a program operation for a target program state, the magnitude of an increased threshold voltage may be reduced, and thus threshold voltage distribution may be improved.

Further, during the program operation, the program operations for the first to seventh program states are sequentially performed, and thus, the program verify operation performed after the program voltage applying operation may be simplified from the verify operation for the first to seventh program states to the verify operation for the target program state and the verify operation for the pre-program state.

Fig. 9 is a schematic diagram describing a programming mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Referring to fig. 9, during a program operation for a first program state PV1, memory cells to be programmed to a first program state PV1 and memory cells to be programmed to a second program state PV2 adjacent to the first program state PV1 may be programmed to have threshold voltage distributions corresponding to the first program state PV 1. That is, bit lines corresponding to memory cells to be programmed to the first program state PV1 and memory cells to be programmed to the second program state PV2 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the first program state PV1 and the memory cells to be programmed to the second program state PV2 is terminated, the memory cells to be programmed to the remaining program states PV3 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the first program state PV 1. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the second program state PV2 among memory cells to be programmed to the remaining program states PV3 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the second program state PV 2. That is, among the memory cells to be programmed to the remaining program states PV3 to PV7, the memory cells having a threshold voltage lower than that in the second program state PV2 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the first program state PV1 is completed, the program operation for the second program state PV2 is performed. During a programming operation for the second program state PV2, memory cells to be programmed to the second program state PV2 and memory cells to be programmed to a third program state PV3 adjacent to the second program state PV2 may be programmed to have threshold voltage distributions corresponding to the second program state PV 2. That is, bit lines corresponding to memory cells to be programmed to the second program state PV2 and memory cells to be programmed to the third program state PV3 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit line corresponding to the memory cell that has been programmed to the first program state PV1 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the second program state PV2 and the memory cells to be programmed to the third program state PV3 is terminated, the memory cells to be programmed to the remaining program states PV4 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distributions of the memory cells are higher than that in the second program state PV 2. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the third program state PV3 among memory cells to be programmed to the remaining program states PV4 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the third program state PV 3. That is, among the memory cells to be programmed to the remaining program states PV4 to PV7, the memory cells having a threshold voltage lower than that in the third program state PV3 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the second program state PV2 is completed, the program operation for the third program state PV3 is performed. During a program operation for the third program state PV3, memory cells to be programmed to the third program state PV3 and memory cells to be programmed to a fourth program state PV4 adjacent to the third program state PV3 may be programmed to have threshold voltage distributions corresponding to the third program state PV 3. That is, bit lines corresponding to memory cells to be programmed to the third program state PV3 and memory cells to be programmed to the fourth program state PV4 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first program state PV1 and the memory cells that have been programmed to the second program state PV2 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operations for the memory cells to be programmed to the third program state PV3 and the memory cells to be programmed to the fourth program state PV4 are terminated, the memory cells to be programmed to the remaining program states PV5 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the third program state PV 3. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fourth program state PV4 among memory cells to be programmed to the remaining program states PV5 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fourth program state PV 4. That is, among the memory cells to be programmed to the remaining program states PV5 to PV7, the memory cells having a threshold voltage lower than that in the fourth program state PV4 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the third program state PV3 is completed, the program operation for the fourth program state PV4 is performed. During a program operation for the fourth program state PV4, memory cells to be programmed to the fourth program state PV4 and memory cells to be programmed to the fifth program state PV5 adjacent to the fourth program state PV4 may be programmed to have threshold voltage distributions corresponding to the fourth program state PV 4. That is, bit lines corresponding to memory cells to be programmed to the fourth program state PV4 and memory cells to be programmed to the fifth program state PV5 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third program states PV1 to PV3 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operations for the memory cells to be programmed to the fourth program state PV4 and the memory cells to be programmed to the fifth program state PV5 are terminated, the memory cells to be programmed to the remaining program states PV6 and PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the fourth program state PV 4. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fifth program state PV5 among memory cells to be programmed to the remaining program states PV6 and PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fifth program state PV 5. That is, among the memory cells to be programmed to the remaining program states PV6 and PV7, the memory cells having a threshold voltage lower than that in the fifth program state PV5 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the fourth program state PV4 is completed, the program operation for the fifth program state PV5 is performed. During a program operation for the fifth program state PV5, memory cells to be programmed to the fifth program state PV5 and memory cells to be programmed to the sixth program state PV6 adjacent to the fifth program state PV5 may be programmed to have threshold voltage distributions corresponding to the fifth program state PV 5. That is, bit lines corresponding to memory cells to be programmed to the fifth program state PV5 and memory cells to be programmed to the sixth program state PV6 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth program states PV1 to PV4 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the fifth program state PV5 and the memory cells to be programmed to the sixth program state PV6 is terminated, the memory cells to be programmed to the remaining program states PV7 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distributions of the memory cells are higher than that in the fifth program state PV 5. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the sixth program state PV6 among memory cells to be programmed to the remaining program state PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the sixth program state PV 6. That is, among the memory cells to be programmed to the remaining program state PV7, the memory cells having a threshold voltage lower than that in the sixth program state PV6 may be controlled to be a program MODE (PGM MODE).

When the program operation for the fifth program state PV5 is completed, the program operation for the sixth program state PV6 is performed. During a program operation for the sixth program state PV6, memory cells to be programmed to the sixth program state PV6 and memory cells to be programmed to the seventh program state PV7 adjacent to the sixth program state PV6 may be programmed to have threshold voltage distributions corresponding to the sixth program state PV 6. That is, bit lines corresponding to memory cells to be programmed to the sixth program state PV6 and memory cells to be programmed to the seventh program state PV7 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth program states PV1 to PV5 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

When the program operation for the sixth program state PV6 is completed, the program operation for the seventh program state PV7 is performed. During a program operation for the seventh program state PV7, bit lines corresponding to memory cells to be programmed to the seventh program state PV7 may be controlled to a program mode (PGM mode) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth program states PV1 to PV6 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Although in the above-described embodiments of the present disclosure, the description has been made based on the three-level cell (TLC) programming scheme in which the number of threshold voltage distributions to program the memory cell is eight (i.e., PV0 to PV7) by way of example, the present embodiment may also be applied to a multi-level cell (MLC) programming scheme in which the number of threshold voltage distributions is four and a four-level cell (QLC) programming scheme in which the number of threshold voltage distributions is 16.

Fig. 10 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Referring to fig. 10, during a program operation for the first program state PV1, memory cells to be programmed to the first program state PV1 may be programmed to have a threshold voltage distribution corresponding to the first program state PV 1. That is, the bit line corresponding to the memory cell to be programmed to the first program state PV1 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the first program state PV1 is terminated, the memory cells to be programmed to the remaining program states PV2 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the first program state PV 1. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the second program state PV2 among memory cells to be programmed to the remaining program states PV2 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the second program state PV 2. That is, among the memory cells to be programmed to the remaining program states PV2 to PV7, the memory cells having a threshold voltage lower than that in the second program state PV2 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the first program state PV1 is terminated, the program operation for the second program state PV2 is performed. During a programming operation for the second program state PV2, memory cells to be programmed to the second program state PV2 may be programmed to have a threshold voltage distribution corresponding to the second program state PV 2. That is, the bit line corresponding to the memory cell to be programmed to the second program state PV2 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit line corresponding to the memory cell that has been programmed to the first program state PV1 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the second program state PV2 is terminated, the memory cells to be programmed to the remaining program states PV3 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the second program state PV 2. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the third program state PV3 among memory cells to be programmed to the remaining program states PV3 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the third program state PV 3. That is, among the memory cells to be programmed to the remaining program states PV3 to PV7, the memory cells having a threshold voltage lower than that in the third program state PV3 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the second program state PV2 is terminated, the program operation for the third program state PV3 is performed. During a programming operation for the third program state PV3, memory cells to be programmed to the third program state PV3 may be programmed to have a threshold voltage distribution corresponding to the third program state PV 3. That is, the bit line corresponding to the memory cell to be programmed to the third program state PV3 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first program state PV1 and the memory cells that have been programmed to the second program state PV2 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the third program state PV3 is terminated, the memory cells to be programmed to the remaining program states PV4 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the third program state PV 3. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fourth program state PV4 among memory cells to be programmed to the remaining program states PV4 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fourth program state PV 4. That is, among the memory cells to be programmed to the remaining program states PV4 to PV7, the memory cells having a threshold voltage lower than that in the fourth program state PV4 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the third program state PV3 is terminated, the program operation for the fourth program state PV4 is performed. During a programming operation for the fourth program state PV4, memory cells to be programmed to the fourth program state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth program state PV 4. That is, the bit line corresponding to the memory cell to be programmed to the fourth program state PV4 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third program states PV1 to PV3 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the fourth program state PV4 is terminated, the memory cells to be programmed to the remaining program states PV5 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the fourth program state PV 4. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fifth program state PV5 among memory cells to be programmed to the remaining program states PV5 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fifth program state PV 5. That is, among the memory cells to be programmed to the remaining program states PV5 to PV7, the memory cells having a threshold voltage lower than that in the fifth program state PV5 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the fourth program state PV4 is terminated, the program operation for the fifth program state PV5 is performed. During a programming operation for the fifth program state PV5, memory cells to be programmed to the fifth program state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth program state PV 5. That is, the bit line corresponding to the memory cell to be programmed to the fifth program state PV5 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth program states PV1 to PV4 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the fifth program state PV5 is terminated, the memory cells to be programmed to the remaining program states PV6 and PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the fifth program state PV 5. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the sixth program state PV6 among memory cells to be programmed to the remaining program states PV6 and PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the sixth program state PV 6. That is, among the memory cells to be programmed to the remaining program states PV6 and PV7, the memory cells having a threshold voltage lower than that in the sixth program state PV6 may be controlled to be in the program MODE (PGM MODE).

When the program operation for the fifth program state PV5 is terminated, the program operation for the sixth program state PV6 is performed. During a programming operation for the sixth program state PV6, memory cells to be programmed to the sixth program state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth program state PV 6. That is, the bit line corresponding to the memory cell to be programmed to the sixth program state PV6 may be controlled to the program MODE (PGM MODE) in which the program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth program states PV1 to PV5 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the sixth program state PV6 is terminated, the memory cells to be programmed to the remaining program states PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the sixth program state PV 6. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the seventh program state PV7 among memory cells to be programmed to the remaining program state PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the seventh program state PV 7. That is, among the memory cells to be programmed to the remaining program state PV7, the memory cells having a threshold voltage lower than that in the seventh program state PV7 may be controlled to be a program MODE (PGM MODE).

When the program operation for the sixth program state PV6 is terminated, the program operation for the seventh program state PV7 is performed. During a program operation for the seventh program state PV7, bit lines corresponding to memory cells to be programmed to the seventh program state PV7 may be controlled to a program mode (PGM mode) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth program states PV1 to PV6 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Fig. 11 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Referring to fig. 11, during a program operation for a first program state PV1, memory cells to be programmed to the first program state PV1, memory cells to be programmed to second and third program states PV2 and PV3 adjacent to the first program state PV1 may be programmed to have threshold voltage distributions corresponding to the first program state PV 1. That is, bit lines corresponding to memory cells to be programmed to the first to third program states PV1 to PV3 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the first to third program states PV1 to PV3 is terminated, the memory cells to be programmed to the remaining program states PV4 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distributions of the memory cells are higher than that in the first program state PV 1. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the second program state PV2 among memory cells to be programmed to the remaining program states PV4 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the second program state PV 2. That is, among the memory cells to be programmed to the remaining program states PV4 to PV7, the memory cells having a threshold voltage lower than that in the second program state PV2 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the first program state PV1 is completed, the program operation for the second program state PV2 is performed. During a programming operation for the second program state PV2, memory cells to be programmed to the second program state PV2 and memory cells to be programmed to the third and fourth program states PV3 and PV4 adjacent to the second program state PV2 may be programmed to have threshold voltage distributions corresponding to the second program state PV 2. That is, bit lines corresponding to memory cells to be programmed to the second to fourth program states PV2 to PV4 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit line corresponding to the memory cell that has been programmed to the first program state PV1 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the second to fourth program states PV2 to PV4 is terminated, the memory cells to be programmed to the remaining program states PV5 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the second program state PV 2. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the third program state PV3 among memory cells to be programmed to the remaining program states PV5 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the third program state PV 3. That is, among the memory cells to be programmed to the remaining program states PV5 to PV7, the memory cells having a threshold voltage lower than that in the third program state PV3 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the second program state PV2 is completed, the program operation for the third program state PV3 is performed. During a programming operation for the third program state PV3, memory cells to be programmed to the third program state PV3 and memory cells to be programmed to the fourth and fifth program states PV4 and PV5 adjacent to the third program state PV3 may be programmed to have threshold voltage distributions corresponding to the third program state PV 3. That is, the bit lines corresponding to the memory cells to be programmed to the third to fifth program states PV3 to PV5 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first program state PV1 and the memory cells that have been programmed to the second program state PV2 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the third to fifth program states PV3 to PV5 is terminated, the memory cells to be programmed to the remaining program states PV6 and PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the third program state PV 3. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fourth program state PV4 among memory cells to be programmed to the remaining program states PV6 and PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fourth program state PV 4. That is, among the memory cells to be programmed to the remaining program states PV6 and PV7, the memory cells having a threshold voltage lower than that in the fourth program state PV4 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the third program state PV3 is completed, the program operation for the fourth program state PV4 is performed. During a programming operation for the fourth program state PV4, memory cells to be programmed to the fourth program state PV4 and memory cells to be programmed to the fifth and sixth program states PV5 and PV6 adjacent to the fourth program state PV4 may be programmed to have threshold voltage distributions corresponding to the fourth program state PV 4. That is, the bit lines corresponding to the memory cells to be programmed to the fourth to sixth program states PV4 to PV6 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third program states PV1 to PV3 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the fourth through sixth program states PV4 through PV6 is terminated, the memory cells to be programmed to the remaining program states PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the fourth program state PV 4. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fifth program state PV5 among memory cells to be programmed to the remaining program state PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fifth program state PV 5. That is, among the memory cells to be programmed to the remaining program state PV7, the memory cells having a threshold voltage lower than that in the fifth program state PV5 may be controlled to be a program MODE (PGM MODE).

When the program operation for the fourth program state PV4 is completed, the program operation for the fifth program state PV5 is performed. During a programming operation for the fifth program state PV5, memory cells to be programmed to the fifth program state PV5 and memory cells to be programmed to the sixth and seventh program states PV6 and PV7 adjacent to the fifth program state PV5 may be programmed to have threshold voltage distributions corresponding to the fifth program state PV 5. That is, the bit lines corresponding to the memory cells to be programmed to the fifth to seventh program states PV5 to PV7 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth program states PV1 to PV4 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

When the program operation for the fifth program state PV5 is completed, the program operation for the sixth program state PV6 is performed. During a program operation for the sixth program state PV6, memory cells to be programmed to the sixth program state PV6 and memory cells to be programmed to the seventh program state PV7 adjacent to the sixth program state PV6 may be programmed to have threshold voltage distributions corresponding to the sixth program state PV 6. That is, bit lines corresponding to memory cells to be programmed to the sixth program state PV6 and memory cells to be programmed to the seventh program state PV7 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth program states PV1 to PV5 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

When the program operation for the sixth program state PV6 is completed, the program operation for the seventh program state PV7 is performed. During a program operation for the seventh program state PV7, bit lines corresponding to memory cells to be programmed to the seventh program state PV7 may be controlled to a program mode (PGM mode) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth program states PV1 to PV6 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Fig. 12 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Referring to fig. 12, during a program operation for the first program state PV1, memory cells to be programmed to the first program state PV1 may be programmed to have a threshold voltage distribution corresponding to the first program state PV 1. That is, the bit line corresponding to the memory cell to be programmed to the first program state PV1 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the first program state PV1 is terminated, the memory cells to be programmed to the remaining program states PV2 to PV7 may be programmed to a pre-programmed state higher than the first program state PV 1. For example, a program permission voltage may be applied to a bit line of a memory cell having a threshold voltage lower than that in the second program state PV2 among memory cells to be programmed to the second program state PV2 and the third program state PV3 adjacent to the first program state PV1, and a program inhibition voltage may be applied to a bit line of a memory cell having a threshold voltage equal to or higher than that in the second program state PV 2. Further, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the third program state PV3 among memory cells to be programmed to the remaining program states PV4 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the third program state PV 3.

That is, among the memory cells to be programmed to the second and third program states PV2 and PV3, the memory cells having a threshold voltage lower than that in the second program state PV2 may be controlled to be a program MODE (PGM MODE). Also, among the memory cells to be programmed into the program states PV4 to PV7, the memory cells having a threshold voltage lower than that in the third program state PV3 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the first program state PV1 is terminated, the program operation for the second program state PV2 is performed. During a programming operation for the second program state PV2, memory cells to be programmed to the second program state PV2 may be programmed to have a threshold voltage distribution corresponding to the second program state PV 2. That is, the bit line corresponding to the memory cell to be programmed to the second program state PV2 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the second program state PV2 is terminated, the memory cells to be programmed to the remaining program states PV3 to PV7 may be programmed to a pre-programmed state higher than the second program state PV 2. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the third program state PV3 among memory cells to be programmed to the third and fourth program states PV3 and PV4 adjacent to the second program state PV2, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the third program state PV 3. Further, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fourth program state PV4 among memory cells to be programmed to the remaining program states PV5 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fourth program state PV 4.

That is, among the memory cells to be programmed to the third and fourth program states PV3 and PV4, the memory cells having a threshold voltage lower than that in the third program state PV3 may be controlled to be a program MODE (PGM MODE). Also, among the memory cells to be programmed into the program states PV5 to PV7, the memory cells having a threshold voltage lower than that in the fourth program state PV4 may be controlled to be in the program MODE (PGM MODE).

When the program operation for the second program state PV2 is terminated, the program operation for the third program state PV3 is performed. During a programming operation for the third program state PV3, memory cells to be programmed to the third program state PV3 may be programmed to have a threshold voltage distribution corresponding to the third program state PV 3. That is, the bit line corresponding to the memory cell to be programmed to the third program state PV3 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the third program state PV3 is terminated, the memory cells to be programmed to the remaining program states PV4 to PV7 may be programmed to a pre-programmed state higher than the third program state PV 3. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fourth program state PV4 among memory cells to be programmed to the fourth and fifth program states PV4 and PV5 adjacent to the third program state PV3, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fourth program state PV 4. Further, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fifth program state PV5 among memory cells to be programmed to the remaining program states PV6 and PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fifth program state PV 5.

That is, among the memory cells to be programmed to the fourth and fifth program states PV4 and PV5, the memory cells having a threshold voltage lower than that in the fourth program state PV4 may be controlled to be a program MODE (PGM MODE). Also, among the memory cells to be programmed into the program states PV6 and PV7, the memory cells having a threshold voltage lower than that in the fifth program state PV5 may be controlled to be a program MODE (PGM MODE).

When the program operation for the third program state PV3 is terminated, the program operation for the fourth program state PV4 is performed. During a programming operation for the fourth program state PV4, memory cells to be programmed to the fourth program state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth program state PV 4. That is, the bit line corresponding to the memory cell to be programmed to the fourth program state PV4 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the fourth program state PV4 is terminated, the memory cells to be programmed to the remaining program states PV5 to PV7 may be programmed to a pre-programmed state higher than the fourth program state PV 4. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fifth program state PV5 among memory cells to be programmed to the fifth and sixth program states PV5 and PV6 adjacent to the fourth program state PV4, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fifth program state PV 5. Further, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the sixth program state PV6 among memory cells to be programmed to the remaining program state PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the sixth program state PV 6.

That is, among the memory cells to be programmed to the fifth and sixth program states PV5 and PV6, the memory cells having a threshold voltage lower than that in the fifth program state PV5 may be controlled to be a program MODE (PGM MODE). Also, among the memory cells to be programmed to the program state PV7, the memory cells having a threshold voltage lower than that in the sixth program state PV6 may be controlled to be a program MODE (PGM MODE).

When the program operation for the fourth program state PV4 is terminated, the program operation for the fifth program state PV5 is performed. During a programming operation for the fifth program state PV5, memory cells to be programmed to the fifth program state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth program state PV 5. That is, the bit line corresponding to the memory cell to be programmed to the fifth program state PV5 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the fifth program state PV5 is terminated, the memory cells to be programmed to the remaining program states PV6 and PV7 may be programmed to a pre-programmed state higher than the fifth program state PV 5. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the sixth program state PV6 among memory cells to be programmed to the sixth and seventh program states PV6 and PV7 adjacent to the fifth program state PV5, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the sixth program state PV 6.

That is, among the memory cells to be programmed to the sixth and seventh program states PV6 and PV7, the memory cells having a threshold voltage lower than that in the sixth program state PV6 may be controlled to be a program MODE (PGM MODE).

When the program operation for the fifth program state PV5 is terminated, the program operation for the sixth program state PV6 is performed. During a programming operation for the sixth program state PV6, memory cells to be programmed to the sixth program state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth program state PV 6. That is, the bit line corresponding to the memory cell to be programmed to the sixth program state PV6 may be controlled to the program MODE (PGM MODE) in which the program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the sixth program state PV6 is terminated, the memory cells to be programmed to the remaining program state PV7 may be programmed to a pre-programmed state higher than the sixth program state PV 6. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the seventh program state PV7 among memory cells to be programmed to the seventh program state PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the seventh program state PV 7.

That is, among the memory cells to be programmed to the seventh program state PV7, the memory cells having a threshold voltage lower than that in the seventh program state PV7 may be controlled to be a program MODE (PGM MODE).

When the program operation for the sixth program state PV6 is terminated, the program operation for the seventh program state PV7 is performed. During a programming operation for the seventh program state PV7, memory cells to be programmed to the seventh program state PV7 may be programmed to have a threshold voltage distribution corresponding to the seventh program state PV 7. That is, the bit line corresponding to the memory cell to be programmed to the seventh program state PV7 may be controlled to the program MODE (PGM MODE) in which the program permission voltage is applied.

Fig. 13 is a schematic diagram for describing a programming mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Referring to fig. 13, during a program operation for a first program state PV1, memory cells to be programmed to a first program state PV1 and memory cells to be programmed to a second program state PV2 adjacent to the first program state PV1 may be programmed to have threshold voltage distributions corresponding to the first program state PV 1. That is, bit lines corresponding to memory cells to be programmed to the first program state PV1 and memory cells to be programmed to the second program state PV2 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the first program state PV1 and the memory cells to be programmed to the second program state PV2 is terminated, the memory cells to be programmed to the remaining program states PV3 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the first program state PV 1.

For example, among the remaining program states PV3 to PV7, memory cells to be programmed to the third program state PV3 and the fourth program state PV4, which have relatively low threshold voltage distributions, and memory cells to be programmed to the fifth program state PV5 to the seventh program state PV7, which have relatively high threshold voltage distributions, may be programmed to have different threshold voltage distributions. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the second program state PV2 among memory cells to be programmed to the third and fourth program states PV3 and PV4, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the second program state PV 2. That is, among the memory cells to be programmed to the third and fourth program states PV3 and PV4, the memory cells having a threshold voltage lower than that in the second program state PV2 may be controlled to be a program MODE (PGM MODE). Further, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the third program state PV3 among memory cells to be programmed to the fifth to seventh program states PV5 to PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the third program state PV 3. That is, among the memory cells to be programmed to the fifth to seventh program states PV5 to PV7, the memory cells having a threshold voltage lower than that in the third program state PV3 may be controlled to be a program MODE (PGM MODE).

When the program operation for the first program state PV1 is completed, the program operation for the second program state PV2 is performed. During a programming operation for the second program state PV2, memory cells to be programmed to the second program state PV2 and memory cells to be programmed to a third program state PV3 adjacent to the second program state PV2 may be programmed to have threshold voltage distributions corresponding to the second program state PV 2. That is, bit lines corresponding to memory cells to be programmed to the second program state PV2 and memory cells to be programmed to the third program state PV3 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit line corresponding to the memory cell that has been programmed to the first program state PV1 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the second program state PV2 and the memory cells to be programmed to the third program state PV3 is terminated, the memory cells to be programmed to the remaining program states PV4 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distributions of the memory cells are higher than that in the second program state PV 2.

For example, among the remaining program states PV4 to PV7, memory cells to be programmed to the fourth and fifth program states PV4 and PV5, which have relatively low threshold voltage distributions, and memory cells to be programmed to the sixth and seventh program states PV6 and PV7, which have relatively high threshold voltage distributions, may be programmed to have different threshold voltage distributions. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the third program state PV3 among memory cells to be programmed to the fourth program state PV4 and the fifth program state PV5, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the third program state PV 3. That is, among the memory cells to be programmed to the fourth and fifth program states PV4 and PV5, the memory cells having a threshold voltage lower than that in the third program state PV3 may be controlled to be a program MODE (PGM MODE). Further, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fourth program state PV4 among memory cells to be programmed to the sixth and seventh program states PV6 and PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fourth program state PV 4. That is, among the memory cells to be programmed to the sixth and seventh program states PV6 and PV7, the memory cells having a threshold voltage lower than that in the fourth program state PV4 may be controlled to be a program MODE (PGM MODE).

When the program operation for the second program state PV2 is completed, the program operation for the third program state PV3 is performed. During a program operation for the third program state PV3, memory cells to be programmed to the third program state PV3 and memory cells to be programmed to a fourth program state PV4 adjacent to the third program state PV3 may be programmed to have threshold voltage distributions corresponding to the third program state PV 3. That is, bit lines corresponding to memory cells to be programmed to the third program state PV3 and memory cells to be programmed to the fourth program state PV4 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first and second program states PV1 and PV2 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operations for the memory cells to be programmed to the third program state PV3 and the memory cells to be programmed to the fourth program state PV4 are terminated, the memory cells to be programmed to the remaining program states PV5 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the third program state PV 3.

For example, among the remaining program states PV5 through PV7, memory cells to be programmed to fifth and sixth program states PV5 and PV6 having relatively low threshold voltage distributions and memory cells to be programmed to a seventh program state PV7 having a relatively high threshold voltage distribution may be programmed to different threshold voltage distributions. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fourth program state PV4 among memory cells to be programmed to the fifth and sixth program states PV5 and PV6, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fourth program state PV 4. That is, among the memory cells to be programmed to the fifth and sixth program states PV5 and PV6, the memory cells having a threshold voltage lower than that in the fourth program state PV4 may be controlled to be a program MODE (PGM MODE). Further, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fifth program state PV5 among memory cells to be programmed to the seventh program state PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fifth program state PV 5. That is, among the memory cells to be programmed to the seventh program state PV7, the memory cells having a threshold voltage lower than that in the fifth program state PV5 may be controlled to be a program MODE (PGM MODE).

When the program operation for the third program state PV3 is completed, the program operation for the fourth program state PV4 is performed. During a program operation for the fourth program state PV4, memory cells to be programmed to the fourth program state PV4 and memory cells to be programmed to the fifth program state PV5 adjacent to the fourth program state PV4 may be programmed to have threshold voltage distributions corresponding to the fourth program state PV 4. That is, bit lines corresponding to memory cells to be programmed to the fourth program state PV4 and memory cells to be programmed to the fifth program state PV5 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third program states PV1 to PV3 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operations for the memory cells to be programmed to the fourth program state PV4 and the memory cells to be programmed to the fifth program state PV5 are terminated, the memory cells to be programmed to the remaining program states PV6 and PV7 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the fourth program state PV 4. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fifth program state PV5 among memory cells to be programmed to the remaining program states PV6 and PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fifth program state PV 5. That is, among the memory cells to be programmed to the remaining program states PV6 and PV7, the memory cells having a threshold voltage lower than that in the fifth program state PV5 may be controlled to be in a program MODE (PGM MODE).

When the program operation for the fourth program state PV4 is completed, the program operation for the fifth program state PV5 is performed. During a program operation for the fifth program state PV5, memory cells to be programmed to the fifth program state PV5 and memory cells to be programmed to the sixth program state PV6 adjacent to the fifth program state PV5 may be programmed to have threshold voltage distributions corresponding to the fifth program state PV 5. That is, bit lines corresponding to memory cells to be programmed to the fifth program state PV5 and memory cells to be programmed to the sixth program state PV6 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth program states PV1 to PV4 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the fifth program state PV5 and the memory cells to be programmed to the sixth program state PV6 is terminated, the memory cells to be programmed to the remaining program states PV7 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distributions of the memory cells are higher than that in the fifth program state PV 5. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the sixth program state PV6 among memory cells to be programmed to the remaining program state PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the sixth program state PV 6. That is, among the memory cells to be programmed to the remaining program state PV7, the memory cells having a threshold voltage lower than that in the sixth program state PV6 may be controlled to be a program MODE (PGM MODE).

When the program operation for the fifth program state PV5 is completed, the program operation for the sixth program state PV6 is performed. During a program operation for the sixth program state PV6, memory cells to be programmed to the sixth program state PV6 and memory cells to be programmed to the seventh program state PV7 adjacent to the sixth program state PV6 may be programmed to have threshold voltage distributions corresponding to the sixth program state PV 6. That is, bit lines corresponding to memory cells to be programmed to the sixth program state PV6 and memory cells to be programmed to the seventh program state PV7 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth program states PV1 to PV5 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

When the program operation for the sixth program state PV6 is completed, the program operation for the seventh program state PV7 is performed. During a program operation for the seventh program state PV7, bit lines corresponding to memory cells to be programmed to the seventh program state PV7 may be controlled to a program mode (PGM mode) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth program states PV1 to PV6 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Fig. 14 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Referring to fig. 14, during a program operation for a first program state PV1, memory cells to be programmed to a first program state PV1 and memory cells to be programmed to a second program state PV2 adjacent to the first program state PV1 may be programmed to have threshold voltage distributions corresponding to the first program state PV 1. That is, bit lines corresponding to memory cells to be programmed to the first program state PV1 and memory cells to be programmed to the second program state PV2 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operations for the memory cells to be programmed to the first program state PV1 and the memory cells to be programmed to the second program state PV2 are terminated, the memory cells to be programmed to the remaining program states PV3 to PV7 may be controlled to be in a program MODE (PGM MODE), and thus the threshold voltage distributions of the memory cells may be increased.

When the program operation for the first program state PV1 is completed, the program operation for the second program state PV2 is performed. During a programming operation for the second program state PV2, memory cells to be programmed to the second program state PV2 and memory cells to be programmed to a third program state PV3 adjacent to the second program state PV2 may be programmed to have threshold voltage distributions corresponding to the second program state PV 2. That is, bit lines corresponding to memory cells to be programmed to the second program state PV2 and memory cells to be programmed to the third program state PV3 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit line corresponding to the memory cell that has been programmed to the first program state PV1 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operations for the memory cells to be programmed to the second program state PV2 and the memory cells to be programmed to the third program state PV3 are terminated, the memory cells to be programmed to the remaining program states PV4 to PV7 may be controlled to be in the program MODE (PGM MODE), and thus the threshold voltage distributions of the memory cells may be increased.

When the program operation for the second program state PV2 is completed, the program operation for the third program state PV3 is performed. During a program operation for the third program state PV3, memory cells to be programmed to the third program state PV3 and memory cells to be programmed to a fourth program state PV4 adjacent to the third program state PV3 may be programmed to have threshold voltage distributions corresponding to the third program state PV 3. That is, bit lines corresponding to memory cells to be programmed to the third program state PV3 and memory cells to be programmed to the fourth program state PV4 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first program state PV1 and the memory cells that have been programmed to the second program state PV2 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operations for the memory cells to be programmed to the third program state PV3 and the memory cells to be programmed to the fourth program state PV4 are terminated, the memory cells to be programmed to the remaining program states PV5 to PV7 may be controlled to be in the program MODE (PGM MODE), and thus the threshold voltage distributions of the memory cells may be increased.

When the program operation for the third program state PV3 is completed, the program operation for the fourth program state PV4 is performed. During a program operation for the fourth program state PV4, memory cells to be programmed to the fourth program state PV4 and memory cells to be programmed to the fifth program state PV5 adjacent to the fourth program state PV4 may be programmed to have threshold voltage distributions corresponding to the fourth program state PV 4. That is, bit lines corresponding to memory cells to be programmed to the fourth program state PV4 and memory cells to be programmed to the fifth program state PV5 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third program states PV1 to PV3 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operations for the memory cells to be programmed to the fourth program state PV4 and the memory cells to be programmed to the fifth program state PV5 are terminated, the memory cells to be programmed to the remaining program states PV6 and PV7 may be controlled to the program MODE PGM MODE, and thus the threshold voltage distributions of the memory cells may be increased.

When the program operation for the fourth program state PV4 is completed, the program operation for the fifth program state PV5 is performed. During a program operation for the fifth program state PV5, memory cells to be programmed to the fifth program state PV5 and memory cells to be programmed to the sixth program state PV6 adjacent to the fifth program state PV5 may be programmed to have threshold voltage distributions corresponding to the fifth program state PV 5. That is, bit lines corresponding to memory cells to be programmed to the fifth program state PV5 and memory cells to be programmed to the sixth program state PV6 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth program states PV1 to PV4 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operations for the memory cells to be programmed to the fifth program state PV5 and the memory cells to be programmed to the sixth program state PV6 are terminated, the memory cells to be programmed to the remaining program states PV7 may be controlled to be in the program MODE (PGM MODE), and thus the threshold voltage distributions of the memory cells may be increased.

When the program operation for the fifth program state PV5 is completed, the program operation for the sixth program state PV6 is performed. During a program operation for the sixth program state PV6, memory cells to be programmed to the sixth program state PV6 and memory cells to be programmed to the seventh program state PV7 adjacent to the sixth program state PV6 may be programmed to have threshold voltage distributions corresponding to the sixth program state PV 6. That is, bit lines corresponding to memory cells to be programmed to the sixth program state PV6 and memory cells to be programmed to the seventh program state PV7 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth program states PV1 to PV5 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

When the program operation for the sixth program state PV6 is completed, the program operation for the seventh program state PV7 is performed. During a program operation for the seventh program state PV7, bit lines corresponding to memory cells to be programmed to the seventh program state PV7 may be controlled to a program mode (PGM mode) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth program states PV1 to PV6 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Fig. 15 is a schematic diagram for describing a program mode of memory cells depending on respective program states during a program operation according to an embodiment of the present disclosure.

Referring to fig. 15, during a program operation for the first program state PV1, memory cells to be programmed to the first program state PV1 may be programmed to have a threshold voltage distribution corresponding to the first program state PV 1. That is, the bit line corresponding to the memory cell to be programmed to the first program state PV1 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied.

Here, until the program operation for the memory cells to be programmed to the first program state PV1 is terminated, the memory cells to be programmed to the second program state PV2 adjacent to the first program state PV1 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than that in the first program state PV 1. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the second program state PV2 among memory cells to be programmed to the second program state PV2, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the second program state PV 2. That is, among the memory cells to be programmed to the second program state PV2, the memory cells having a threshold voltage lower than that in the second program state PV2 may be controlled to be a program MODE (PGM MODE).

Also, until the program operation for the memory cells to be programmed to the first program state PV1 is terminated, the memory cells to be programmed to the remaining program states PV3 to PV7 may be controlled to be in a program MODE (PGM MODE), and thus their threshold voltage distributions may be increased.

When the program operation for the first program state PV1 is completed, the program operation for the second program state PV2 is performed. During a programming operation for the second program state PV2, memory cells to be programmed to the second program state PV2 may be programmed to have a threshold voltage distribution corresponding to the second program state PV 2. That is, the bit line corresponding to the memory cell to be programmed to the second program state PV2 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit line corresponding to the memory cell that has been programmed to the first program state PV1 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the second program state PV2 is terminated, the memory cells to be programmed to the third program state PV3 adjacent to the second program state PV2 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than those in the second program state PV 2. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the third program state PV3 among memory cells to be programmed to the third program state PV3, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the third program state PV 3. That is, among the memory cells to be programmed to the third program state PV3, the memory cells having a threshold voltage lower than that in the third program state PV3 may be controlled to be a program MODE (PGM MODE).

Also, until the program operation for the memory cells to be programmed to the second program state PV2 is terminated, the memory cells to be programmed to the remaining program states PV4 to PV7 may be controlled to be in a program MODE (PGM MODE), and thus their threshold voltage distributions may be increased.

When the program operation for the second program state PV2 is completed, the program operation for the third program state PV3 is performed. During a programming operation for the third program state PV3, memory cells to be programmed to the third program state PV3 may be programmed to have a threshold voltage distribution corresponding to the third program state PV 3. That is, the bit line corresponding to the memory cell to be programmed to the third program state PV3 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first and second program states PV1 and PV2 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Until the program operation for the memory cells to be programmed to the third program state PV3 is terminated, the memory cells to be programmed to the fourth program state PV4 adjacent to the third program state PV3 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than in the third program state PV 3. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fourth program state PV4 among memory cells to be programmed to the fourth program state PV4, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fourth program state PV 4. That is, among the memory cells to be programmed to the fourth program state PV4, the memory cells having a threshold voltage lower than that in the fourth program state PV4 may be controlled to be a program MODE (PGM MODE).

Also, until the program operation for the memory cells to be programmed to the third program state PV3 is terminated, the memory cells to be programmed to the remaining program states PV5 to PV7 may be controlled to be in the program MODE (PGM MODE), and thus their threshold voltage distributions may be increased.

When the program operation for the third program state PV3 is completed, the program operation for the fourth program state PV4 is performed. During a programming operation for the fourth program state PV4, memory cells to be programmed to the fourth program state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth program state PV 4. That is, the bit line corresponding to the memory cell to be programmed to the fourth program state PV4 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third program states PV1 to PV3 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Here, until the program operation for the memory cells to be programmed to the fourth program state PV4 is terminated, the memory cells to be programmed to the fifth program state PV5 adjacent to the fourth program state PV4 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than that in the fourth program state PV 4. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the fifth program state PV5 among memory cells to be programmed to the fifth program state PV5, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the fifth program state PV 5. That is, among the memory cells to be programmed to the fifth program state PV5, the memory cells having a threshold voltage lower than that in the fifth program state PV5 may be controlled to be a program MODE (PGM MODE).

Also, until the program operation for the memory cells to be programmed to the fourth program state PV4 is terminated, the memory cells to be programmed to the remaining program states PV6 and PV7 may be controlled to be in the program MODE (PGM MODE), and thus their threshold voltage distributions may be increased.

When the program operation for the fourth program state PV4 is completed, the program operation for the fifth program state PV5 is performed. During a programming operation for the fifth program state PV5, memory cells to be programmed to the fifth program state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth program state PV 5. That is, the bit line corresponding to the memory cell to be programmed to the fifth program state PV5 may be controlled to a program MODE (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth program states PV1 to PV4 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Until the program operation for the memory cells to be programmed to the fifth program state PV5 is terminated, the memory cells to be programmed to the sixth program state PV6 adjacent to the fifth program state PV5 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the fifth program state PV 5. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the sixth program state PV6 among memory cells to be programmed to the sixth program state PV6, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the sixth program state PV 6. That is, among the memory cells to be programmed to the sixth program state PV6, the memory cells having a threshold voltage lower than that in the sixth program state PV6 may be controlled to be a program MODE (PGM MODE).

Also, until the program operation for the memory cells to be programmed to the fifth program state PV5 is terminated, the memory cells to be programmed to the remaining program states PV7 may be controlled to be in the program MODE (PGM MODE), and thus their threshold voltage distributions may be increased.

When the program operation for the fifth program state PV5 is completed, the program operation for the sixth program state PV6 is performed. During a programming operation for the sixth program state PV6, memory cells to be programmed to the sixth program state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth program state PV 6. That is, the bit line corresponding to the memory cell to be programmed to the sixth program state PV6 may be controlled to the program MODE (PGM MODE) in which the program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth program states PV1 to PV5 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

Until the program operation for the memory cells to be programmed to the sixth program state PV6 is terminated, the memory cells to be programmed to the seventh program state PV7 adjacent to the sixth program state PV6 may be programmed to a pre-programmed state in which the threshold voltage distributions of the memory cells are higher than that in the sixth program state PV 6. For example, a program permission voltage may be applied to bit lines of memory cells having a threshold voltage lower than that in the seventh program state PV7 among memory cells to be programmed to the seventh program state PV7, and a program inhibition voltage may be applied to bit lines of memory cells having a threshold voltage equal to or higher than that in the seventh program state PV 7. That is, among the memory cells to be programmed to the seventh program state PV7, the memory cells having a threshold voltage lower than that in the seventh program state PV7 may be controlled to be a program MODE (PGM MODE).

When the program operation for the sixth program state PV6 is completed, the program operation for the seventh program state PV7 is performed. During a program operation for the seventh program state PV7, bit lines corresponding to memory cells to be programmed to the seventh program state PV7 may be controlled to a program mode (PGM mode) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth program states PV1 to PV6 may be controlled to a program INHIBIT MODE (INHIBIT MODE) in which a program INHIBIT voltage is applied.

FIG. 16 is a schematic diagram illustrating an embodiment of a memory system.

Referring to fig. 16, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a Personal Digital Assistant (PDA), or a wireless communication device. The memory system 30000 can include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 may control data access operations of the memory device 1100, such as a program operation, an erase operation, or a read operation, under the control of the processor 3100.

Data programmed to memory device 1100 may be output via display 3200 under the control of memory controller 1200.

The radio transceiver 3300 may exchange radio signals through an antenna ANT. For example, the radio transceiver 3300 may convert a radio signal received through the antenna ANT into a signal that may be processed by the processor 3100. Accordingly, the processor 3100 may process a signal output from the radio transceiver 3300 and may transmit the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 may program signals processed by the processor 3100 to the memory device 1100. Further, the radio transceiver 3300 may convert a signal output from the processor 3100 into a radio signal, and output the radio signal to an external device through an antenna ANT. The input device 3400 may be used to input control signals to control the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 may be implemented as a pointing device, such as a touchpad, a computer mouse, a keypad, or a keyboard. The processor 3100 may control the operation of the display 3200 so that data output from the memory controller 1200, data output from the radio transceiver 3300, or data output from the input device 3400 is output via the display 3200.

In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100 or a chip provided separately from the processor 3100. Further, the memory controller 1200 may be implemented by the example of the memory controller 1200 illustrated in fig. 1, and the memory device 1100 may be implemented by the example of the memory device 1100 illustrated in fig. 2.

FIG. 17 is a schematic diagram illustrating an embodiment of a memory system.

Referring to fig. 17, the memory system 40000 may be embodied in a personal computer, a tablet PC, a netbook, an e-reader, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling data processing operations of the memory device 1100.

The processor 4100 may output data stored in the memory device 1100 via the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device, such as a touchpad, a computer mouse, a keypad, or a keyboard.

The processor 4100 may control the overall operation of the memory system 40000 and may control the operation of the memory controller 1200. In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or a chip provided separately from the processor 4100. Further, memory controller 1200 may be implemented by the example of memory controller 1200 illustrated in fig. 1, and memory device 1100 may be implemented by the example of memory device 1100 illustrated in fig. 2.

FIG. 18 is a schematic diagram illustrating an embodiment of a memory system.

Referring to fig. 18, the memory system 50000 may be implemented as an image processing apparatus such as a digital camera, a mobile phone provided with a digital camera, a smart phone provided with a digital camera, or a tablet PC provided with a digital camera.

The memory system 50000 may include a memory device 1100 and a memory controller 1200 capable of controlling data processing operations (e.g., program operations, erase operations, or read operations) of the memory device 1100.

The illustrative image sensor 5200 of the memory system 50000 may convert the optical image to a digital signal and the converted digital signal may be transmitted to the processor 5100 or the memory controller 1200. The converted digital signal may be output via the display 5300 or may be stored in the memory device 1100 through the memory controller 1200 under the control of the processor 5100. Further, data stored in the memory device 1100 can be output via the display 5300 under the control of the processor 5100 or the memory controller 1200.

In embodiments, the memory controller 1200, which is capable of controlling the operation of the memory device 1100, may be implemented as part of the processor 5100 or as a chip provided separately from the processor 5100. Further, the memory controller 1200 may be implemented by the example of the memory controller 1200 illustrated in fig. 1, and the memory device 1100 may be implemented by the example of the memory device 1100 illustrated in fig. 2.

FIG. 19 is a schematic diagram illustrating an embodiment of a memory system.

Referring to fig. 19, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In an embodiment, card interface 7100 may be, but is not limited to, a Secure Digital (SD) card interface or a multimedia card (MMC) interface. Further, memory controller 1200 may be implemented by the example of memory controller 1200 illustrated in fig. 1, and memory device 1100 may be implemented by the example of memory device 1100 illustrated in fig. 2.

Further, the card interface 7100 may interface data exchange between the host 60000 and the memory controller 1200 according to a protocol of the host 60000. In an embodiment, the card interface 7100 may support a Universal Serial Bus (USB) protocol and an inter-chip (IC) -USB protocol. Here, the card interface 7100 may refer to hardware capable of supporting a protocol used by the host 60000, software installed in hardware, or a signal transmission method performed by hardware.

When the memory system 70000 is coupled to a host interface 6200 of a host 60000 (such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, console video game hardware, or a digital set-top box), the host interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

The present disclosure may improve the range of threshold voltage distributions of memory cells during a program operation of a memory device, and may also improve the speed of the program operation of the memory device.

In the embodiments discussed above, all operations may be selectively performed or skipped. In addition, the operations in each embodiment may not always be performed in order, and may be performed randomly. Furthermore, the embodiments disclosed in the specification and the drawings are intended to help those of ordinary skill in the art clearly understand the present disclosure, and are not intended to limit the scope of the present disclosure. In other words, a person of ordinary skill in the art to which the present disclosure pertains will readily understand that various modifications are possible based on the technical scope of the present disclosure.