1. A display device, comprising:

a display panel including a front surface at which an image is displayed and a rear surface opposite to the front surface;

a circuit board connected to the display panel and facing the rear surface of the display panel; and

a heat dissipation layer between the rear surface of the display panel and the circuit board, the heat dissipation layer comprising:

a first heat sink electrically connected to the circuit board; and

a second heat sink spaced apart from the first heat sink in a direction along the display panel.

2. The display device of claim 1, wherein the first heat sink is electrically insulated from the second heat sink.

3. The display device according to claim 1, wherein the circuit board faces the display panel, and the first heat sink is located between the circuit board and the display panel.

4. The display device according to claim 3,

each of the first heat sink and the circuit board has a planar shape, an

The planar shape of the first heat sink corresponds to the planar shape of the circuit board.

5. The display device according to claim 1,

the display panel includes a curved portion at which the display panel is bendable and a flat portion extending from the curved portion, an

The display panel bent at the bent portion sets the bent portion to face the flat portion.

6. The display device according to claim 5, further comprising a driving chip provided on the curved portion of the display panel, and

the display panel bent at the bent portion disposes a portion of the bent portion and the driving chip to face the first heat sink, respectively.

7. The display device according to claim 1, further comprising a flexible circuit film which is bendable and electrically connects the display panel and the circuit board to each other,

wherein the flexible circuit film includes a driving chip.

8. The display device according to claim 7, wherein the driving chip is provided on the bent flexible circuit film and faces the first heat sink.

9. The display device according to claim 1,

the circuit board facing the rear surface of the display panel includes a ground line, an

The first heat sink is electrically connected to the ground line of the circuit board.

10. The display device according to claim 9, further comprising a conductive adhesive film which electrically connects the first heat sink and the ground line of the circuit board to each other.

11. The display device according to claim 10, wherein the circuit board comprises:

a cover layer between the ground wire and the conductive adhesive film;

an opening defined through the cover layer and exposing a portion of the ground wire to an outside of the cover layer to define an exposed portion of the ground wire; and

a step difference compensation pattern located in the opening and electrically connecting the conductive adhesive film to the exposed portion of the ground line.

12. The display device according to claim 11, wherein the step difference compensation pattern forms an interface with both the conductive adhesive film and the exposed portion of the ground line.

13. The display device according to claim 9, further comprising:

a first conductive adhesive film electrically connecting the first heat sink and the ground line of the circuit board to each other; and

a second conductive adhesive film electrically connecting the second heat sink and the ground line of the circuit board to each other,

wherein the second heat sink is electrically connected to the circuit board.

14. The display device according to claim 13,

the second heat sink is spaced apart from the first heat sink by a first distance in the direction along the display panel,

the first and second conductive adhesive films are spaced apart from each other by a second distance in the direction along the display panel, and the second distance is greater than the first distance, an

The first conductive adhesive film faces the display panel, and the first heat sink is positioned between the first conductive adhesive film and the display panel, and the second conductive adhesive film faces the display panel, and the second heat sink is positioned between the second conductive adhesive film and the display panel.

Background

Rollable and/or foldable display panels (hereinafter referred to as "flexible display modules") are being developed. The flexible display module includes a flexible display panel and various functional members. The flexible display panel includes a base member, various functional layers on the base member, and pixels on the base member.

The rollable display device or the foldable display device includes a flexible display module.

Disclosure of Invention

The present disclosure provides a display device having improved electrostatic characteristics.

Embodiments provide a display device including a display panel displaying an image, a circuit board connected to the display panel and facing a rear surface of the display panel, and a heat dissipation layer between the rear surface of the display panel and the circuit board. The heat sink layer includes a first heat sink electrically connected to the circuit board and a second heat sink spaced apart from the first heat sink.

According to one or more embodiments, the heat dissipation layer is divided into a first heat dissipation fin and a second heat dissipation fin spaced apart from each other, and the first heat dissipation fin is electrically connected to a ground of the circuit board. Accordingly, damage to the driving chip due to static electricity introduced through the second heat sink may be reduced or effectively prevented, and static electricity characteristics of the display device may be improved.

Drawings

The above and other advantages of the present disclosure will become apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein:

fig. 1A is a perspective view illustrating an embodiment of a display device;

FIG. 1B is an exploded perspective view illustrating an embodiment of a display device;

FIG. 2A is a cross-sectional view taken along line I-I' shown in FIG. 1B;

FIG. 2B is an exploded perspective view illustrating an embodiment of the cover panel in FIG. 1B;

FIG. 3 is a cross-sectional view taken along line II-II' shown in FIG. 1B;

FIG. 4A is a rear view illustrating an embodiment of a portion of a rear surface of a display device;

FIG. 4B is a rear view illustrating an embodiment of the first and second heat sinks and circuit board of FIG. 4A;

FIG. 5A is a sectional view showing an inverted state of the section taken along the line III-III' shown in FIG. 4A;

fig. 5B is an enlarged cross-sectional view showing an embodiment of a portion BB in fig. 5A;

FIG. 6A is a rear view illustrating an embodiment of a portion of a rear surface of a display device;

FIG. 6B is a rear view illustrating an embodiment of the first and second heat sinks and circuit board of FIG. 6A;

fig. 7A is a sectional view showing an inverted state of the section taken along a line IV-IV' shown in fig. 6A;

fig. 7B is an enlarged cross-sectional view illustrating an embodiment of a portion CC in fig. 7A;

fig. 8 is an exploded perspective view illustrating an embodiment of a display device;

FIG. 9 is a cross-sectional view taken along line V-V' shown in FIG. 8; and

fig. 10A to 10D are cross-sectional views illustrating an embodiment of a manufacturing process of a display device.

Detailed Description

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will be understood that when an element or layer is referred to as being "associated with" another element or layer, such as on, connected to, or coupled to the other element or layer, it can be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "associated with" another element, such as directly on, directly connected to, or directly coupled to the other element or layer, there are no other elements or layers or intervening elements or layers present.

Like reference numerals refer to like elements throughout. In the drawings, the thickness, proportion, and size of components are exaggerated for the purpose of effectively describing technical contents.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. For example, "an element" has the same meaning as "at least one element" unless the context clearly dictates otherwise. "at least one" should not be construed as limiting "one" or "an". "or" means "and/or".

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Spatially relative terms, such as "below," "lower," "above," "upper," and the like, are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.

It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular zone shapes as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. In addition, the sharp corners shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1A is a perspective view illustrating an embodiment of a display device DD, and fig. 1B is an exploded perspective view illustrating an embodiment of a display device DD. Fig. 2A is a sectional view taken along line I-I' shown in fig. 1B, and fig. 2B is an exploded perspective view illustrating an embodiment of the cover panel CVP shown in fig. 1B.

Referring to fig. 1A and 1B, the display device DD may be activated in response to an electrical signal. The display device DD may be applied to various electronic devices. In an embodiment, for example, the display device DD may be applied to an electronic device such as a smart watch, a tablet computer, a notebook computer, a computer, or a smart tv.

The display device DD may display the image IM in the third direction DR3 through the display surface IS disposed in a plane substantially parallel to a plane defined by the first direction DR1 and the second direction DR2 crossing each other. The display surface IS through which the image IM IS displayed may correspond to the front surface of the display device DD. The image IM may include a still image as well as a moving image.

In the present disclosure, the front (or upper) surface and the rear (or lower) surface of the member are defined with respect to the direction in which the image IM is displayed. The front surface and the rear surface are opposite to each other along the third direction DR3, and a normal direction of each of the front surface and the rear surface is substantially parallel to the third direction DR 3.

The distance between the front and rear surfaces along the third direction DR3 may correspond to the thickness of the display device DD and its various components. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are opposite to each other, and thus, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to other directions.

The display device DD may sense an external input applied thereto from outside the display device DD. The external input may include various forms of input provided from outside the display device DD.

In an embodiment, for example, the external input may include an external input (e.g., a hovering input) near or near the display device DD at a predetermined distance and a touch input or contact input through an input tool such as a user's hand. Further, the external input may include various forms, such as force, pressure, temperature, and/or light.

The front surface of the display device DD may be divided into a transmissive area TA (e.g., an image transmissive area) and a bezel area BZA. The image IM may be displayed through the transmissive area TA. The transmissive area TA may be referred to as a display area. The image IM is viewable through the transmissive area TA from outside the display device DD. In a top view (e.g., in a direction opposite to the third direction DR 3), the transmissive area TA may have a quadrangular planar shape with rounded vertices. However, this is merely exemplary, and the transmissive area TA may have various planar shapes, and should not be particularly limited.

The frame area BZA may be defined adjacent to the transmissive area TA. The frame area BZA may have a predetermined color. The image IM may not be displayed by the frame area BZA, and the frame area BZA may be referred to as a non-display area. In the top view, the frame area BZA may surround the transmissive area TA. Therefore, the planar shape of the transmissive area TA may be defined by the shape of the frame area BZA, however, this is merely exemplary. That is, the frame area BZA may be disposed adjacent to only one side of the transmissive area TA, or may be omitted from the display device DD. The display device DD may be implemented in various embodiments, and should not be particularly limited.

As shown in fig. 1B and 2A, the display device DD may include a window WM, a display module DM, a cover panel CVP, and a case EDC. The display module DM may include a display panel DP, an input sensing unit ISP (e.g., an input sensing layer), and an anti-reflection unit RPP (e.g., an anti-reflection layer).

The window WM may comprise a transparent material through which the image IM is transmittable. In an embodiment, for example, the window WM may comprise glass, sapphire, or plastic. The window WM is shown as a single layer, however, it should not be limited thereto or thereby. The window WM may comprise a plurality of layers. Although not shown in the drawings, the frame area BZA of the display device DD may be obtained by providing (such as by printing) a material having a predetermined color on an area of the window WM. As an example, the window WM may include a light-blocking pattern WBM defining a frame region BZA. The light blocking pattern WBM may be a colored organic material layer, and may be disposed or formed by a coating method.

The display panel DP may be a light emitting type display panel, however, should not be particularly limited. In an embodiment, the display panel DP may be an organic light emitting display panel or a quantum dot light emitting display panel. The light emitting layer of the organic light emitting display panel may include an organic light emitting material. The light emitting layer of the quantum dot light emitting display panel may include quantum dots and/or quantum rods. Hereinafter, the organic light emitting display panel will be described as a representative example of the display panel DP.

The input sensing unit ISP may be directly disposed on the display panel DP. According to an embodiment, the input sensing unit ISP may be disposed or formed on the display panel DP through a continuous process. That is, when the input sensing unit ISP is directly disposed on the display panel DP, an adhesive film (e.g., an intermediate layer) may not be disposed between the input sensing unit ISP and the display panel DP.

The display panel DP may generate the image IM, and the input sensing unit ISP may obtain coordinate information on the above-described external input (e.g., touch event).

The antireflection unit RPP can reduce the reflectance of external light incident thereto from the outside of the window WM. The anti-reflection unit RPP may comprise a retarder and a polarizer. The retarder may be a thin film type or a liquid crystal coating type, and may include a lambda/2 retarder and/or a lambda/4 retarder. The polarizer may be of a film type or a liquid crystal coating type. The film-type polarizer may include a stretched synthetic resin film, and the liquid crystal coating-type polarizer may include liquid crystals aligned in a predetermined orientation. The retarder and the polarizer may be implemented as one polarizing film. The antireflection unit RPP may further include a protective film disposed above or below the polarizing film.

The anti-reflection unit RPP may be provided on the input sensing unit ISP. That is, the anti-reflection unit RPP may be disposed between the input sensing unit ISP and the window WM facing each other. The input sensing unit ISP, the antireflective unit RPP and the window WM may be coupled to each other by intervening members (e.g., adhesive members), respectively. A first adhesive film AF1 (e.g., a first adhesive layer) may be disposed between the input sensing unit ISP and the anti-reflection unit RPP, and a second adhesive film AF2 (e.g., a second adhesive layer) may be disposed between the anti-reflection unit RPP and the window WM. Accordingly, the anti-reflection unit RPP may be coupled to the input sensing unit ISP through the first adhesive film AF1, and the window WM may be coupled to the anti-reflection unit RPP through the second adhesive film AF 2.

In embodiments, for example, first adhesive film AF1 and second adhesive film AF2 may be optically clear adhesive ("OCA") films including OCA. However, the first adhesive film AF1 and the second adhesive film AF2 should not be limited thereto or thereby, and may include a common adhesive. In embodiments, for example, first adhesive film AF1 and second adhesive film AF2 can include optically clear resin ("OCR") and/or pressure sensitive adhesive ("PSA") films.

The display module DM may generate and/or display an image IM in response to the electrical signal, and may transmit/receive information regarding an external input. The display module DM may include an active area AA and a peripheral area NAA. The active area AA may be defined as an area through which an image IM provided from the display module DM is transmitted.

The peripheral area NAA may be defined adjacent to the active area AA. In an embodiment, for example, in a plan view, the peripheral zone NAA may surround the active zone AA, however, the peripheral zone NAA may be defined in various shapes, and should not be particularly limited. According to an embodiment, the active area AA of the display module DM may correspond to at least a portion of the transmissive area TA.

The display module DM may further include a circuit board MCB and a driving chip DIC. The circuit board MCB may be electrically connected to the display panel DP. An electrical signal may be supplied from the circuit board MCB to the display panel DP to drive the display panel DP and display an image IM. The circuit board MCB may include a plurality of driving elements. The driving element may include a circuit unit that drives the display panel DP.

The driving chip DIC may be mounted on the display panel DP. The electric signal may be supplied from or through the driving chip DIC to drive the display panel DP and display the image IM. In this case, a portion of the display panel DP where the driving chip DIC is mounted may be bent to be disposed to face the rear surface of the display module DM.

The driving chip DIC may include a driving element, such as a data driving circuit, which drives the pixels of the display panel DP. Fig. 1B shows a structure in which the driving chip DIC is mounted on the display panel DP, however, it should not be limited thereto or thereby. In an embodiment, for example, the driving chip DIC may be mounted on the flexible circuit film FCB disposed between the display panel DP and the circuit board MCB (refer to fig. 8 and 9). A structure in which the driving chip DIC is mounted on the flexible circuit film FCB will be described below with reference to fig. 8 and 9.

The input sensing unit ISP may be electrically connected to the circuit board MCB, however, it should not be limited thereto or thereby. That is, the display module DM may further include a separate one of the flexible circuit films FCB to electrically connect the input sensing unit ISP to the circuit board MCB.

The cover panel CVP may be disposed on a rear surface of the display panel DP. The cover panel CVP may include a heat dissipation layer MS. The heat dissipation layer MS may effectively dissipate heat generated from the display panel DP.

The heat dissipation layer MS may include a first heat sink MS1 (e.g., a first heat dissipation member) and a second heat sink MS2 (e.g., a second heat dissipation member). The first and second heat sinks MS1 and MS2 may be disposed to be spaced apart from each other by a predetermined distance in a direction along the display panel DP. The circuit board MCB faces the display panel DP, and the first heat sink MS1 is located between the circuit board MCB and the display panel DP.

As an example, the first heat sink MS1 and the second heat sink MS2 may include the same conductive material, such as the same metallic material. In an embodiment, for example, the first and second heat sinks MS1 and MS2 may include a metal material having high thermal conductivity, such as copper (Cu), aluminum (Al), gold (Au), or the like, however, should not be limited thereto or thereby. That is, the first and second heat sinks MS1 and MS2 may include metal materials different from each other. Further, the first heat sink MS1 may include a material having a higher electrical conductivity than that of the material of the second heat sink MS 2. In an embodiment, for example, the first heat sink MS1 may include gold and the second heat sink MS2 may include copper.

The cover panel CVP may further include a first layer PF and a second layer CH each disposed between the heat dissipation layer MS and the display panel DP. The first layer PF may be a polyimide ("PI") film. The first layer PF may be a base member or layer on which the first and second heat sinks MS1 and MS2 are disposed. Adhesive layers may also be disposed between the first and second heat sinks MS1 and MS2 and the first layer PF, respectively. Thus, the first heat sink MS1 and the second heat sink MS2 may each be attached to the first layer PF by an adhesive layer. The first layer PF may be common to each of the first and second heat sinks MS1 and MS 2.

The second layer CH may be an impact absorbing layer. The second layer CH may be disposed on the rear surface of the display panel DP, and may improve the impact resistance of the display device DD. In the embodiment, the second layer CH is disposed between the display panel DP and the first layer PF, however, it should not be limited thereto or thereby. In an embodiment, the second layer CH may be disposed between the first layer PF and the heat dissipation layer MS.

According to the present disclosure, since the heat dissipation layer MS is disposed on the rear surface of the display panel DP, heat generated from the display panel DP may be easily dissipated to the outside of the display device DD through the heat dissipation layer MS.

In an embodiment, at least one of the first layer PF and the second layer CH may be omitted, or another functional layer may be added to the cover panel CVP in addition to the first layer PF and the second layer CH.

The cover panel CVP may be fixed to the rear surface of the display panel DP by an adhesive layer. The adhesive layer may include a pressure sensitive adhesive ("PSA"), an optically clear adhesive ("OCA"), or an optically clear resin ("OCR").

The housing EDC may accommodate the display module DM. The housing EDC may be coupled to the window WM and may define the exterior of the display device DD. The case EDC may absorb an impact applied thereto from the outside of the display device DD, and may prevent impurities/moisture from entering the display module DM to protect components contained in the case EDC. In an embodiment, the housing EDC may be an assembly of a plurality of separately provided receiving members.

Fig. 3 is a sectional view taken along line II-II' shown in fig. 1B.

Referring to fig. 3, the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layer, the semiconductor layer, and the conductive layer may be disposed or formed by a coating or deposition process. The insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography process. The semiconductor pattern, the conductive pattern, and the signal line included in the circuit element layer 110-2, and the display element layer 110-3 may be disposed or formed on the base layer 110-1. The encapsulation layer 110-4 may be disposed or formed to cover the display element layer 110-3.

The base layer 110-1 may include a synthetic resin film. The synthetic resin film may include a heat curable resin. The base layer 110-1 may have a multi-layer structure. In an embodiment, for example, the base layer 110-1 may have a three-layer structure of a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material for the synthetic resin layer should not be particularly limited. The synthetic resin layer may include at least one of an acrylic-based resin, a methacrylic-based resin, polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a silicone-based resin, a polyamide-based resin, and a perylene-based resin. The base layer 110-1 may include a glass substrate or an organic/inorganic composite substrate.

At least one inorganic layer may be disposed or formed on the upper surface of the base layer 110-1. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be provided or formed by a plurality of layers. The inorganic layer may form a barrier layer and/or a buffer layer BFL. Referring to fig. 3, the display panel DP may include a buffer layer BFL.

The buffer layer BFL may increase a coupling force between the base layer 110-1 and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer stacked on each other.

The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, however, should not be limited thereto or thereby. The semiconductor pattern may include amorphous silicon or an oxide semiconductor.

As shown in fig. 3, the first semiconductor pattern of the first transistor 111 and the second semiconductor pattern of the second transistor 112 may be disposed on the buffer layer BFL. The first semiconductor pattern may include a first source S1, a first channel a1, and a first drain D1, and the second semiconductor pattern may include a second source S2, a second channel a2, and a second drain D2. In a direction along the base layer 110-1, the first channel a1 may be disposed between the first source S1 and the first drain D1, and the second channel a2 may be disposed between the second source S2 and the second drain D2. Fig. 3 shows a part of the connection signal line SCL. Although not shown in the drawings, the connection signal line SCL may be connected to the second drain D2 of the second transistor 112 in a plan view.

The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the plurality of semiconductor patterns. The first insulating layer 10 may be an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may have a silicon oxide layer of a single-layer structure. The first insulating layer 10 and an insulating layer of the circuit element layer 110-2 described later may be inorganic layers and/or organic layers, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

The first gate G1 of the first transistor 111 and the second gate G2 of the second transistor 112 may be disposed on the first insulating layer 10. The first and second gates G1 and G2 may overlap or correspond to the first and second channels a1 and a2, respectively.

The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the first and second gates G1 and G2. The second insulating layer 20 may be an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. In an embodiment, the second insulating layer 20 may have a silicon oxide layer of a single-layer structure.

The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the second gate G2 of the second transistor 112. A portion of the second gate G2 and a portion of the upper electrode UE overlapping the portion of the second gate G2 may form part of a capacitor.

The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE. In an embodiment, the third insulating layer 30 may have a silicon oxide layer of a single-layer structure. The first connection electrode CNE1 may be disposed on the third insulation layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a first contact hole CNT-1, the first contact hole CNT-1 being defined to extend through each of the first, second, and third insulating layers 10, 20, and 30.

The fourth insulation layer 40 may be disposed on the third insulation layer 30. The fourth insulating layer 40 may have a silicon oxide layer of a single-layer structure. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CNT-2, the second contact hole CNT-2 being defined to extend through each of the fourth and fifth insulating layers 40 and 50.

The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the second connection electrode CNE 2. The sixth insulating layer 60 may be an organic layer. The first electrode AE may be disposed on the sixth insulating layer 60. The first electrode AE may be connected to the second connection electrode CNE2 through a third contact hole CNT-3, the third contact hole CNT-3 being defined to extend through the sixth insulating layer 60.

An opening 70-OP may be defined to extend through the pixel defining layer 70. The first electrode AE may be exposed to the outside of the pixel defining layer 70 at the opening 70-OP of the pixel defining layer 70 or through the opening 70-OP of the pixel defining layer 70.

The active area AA (refer to fig. 1B) may include a light-emitting area PXA (e.g., a plurality of light-emitting areas PXA) disposed in plurality and a non-light-emitting area NPXA (e.g., a plurality of non-light-emitting areas NPXA) disposed in plurality defined adjacent to the light-emitting area PXA. In a top view, a non-light emitting region NPXA may surround the light emitting region PXA. Each of the light emitting regions PXA may be defined to correspond to a portion of the first electrode AE exposed to the outside of the pixel defining layer 70 through the opening 70-OP.

The hole control layer HCL may be generally disposed in the light emitting region PXA and the non-light emitting region NPXA. The hole control layer HCL may include a hole transport layer and may also include a hole injection layer. The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the opening 70-OP. That is, the light emitting layer EML may be disposed or formed in each pixel of the display panel DP after being divided into a plurality of portions.

The electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may comprise an electron transport layer and may also comprise an electron injection layer. The hole control layer HCL and the electron control layer ECL may be disposed or formed in the light emitting region PXA together, such as by using an opening mask.

The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have an overall shape, and may be commonly disposed in each light emitting region PXA.

The capping layer 80 may be disposed on the second electrode CE. The cap layer 80 may include an organic material. The cover layer 80 may protect the second electrode CE from a process (such as a sputtering process) of disposing the display device DD, and may improve the light emitting efficiency of the light emitting element 114 or the display element. In an embodiment, the cap layer 80 may be omitted.

The encapsulation layer 110-4 may be disposed on the display element layer 110-3. The encapsulation layer 110-4 may include a first inorganic layer 91, an organic layer 92, and a second inorganic layer 93. The first and second inorganic layers 91 and 93 may protect the display element layer 110-3 from moisture and oxygen, and the organic layer 92 may protect the display element layer 110-3 from impurities such as dust particles. The first inorganic layer 91 and the second inorganic layer 93 may include one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. In an embodiment, the first and second inorganic layers 91 and 93 may include a titanium oxide layer or an aluminum oxide layer. The organic layer 92 may include an acrylic-based organic layer, however, should not be particularly limited.

The input sensing unit ISP may include a base insulating layer 120-1, a first conductive layer 120-2, a sensing insulating layer 120-3 (e.g., an intermediate insulating layer), a second conductive layer 120-4, and a cover insulating layer 120-5. After the display panel DP is disposed or formed, the input sensing unit ISP may be disposed or formed through a continuous process, however, it should not be limited thereto or thereby.

The base insulating layer 120-1 may be directly disposed on the display panel DP. In an embodiment, for example, the base insulating layer 120-1 may be in contact with (e.g., form an interface with) the second inorganic layer 93. The base insulating layer 120-1 may have a single-layer structure or a multi-layer structure. In an embodiment, the base insulating layer 120-1 may be omitted. In an embodiment, the base insulating layer 120-1 may be disposed or formed as a separate base layer, and the separate base layer may be coupled to the display panel DP by an intervening member (such as an adhesive member).

Each of the first and second conductive layers 120-2 and 120-4 may have a single layer structure or a multi-layer structure of layers stacked along the third direction DR 3. The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, alloys thereof, or combinations thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide ("ZnO"), indium tin zinc oxide ("ITZO"). In addition, the transparent conductive layer may include a conductive polymer (e.g., poly (3, 4-ethylenedioxythiophene) ("PEDOT")), metal nanowires, and graphene.

The conductive layer having a multi-layer structure may include a plurality of metal layers. The metal layer may have a three-layer structure of titanium/aluminum/titanium. The conductive layer of the multilayer structure may include at least one metal layer and at least one transparent conductive layer.

Each of the first conductive layer 120-2 and the second conductive layer 120-4 may include a conductive pattern forming a sensing electrode. The input sensing unit ISP may obtain information about an external input based on a change in capacitance between the sensing electrodes.

The sensing insulation layer 120-3 may be disposed between the first conductive layer 120-2 and the second conductive layer 120-4, and may cover the first conductive layer 120-2. A portion of the second conductive layer 120-4 may be electrically connected to a portion of the first conductive layer 120-2 through a contact hole defined to extend through the sensing insulation layer 120-3. The cover insulating layer 120-5 may be disposed on the sensing insulating layer 120-3 and may cover the second conductive layer 120-4.

In an embodiment, at least one of the sensing insulating layer 120-3 and the capping insulating layer 120-5 may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

In an embodiment, at least one of the sensing insulating layer 120-3 and the capping insulating layer 120-5 may include an organic layer. The organic layer may include at least one of an acrylic-based resin, a methacrylic-based resin, polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin.

Fig. 4A is a rear view illustrating an embodiment of a portion of a rear surface of the display device DD, and fig. 4B is a rear view illustrating embodiments of the first and second heat sinks MS1 and MS2 and the circuit board MCB illustrated in fig. 4A. Fig. 5A is a sectional view taken along line III-III' shown in fig. 4A, and fig. 5B is an enlarged sectional view showing an embodiment of a portion BB shown in fig. 5A.

Referring to fig. 4A, 4B, 5A, and 5B, a cover panel CVP may be disposed on a rear surface of the display panel DP. The rear surface is opposite to the front surface of the display panel DP in the third direction DR 3. The cover panel CVP may include a heat dissipation layer MS, a first layer PF and a second layer CH.

The heat dissipation layer MS may include a first heat sink MS1 and a second heat sink MS 2. The first and second fins MS1 and MS2 may be disposed to be spaced apart from each other along a plane defined by the first and second directions DR1 and DR2 intersecting each other. In an embodiment, first fin MS1 and second fin MS2 may be spaced apart from each other by a first distance dt 1. The first distance dt1 should not be particularly limited. A gap GP may be defined between the first fin MS1 and the second fin MS 2. Referring to fig. 4A, for example, the gap GP may not overlap the driving chip DIC in a plan view. In the curved display panel DP, the first heat sink MS1 may be disposed to overlap or correspond to the driving chip DIC and the circuit board MCB. In an embodiment, the first heat sink MS1 may have a planar shape corresponding to the circuit board MCB. That is, the first heat radiating fin MS1 may have an amorphous shape, and the shape of the first heat radiating fin MS1 should not be particularly limited.

The display panel DP may include a flat portion FP and a curved portion BP where the display panel DP is bendable. The flat portion FP extends from the curved portion BP. The flat portion FP may be a portion of the display panel DP that is not bendable or remains flat when the bent portion BP is bent. The curved portion BP may be curved to face the flat portion FP along the third direction DR3 (fig. 5A). The driving chip DIC may be mounted on the curved portion BP of the display panel DP. The display panel DP bent at the bent portion BP sets the bent portion BP to face the flat portion FP.

Referring to fig. 4A, the first heat sink MS1 may be disposed to overlap the driving chip DIC and the bent portion BP of the display panel DP. The display panel DP (fig. 4B) which is not bent or flat disposes the driving chip DIC and the circuit board MCB so as not to overlap the heat dissipation layer MS. The curved display panel DP (fig. 4A) sets the driving chip DIC and the circuit board MCB to face the heat dissipation layer MS.

The curved display panel DP (fig. 4A) sets the second heat sink MS2 not to overlap the driving chip DIC and the curved portion BP of the display panel DP. Fig. 4A shows a structure in which the second heat sink MS2 partially overlaps the circuit board MCB, however, the second heat sink MS2 and the circuit board MCB should not be limited to this structure. In an embodiment, for example, the curved display panel DP (fig. 4A) may dispose the second heat sink MS2 not to overlap the circuit board MCB.

The display device DD may also include a conductive adhesive film CAF (e.g., a conductive adhesive layer) to attach the first heat sink MS1 to the circuit board MCB. The circuit board MCB may be fixed to the rear surface of the first heat sink MS1 by a conductive adhesive film CAF. Some of the conductive wires or signal lines (e.g., ground lines GRL shown in fig. 5B) of the circuit board MCB may be electrically connected to the first heat sink MS1 via the conductive adhesive film CAF. That is, the circuit board MCB may be electrically connected to the first heat sink MS1 and may form an electrostatic path. The second heat sink MS2 may be disposed spaced apart from the first heat sink MS1 (e.g., electrically insulated from the first heat sink MS 1), and thus, the second heat sink MS2 may be electrically insulated from the circuit board MCB electrically connected to the first heat sink MS 1.

The conductive adhesive film CAF may be a double-sided adhesive film. Accordingly, the conductive adhesive film CAF may be attached to each of the rear surface of the first heat sink MS1 and the rear surface of the circuit board MCB. Referring to fig. 5A and 5B, the display panel DP bent at the bent portion BP sets the rear surface of the first heat sink MS1 to face the rear surface of the circuit board MCB.

As shown in fig. 5B, the conductive adhesive film CAF may include a first conductive film CF1 (e.g., a first conductive pattern), a first conductive adhesive CA1 (e.g., a first conductive adhesive pattern), and a second conductive adhesive CA2 (e.g., a second conductive adhesive pattern). The first conductive film CF1 may include a conductive fabric or a metal film as its base film. The first conductive adhesive CA1 may be disposed between the first conductive film CF1 and the rear surface of the first heat sink MS1, and the second conductive adhesive CA2 may be disposed between the first conductive film CF1 and the rear surface of the circuit board MCB.

Each of the first and second conductive adhesives CA1 and CA2 may include a conductive adhesive material. In an embodiment, for example, each of the first and second conductive adhesives CA1 and CA2 may be a film provided or formed by distributing metal particles of gold, silver, platinum, nickel, copper, or carbon in a synthetic resin. The synthetic resin may include materials of epoxy, silicon, polyimide, or polyurethane.

The conductive adhesive film CAF may be attached to each of the rear surface of the first heat sink MS1 and the rear surface of the circuit board MCB by a first conductive adhesive CA1 and a second conductive adhesive CA2, respectively.

The circuit components CM such as the control chip, the plurality of passive elements, the plurality of active elements, and the like may be provided by being mounted on the circuit board MCB, for example. The circuit board MCB may include a rear surface (e.g., visible in fig. 4B) facing the first heat sink MS1 in the curved display panel DP (fig. 4A, 5A, and 5B). An upper surface of the circuit board MCB (e.g., visible in fig. 4A) may be opposite to a rear surface of the circuit board MCB.

The circuit board MCB may include a ground line GRL, a first cover layer CVL1, a second cover layer CVL2, and a step difference compensation film SCF (e.g., a step difference compensation pattern). The first and second cover layers CVL1 and CVL2 may include an insulating material. The upper surface of the circuit board MCB may be defined by the first surface of the first cover layer CVL1, however, should not be limited thereto or thereby. The circuit board MCB may include a plurality of cover layers in addition to the first cover layer CVL1 and the second cover layer CVL 2. In this case, the upper surface of the circuit board MCB may be defined by an upper surface of an outermost one of the cover layers (e.g., the cover layer farthest from the flat portion FP of the display panel DP). The ground line GRL may be disposed on a second surface of the first cover layer CVL1 opposite to the first surface of the first cover layer CVL 1. The ground line GRL may be a copper line and may receive a ground voltage.

The ground line GRL may be covered by a second cover layer CVL 2. The second clad layer CVL2 may be provided with a first opening OP1 and a second opening OP2, and portions of the ground wire GRL are exposed through the first opening OP1 and the second opening OP 2. That is, each of the first opening OP1 and the second opening OP2 is defined by the second clad layer CVL2, and exposes a portion of the ground wire GRL to the outside of the second clad layer CVL2 to define an exposed portion of the ground wire GRL. Other wires or signal lines may be provided on the second surface of the first cover layer CVL1 in addition to the ground line GRL, however, the other wires or signal lines are omitted in fig. 5B for convenience of explanation.

The step difference compensation film SCF may be provided corresponding to each of the first opening OP1 and the second opening OP2, and may be electrically connected to the ground line GRL at the first opening OP1 and the second opening OP 2. The step difference compensation film SCF forms an interface with both the conductive adhesive film CAF and the exposed portion of the ground line GRL. Further, the step difference compensation film SCF may compensate for a step difference occurring in the second clad layer CVL2 caused by the first opening OP1 and the second opening OP 2.

The step difference compensation film SCF may include a second conductive film CF2 (e.g., a second conductive pattern) and a third conductive adhesive CA3 (e.g., a third conductive adhesive pattern). The second conductive film CF2 may be used as the base film of the step difference compensation film SCF. The second conductive film CF2 may have a thickness sufficient to compensate for a step difference occurring in the second cover layer CVL 2. The second conductive film CF2 may include a material having conductivity. In an embodiment, for example, the second conductive film CF2 may include the same material as that of the first conductive film CF 1. The third conductive adhesive CA3 may be disposed between the second conductive film CF2 and the ground line GRL. The third conductive adhesive CA3 may include a conductive adhesive material. In an embodiment, for example, the third conductive adhesive CA3 may include the same material as that of the first and second conductive adhesives CA1 and CA2 or be formed of the same material as that of the first and second conductive adhesives CA1 and CA 2.

In an embodiment, the circuit board MCB may further include a protection metal layer PL covering a portion of the ground line GRL exposed through the first and second openings OP1 and OP 2. The protection metal layer PL may serve to reduce or effectively prevent the ground line GRL from being oxidized or corroded. In an embodiment, for example, the protective metal layer PL may include a metal material that is resistant to oxidation and corrosion, such as gold (Au).

In the case where the protective metal layer PL is provided, the step difference compensation film SCF may be attached to the protective metal layer PL by the third conductive adhesive CA 3. When the protective metal layer PL is omitted, the step difference compensation film SCF may be directly attached to the ground line GRL.

The second conductive film CF2 of the step difference compensation film SCF may be attached to the second conductive adhesive CA2 of the conductive adhesive film CAF. Accordingly, the conductive adhesive film CAF may be electrically connected to the ground line GRL through the step difference compensation film SCF. Accordingly, the first heat sink MS1 and the ground line GRL are electrically connected to each other through the conductive adhesive film CAF together with the step difference compensation film SCF, and therefore, an electrostatic path may be provided or formed between the cover panel CVP and the circuit board MCB.

Accordingly, when static electricity is generated, the static electricity may be dissipated through the static electricity path, and thus, damage to the circuit components CM mounted on the circuit board MCB or the driving chip DIC mounted on the display panel DP due to the static electricity may be reduced or effectively prevented. In particular, since the first heat sink MS1 is separated from the second heat sink MS2 (e.g., electrically insulated from the second heat sink MS 2), damage to the circuit components CM mounted on the circuit board MCB or the driving chip DIC mounted on the display panel DP due to static electricity introduced through the second heat sink MS2 may be reduced or effectively prevented.

As shown in fig. 5B, the second layer CH of the cover panel CVP may include a cushion layer CH1 and an embossed structure layer CH2 (e.g., an embossed layer). The buffer layer CH1 is disposed facing the display panel DP, and the embossed structure layer CH2 is located between the buffer layer CH1 and the display panel DP. Buffer layer CH1 may include a porous structure having elasticity. The buffer layer CH1 may include synthetic resin foam. In an embodiment, for example, buffer layer CH1 may include at least one of acrylonitrile butadiene styrene ("ABS"), polyurethane ("PU"), polyethylene ("PE"), ethylene vinyl acetate ("EVA"), and polyvinyl chloride ("PVC").

The embossed structure layer CH2 may include a plurality of protrusions protruding in the third direction DR 3. The protrusions may have an embossed shape defined by peaks and valleys alternating with each other in a direction along the display panel DP. The protrusion may protrude toward the display panel DP. Each protrusion may have a semicircular shape when viewed in cross section. However, each protrusion may have a triangular shape, and should not be particularly limited. The embossed structure layer CH2 may include an elastic material. Accordingly, the embossed structure layer CH2 and the cushion layer CH1 may improve the impact resistance of the cover panel CVP.

In an embodiment, the embossed structure layer CH2 may include a light blocking material. The embossed structure layer CH2 may reduce or effectively prevent components disposed on the rear surface of the display panel DP from being visible from the outside of the display panel DP due to the inclusion of the light blocking material.

Fig. 6A is a rear view illustrating an embodiment of a portion of a rear surface of the display device DD, and fig. 6B is a rear view illustrating embodiments of the first and second heat sinks MS1 and MS2 and the circuit board MCB illustrated in fig. 6A. Fig. 7A is a sectional view taken along a line IV-IV' shown in fig. 6A, and fig. 7B is an enlarged sectional view showing an embodiment of a portion CC shown in fig. 7A. In fig. 6A, 6B, 7A, and 7B, the same reference numerals denote the same elements in fig. 4A to 5B, and thus, detailed descriptions of the same elements will be omitted in fig. 6A to 7B.

Referring to fig. 6A to 7B, a cover panel CVP may be disposed on a rear surface of the display panel DP. The cover panel CVP may include a heat dissipation layer MS, a first layer PF and a second layer CH.

The heat dissipation layer MS may include a first heat sink MS1 and a second heat sink MS 2. The first and second fins MS1 and MS2 may be disposed to be spaced apart from each other along a plane defined by the first and second directions DR1 and DR2 intersecting each other. In an embodiment, first fin MS1 and second fin MS2 may be disposed a first distance dt1 from each other. The first distance dt1 should not be particularly limited. A gap GP may be defined between the first fin MS1 and the second fin MS 2. Referring to fig. 6A, for example, the gap GP may not overlap the driving chip DIC in a plan view.

In the curved display panel DP (fig. 6A), the first heat sink MS1 may be disposed to overlap or correspond to the driving chip DIC and the circuit board MCB. In an embodiment, the first heat sink MS1 may have a planar quadrangular shape and may partially overlap the circuit board MCB. The first heat sink MS1 may be disposed to overlap the driving chip DIC and the bent portion BP of the display panel DP.

The curved display panel DP (fig. 6A) sets the second heat sink MS2 not to overlap the driving chip DIC and the curved portion BP of the display panel DP. Fig. 7A shows a structure in which the display panel DP is bent and the second heat sink MS2 is provided to partially overlap the circuit board MCB, however, it should not be limited thereto or thereby. In an embodiment, for example, the curved display panel DP may dispose the second heat sink MS2 so as not to overlap the circuit board MCB.

The display device DD may further include a first conductive adhesive film CAF1 (e.g., a first conductive adhesive layer) and a second conductive adhesive film CAF2 (e.g., a second conductive adhesive layer). The first conductive adhesive film CAF1 faces the display panel DP, and the first heat sink MS1 is located between the first conductive adhesive film CAF1 and the display panel DP, and the second conductive adhesive film CAF2 faces the display panel DP, and the second heat sink MS2 is located between the second conductive adhesive film CAF2 and the display panel DP.

The circuit board MCB may be fixed to the rear surface of the first heat sink MS1 by a first conductive adhesive film CAF1, and may be fixed to the rear surface of the second heat sink MS2 by a second conductive adhesive film CAF 2. Some of the conductive lines or signal lines (e.g., ground lines GRL shown in fig. 7B) of the circuit board MCB may be electrically connected to the first heat sink MS1 via the first conductive adhesive film CAF 1. That is, the circuit board MCB may be electrically connected to the first heat sink MS1 and may form an electrostatic path. The second heat sink MS2 may be electrically connected to the ground line GRL of the circuit board MCB through the second conductive adhesive film CAF 2. That is, the circuit board MCB may be electrically connected to the second heat sink MS2 to form an electrostatic path.

Each of the first conductive adhesive film CAF1 and the second conductive adhesive film CAF2 may be a double-sided adhesive film. Accordingly, the first conductive adhesive film CAF1 may be attached to each of the rear surface of the first heat sink MS1 and the rear surface of the circuit board MCB, and the second conductive adhesive film CAF2 may be attached to each of the rear surface of the second heat sink MS2 and the rear surface of the circuit board MCB.

As shown in fig. 7B, the first conductive adhesive film CAF1 may include a first conductive film CF1-1, a first conductive adhesive CA1-1, and a second conductive adhesive CA 2-1. The first conductive adhesive CA1-1 may be disposed between the first conductive film CF1-1 and the rear surface of the first heat sink MS1, and the second conductive adhesive CA2-1 may be disposed between the first conductive film CF1-1 and the rear surface of the circuit board MCB. Accordingly, the first conductive adhesive film CAF1 may be attached to each of the rear surface of the first heat sink MS1 and the rear surface of the circuit board MCB by the first conductive adhesive CA1-1 and the second conductive adhesive CA 2-1.

The second conductive adhesive film CAF2 may include a first conductive film CF1-2, a first conductive adhesive CA1-2, and a second conductive adhesive CA 2-2. The first conductive adhesive CA1-2 may be disposed between the first conductive film CF1-2 and the rear surface of the second heat sink MS2, and the second conductive adhesive CA2-2 may be disposed between the first conductive film CF1-2 and the rear surface of the circuit board MCB. Accordingly, the second conductive adhesive film CAF2 may be attached to each of the rear surface of the second heat sink MS2 and the rear surface of the circuit board MCB by the first conductive adhesive CA1-2 and the second conductive adhesive CA 2-2.

The first and second conductive adhesive films CAF1 and CAF2 may be disposed to correspond to a gap GP between the first and second heat sinks MS1 and MS2, and may be spaced apart from each other (e.g., disconnected from each other) by the gap GP. In an embodiment, first and second heat sinks MS1 and MS2 may be spaced apart from each other by a first distance dt1, and first and second conductive adhesive films CAF1 and CAF2 may be spaced apart from each other by a second distance dt 2. In an embodiment, second distance dt2 may be equal to or greater than first distance dt 1.

The circuit board MCB may include a first step difference compensation film SCF1 (e.g., a first step difference compensation pattern) and a second step difference compensation film SCF2 (e.g., a second step difference compensation pattern). The first step difference compensation film SCF1 may be provided corresponding to the first opening OP1, and may be electrically connected to the ground line GRL. The second step difference compensation film SCF2 may be provided corresponding to the second opening OP2, and may be electrically connected to the ground line GRL.

The first step difference compensation film SCF1 may include a second conductive film CF2-1 and a third conductive adhesive CA 3-1. The first conductive adhesive film CAF1 may be electrically connected to the ground line GRL via the first step difference compensation film SCF 1. Accordingly, the first heat sink MS1 and the ground line GRL may be electrically connected to each other through the first conductive adhesive film CAF1 and the first step difference compensation film SCF1, and thus an electrostatic path may be formed.

The second step difference compensation film SCF2 may include a second conductive film CF2-2 and a third conductive adhesive CA 3-2. The second conductive adhesive film CAF2 may be electrically connected to the ground line GRL via the second step difference compensation film SCF 2. Accordingly, the second heat sink MS2 and the ground line GRL may be electrically connected to each other through the second conductive adhesive film CAF2 and the second step difference compensation film SCF2, and thus an electrostatic path may be formed.

Since the electrostatic path is provided to each of the first and second heat sinks MS1 and MS2 in the structure in which the first and second heat sinks MS1 and MS2 are spaced apart from each other, the electrostatic dissipation characteristic of the display device DD may be improved. In particular, since the first heat sink MS1 is electrically separated from the second heat sink MS2, damage to the driving chip DIC mounted on the display panel DP due to static electricity introduced through the second heat sink MS2 may be reduced or effectively prevented.

Fig. 8 is an exploded perspective view illustrating an embodiment of the display device DD, and fig. 9 is a sectional view taken along a line V-V' shown in fig. 8. In fig. 8, the same reference numerals denote the same elements in fig. 1B to 7B, and thus, detailed descriptions of the same elements will be omitted.

Referring to fig. 8 and 9, the display device DD may further include a flexible circuit film FCB disposed between the display panel DP and the circuit board MCB. The circuit board MCB may be electrically connected to the display panel DP through the flexible circuit film FCB. The flexible circuit film FCB may be connected to the display panel DP at a first end of the flexible circuit film FCB, and the flexible circuit film FCB may be connected to the circuit board MCB at a second end of the flexible circuit film FCB opposite to the first end thereof.

The display panel DP may be connected to the flexible circuit film FCB at the peripheral area NAA of the display panel DP, such as by an adhesive process. The driving chip DIC may be mounted on the flexible circuit film FCB. A flexible circuit film FCB bent to surround a side surface of the display panel DP, a driving chip DIC, and a circuit board MCB coupled to the flexible circuit film FCB may be disposed on a rear surface of the display panel DP. The bent flexible circuit film FCB disposes the driving chip DIC and a portion of the flexible circuit film FCB to face the first heat sink MS 1.

The electrical connection relationship between the first heat sink MS1 and the circuit board MCB is substantially the same as the electrical connection relationship between the first heat sink MS1 and the circuit board MCB described with reference to fig. 4A to 5B, and therefore, the details thereof will be omitted. In an embodiment, the electrical connection relationship between the heat dissipation layer MS and the circuit board MCB may be substantially the same as the electrical connection relationship between the heat dissipation layer MS and the circuit board MCB described with reference to fig. 6A to 7B, and thus, the details thereof will be omitted.

Fig. 10A to 10D are cross-sectional views illustrating an embodiment of a manufacturing process of the display device DD.

Referring to fig. 10A, the manufacturing process of the display device DD may include providing the display module DM as described above as a completed assembly. The completed display module DM may include a display panel DP (refer to fig. 1B) and an input sensing unit ISP (refer to fig. 1B). For convenience of explanation, a detailed configuration of the display module DM is omitted in fig. 10A.

Referring to fig. 10B, a preliminary cover panel P-CVP may be provided on a rear surface of the display module DM. The preliminary cover panel P-CVP may be coupled to the rear surface of the display module DM, such as by an adhesive film.

The preliminary cover panel P-CVP may include a preliminary heat dissipation layer P-MS, a first layer PF, and a second layer CH. The preliminary heat dissipation layer P-MS may be disposed on the rear surface of the first layer PF, and the second layer CH may be disposed on the front surface or the upper surface of the first layer PF. The preliminary heat dissipation layer P-MS may include a metal material. In an embodiment, for example, the preliminary heat dissipation layer P-MS may include a metal material having high thermal conductivity, such as copper (Cu), aluminum (Al), gold (Au), or the like.

The first layer PF may be a polyimide ("PI") film. An adhesive layer may be further disposed between the first layer PF and the preliminary heat dissipation layer P-MS. The second layer CH may be an impact absorbing layer. The second layer CH may be disposed between the display module DM and the first layer PF.

Referring to fig. 10C, the method of manufacturing the display device DD may include removing a portion of the preliminary heat dissipation layer P-MS along a cutting line CL defined in the preliminary heat dissipation layer P-MS, such as by cutting in a cutting process. The cutting line CL may correspond to a gap GP between portions of the heat dissipation layer MS. The cutting process may include irradiating a laser beam along the cutting line CL. The laser unit LD may be disposed adjacent to the rear surface of the preliminary cover panel P-CVP, and may irradiate a laser beam to the preliminary heat dissipation layer P-MS while moving along the cutting line CL.

As shown in fig. 10C and 10D, the preliminary heat dissipation layer P-MS may be divided into a first heat dissipation fin MS1 and a second heat dissipation fin MS2 by a laser beam. Accordingly, a heat dissipation layer MS including a first heat sink MS1 and a second heat sink MS2 may be provided within the cover panel CVP.

In fig. 10A to 10D, a method of irradiating a laser beam is described as a method of forming the first heat sink MS1 and the second heat sink MS2 from the preliminary heat sink layer P-MS, however, it should not be limited thereto or thereby. In an embodiment, the first and second heat sinks MS1 and MS2 are each manufactured as a separate sheet and are respectively provided to the cover panel CVP to omit a cutting process.

Although embodiments have been described, it is to be understood that the present disclosure is not limited to those embodiments, but various changes and modifications may be made by one of ordinary skill in the art within the spirit and scope of the present disclosure as hereinafter claimed. Accordingly, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the invention should be determined from the following claims.