1. A clock management method is applied to a target component, wherein the target component is connected with a host end through a cable, and the method comprises the following steps:

acquiring output clock parameters prestored by the host computer, cable parameters prestored by the cable and demand clock parameters prestored by the target component;

determining a clock mode according to the output clock parameter, the cable parameter and the demand clock parameter, and updating the firmware of the PCIe switcher of the target component based on the clock mode; wherein the clock modes include a homologous mode and a non-homologous mode;

sending the clock mode to the host side so that the host side updates firmware of a retimer and default clock configuration of a basic input output system based on the clock mode;

wherein the method further comprises: obtaining a demand clock parameter of the target component based on the inherent property test of the target component; correspondingly, the host side obtains the output clock parameters of the host side based on the inherent property test of the host side.

2. The clock management method according to claim 1, wherein the first memory corresponding to the host side comprises a first memory space and a second memory space, the first memory space is used for storing firmware of a baseboard management controller at the host side, and the second memory space is used for storing homologous mode firmware and non-homologous mode firmware of the retimer;

the second storage corresponding to the target assembly comprises a third storage space and a fourth storage space, the third storage space is used for storing the firmware of the baseboard management controller of the target assembly, and the fourth storage space is used for storing the homologous mode firmware and the nonhomologous mode firmware of the PCIe switcher of the target assembly.

3. The clock management method of claim 2, wherein the updating the firmware of the PCIe switch of the target component based on the clock mode comprises:

acquiring first firmware corresponding to the clock mode of the PCIe switcher of the target component from the fourth storage space, and updating the first firmware to a third storage corresponding to the PCIe switcher of the target component;

correspondingly, the host side updates the firmware of the retimer based on the clock mode, including:

and the host side acquires second firmware corresponding to the clock mode of the retimer from the second storage space and updates the second firmware to a fourth memory corresponding to the retimer.

4. The clock management method of claim 1, wherein determining a clock mode from the output clock parameter, the cable parameter, and the demand clock parameter comprises:

judging whether a homologous mode is feasible or not according to the output clock parameter, the cable parameter and the demand clock parameter;

if so, determining the clock mode as a homologous mode;

if not, determining that the clock mode is a non-homologous mode.

5. The clock management method of claim 1, wherein prior to updating the firmware of the PCIe switch of the target component based on the clock mode, further comprising:

judging whether the current clock mode is consistent with the clock mode; if not, executing the step of updating the firmware of the PCIe switcher of the target component based on the clock mode;

correspondingly, before the host side updates the firmware of the retimer based on the clock mode, the method further includes:

the host side judges whether the current clock mode configured by the host side is consistent with the clock mode; if not, executing the step of updating the firmware of the retimer based on the clock mode.

6. The clock management method of claim 5, wherein the intrinsic attributes comprise any one or a combination of any of clock routing, PCIe switch cascading of the target component, number of clock buffer cascading, device jitter, furthest away device clock specification.

7. A clock management apparatus applied to a target component, the target component being connected to a host terminal through a cable, the apparatus comprising:

the acquisition module is used for acquiring output clock parameters prestored by the host computer end, cable parameters prestored by the cable and required clock parameters prestored by the target component;

a determining module, configured to determine a clock mode according to the output clock parameter, the cable parameter, and the demand clock parameter, and update a firmware of a PCIe switch of the target component based on the clock mode; wherein the clock modes include a homologous mode and a non-homologous mode;

a sending module, configured to send the clock mode to the host side, so that the host side updates firmware of the retimer and default clock configuration of the bios based on the clock mode;

wherein the apparatus further comprises:

the test module is used for testing and obtaining the required clock parameters of the target component based on the inherent properties of the target component;

correspondingly, the host end comprises: and the module is used for testing and obtaining the output clock parameters at the host side based on the inherent properties of the module.

8. An electronic device, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the clock management method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the clock management method according to any one of claims 1 to 6.

Background

Pcie (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, and is widely used in board level interconnection of servers, inter-board interconnection, and inter-system interconnection. For more complex PCIe interconnect systems, when the link is too long, a Retimer (Retimer) may be used for data and clock recovery, reconstruction, or PCIe switch (PCIe switch) may be used for bus expansion, while signal relay is implemented.

Although the PCIe specification has a ± 300ppm frequency offset constraint on both the homologous clock and the non-homologous clock, from the engineering practice, the system stability is better when the homologous clock is used particularly in the case of frequency spreading, so the homologous clock is preferentially adopted in the system design. However, if two devices to be interconnected are far away from each other, the clock is routed through Cable and the PCIe switches of the multiple stages of target components, and the Cable is long, the clock jitter may be close to the specification threshold, which may cause a risk to the reliable operation of the system, and in this case, the non-homogeneous clock needs to be used, and the system operates in the non-spread spectrum mode.

In the related art, for a PCIe link actually routed longer, a timer is used to perform PCIe signal relay or PCIe Switch to perform extension and relay, and the system operates in a non-homologous clock mode. When the clock scheme is determined, the Retimer and Switch will burn FW (Firmware) corresponding to the clock scheme, and the BIOS (Basic Input Output System) configuration defaults to the clock scheme. The clock scheme needs to be changed, all Firmware needs to be updated, the BIOS configuration needs to be modified, maintenance is difficult, and the risk of omission exists. When the replaceable component is changed, the system cannot select the optimal clock scheme according to the actual condition of the link, and the flexibility is not high.

Therefore, how to increase the flexibility of selecting the clock mode of the interconnection system is a technical problem that needs to be actually solved by those skilled in the art.

Disclosure of Invention

The present application aims to provide a clock management method, a clock management device, an electronic apparatus, and a computer-readable storage medium, which improve the flexibility of selecting a clock mode in an interconnection system.

In order to achieve the above object, the present application provides a clock management method applied to a target component, where the target component is connected to a host end through a cable, and the method includes:

acquiring output clock parameters prestored by the host computer, cable parameters prestored by the cable and demand clock parameters prestored by the target component;

determining a clock mode according to the output clock parameter, the cable parameter and the demand clock parameter, and updating the firmware of the PCIe switcher of the target component based on the clock mode; wherein the clock modes include a homologous mode and a non-homologous mode;

and sending the clock mode to the host side so that the host side updates firmware of the retimer and default clock configuration of the basic input output system based on the clock mode.

The first memory corresponding to the host end comprises a first memory space and a second memory space, wherein the first memory space is used for storing firmware of a baseboard management controller at the host end, and the second memory space is used for storing homologous mode firmware and non-homologous mode firmware of the retimer;

the second storage corresponding to the target assembly comprises a third storage space and a fourth storage space, the third storage space is used for storing the firmware of the baseboard management controller of the target assembly, and the fourth storage space is used for storing the homologous mode firmware and the nonhomologous mode firmware of the PCIe switcher of the target assembly.

Wherein the updating the firmware of the PCIe switcher of the target component based on the clock mode comprises:

acquiring first firmware corresponding to the clock mode of the PCIe switcher of the target component from the fourth storage space, and updating the first firmware to a third storage corresponding to the PCIe switcher of the target component;

correspondingly, the host side updates the firmware of the retimer based on the clock mode, including:

and the host side acquires second firmware corresponding to the clock mode of the retimer from the second storage space and updates the second firmware to a fourth memory corresponding to the retimer.

Wherein, after the host side updates the firmware of the retimer based on the clock mode, the method further includes:

the host side updates a basic input output system default clock configuration based on the clock mode.

Wherein the determining a clock mode according to the output clock parameter, the cable parameter, and the demand clock parameter comprises:

judging whether a homologous mode is feasible or not according to the output clock parameter, the cable parameter and the demand clock parameter;

if so, determining the clock mode as a homologous mode;

if not, determining that the clock mode is a non-homologous mode.

Wherein before updating the firmware of the PCIe switch of the target component based on the clock mode, the method further includes:

judging whether the current clock mode is consistent with the clock mode; if not, executing the step of updating the firmware of the PCIe switcher of the target component based on the clock mode;

correspondingly, before the host side updates the firmware of the retimer based on the clock mode, the method further includes:

the host side judges whether the current clock mode configured by the host side is consistent with the clock mode; if not, executing the step of updating the firmware of the retimer based on the clock mode.

Wherein, still include:

obtaining a demand clock parameter of the target component based on the inherent property test of the target component;

correspondingly, the host side obtains the output clock parameters of the host side based on the inherent property test of the host side;

wherein the inherent attribute comprises any one or a combination of any several of clock routing, PCIe switch cascading of the target component, clock buffer cascading number, device jitter, and clock specification of a farthest device.

In order to achieve the above object, the present application provides a clock management apparatus applied to a target component, where the target component is connected to a host end through a cable, the apparatus including:

the acquisition module is used for acquiring output clock parameters prestored by the host computer end, cable parameters prestored by the cable and required clock parameters prestored by the target component;

a determining module, configured to determine a clock mode according to the output clock parameter, the cable parameter, and the demand clock parameter, and update a firmware of a PCIe switch of the target component based on the clock mode; wherein the clock modes include a homologous mode and a non-homologous mode;

and the sending module is used for sending the clock mode to the host side so that the host side can update the firmware of the retimer and the default clock configuration of the basic input output system based on the clock mode.

To achieve the above object, the present application provides an electronic device including:

a memory for storing a computer program;

a processor for implementing the steps of the clock management method as described above when executing the computer program.

To achieve the above object, the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the clock management method as described above.

According to the above scheme, the clock management method provided by the present application is applied to a target component, where the target component is connected to a host end through a cable, and the method includes: acquiring output clock parameters prestored by the host computer, cable parameters prestored by the cable and demand clock parameters prestored by the target component; determining a clock mode according to the output clock parameter, the cable parameter and the demand clock parameter, and updating the firmware of the PCIe switcher of the target component based on the clock mode; wherein the clock modes include a homologous mode and a non-homologous mode; and sending the clock mode to the host side so that the host side updates firmware of the retimer and default clock configuration of the basic input output system based on the clock mode.

According to the clock management method, readability design is conducted on the parameters of the interconnected cables, the output clock parameters and the demand clock parameters are prestored at the two ends of the interconnected system respectively, the target assembly can evaluate the optimal clock mode according to the cable parameters, the output clock parameters and the demand clock parameters during power-on, corresponding firmware is updated, and the problems that efficiency is low, maintenance is difficult or risks are omitted when the firmware is updated manually are avoided. Therefore, the clock management method provided by the application realizes automatic matching of the optimal clock mode among the interconnected systems, ensures the reliability of the system to the maximum extent and solves the problem of low flexibility of selecting the clock mode in the interconnected scene of the system. The application also discloses a clock management device, an electronic device and a computer readable storage medium, which can also realize the technical effects.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

FIG. 1 is an architecture diagram of an interconnect system provided by an embodiment of the present application;

fig. 2 is a block diagram of routing between interconnection systems according to an embodiment of the present disclosure;

FIG. 3 is a structural diagram of an interconnect cable provided by an embodiment of the present application;

fig. 4 is a circuit diagram of a timer FW update and load circuit provided in the embodiment of the present application;

fig. 5 is a PCIe Switch FW update and load circuit according to an embodiment of the present application;

FIG. 6 is a flow diagram illustrating a clock management method in accordance with an exemplary embodiment;

fig. 7 is a flow chart of automatic matching of system clocks according to an embodiment of the present application;

FIG. 8 is a block diagram illustrating a clock management apparatus in accordance with an exemplary embodiment;

FIG. 9 is a block diagram illustrating an electronic device in accordance with an exemplary embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. In addition, in the embodiments of the present application, "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a specific order or a sequential order.

To facilitate understanding of the clock management method provided in the present application, an interconnection system applied thereto is described below, which includes a Host side (head or Host) and a target component (tail) connected by a Cable (Cable). Taking a Central Processing Unit (CPU) server and a Graphics Processing Unit (GPU) server as an example, referring to fig. 1, an architecture diagram of an interconnection system provided in an embodiment of the present application is shown, as shown in fig. 1, the CPU server and the GPU server are externally interconnected by using a MiniSAS HD (mini SAS high density) cable, a system bus is PCIe, and a management bus is I2C (Inter-Integrated Circuit). A host BMC (Baseboard Management Controller) in the CPU server is connected to a PCH (Platform Controller Hub). The CPU server and the GPU server have respective 100M system clock topologies, a clock source of a tail (GPU server) can be 100M from a head (CPU server) or 100M generated by an independent clock generator (CLK Generator), and the selection of the clock source is realized by a tail end BMC (baseboard control) clock source selection pin (CLK _ SELECT).

As shown in fig. 2, fig. 2 is a wiring block diagram between interconnection systems according to an embodiment of the present application, and it can be understood that there is a difference in internal wiring or clock Buffer devices of boards between multiple types of a handpiece, which results in a difference in output clock parameters of a point a of an interconnection port, and configuration parameters of the point a are stored in a handpiece BMC. Similarly, the required clock parameters output to the point B of the interconnection port are different due to differences in the internal routing or clock Buffer devices of the board card among various models of the tail, and the configuration parameters of the point B are stored in the tail BMC. When cables with different lengths are matched according to the space arrangement of the field machine and the convenience degree of outgoing lines, the change of clock parameters caused by the cables is related to the length of the cables.

Fig. 3 is a structural diagram of an interconnection Cable according to an embodiment of the present application, and as shown in fig. 3, the interconnection Cable includes two ends of a gold finger (1), a gold finger carrier (2), that is, a Printed Circuit Board (PCB), and a Cable (4), a small package EEPROM (3) is soldered to the gold finger PCB at one end, Cable parameters such as length and loss of the Cable are stored in the EEPROM (Electrically Erasable Programmable read only memory), I2C (5) of the EEPROM is connected to a Cable gold finger I2C bus, and the EEPROM can be read by BMC at two ends through an I2C bus.

Fig. 4 is a circuit diagram of a Retimer FW update and load circuit according to an embodiment of the present disclosure, where SDA is a data line and SCL is a control line. As shown in FIG. 4, the Retimer uses EEPROM to store FW, a two-way 2-out electronic switch is used in an I2C line between the Retimer and the EEPROM, the common terminal of the switch is connected with the EEPROM, when the electronic switch switches a selection pin (SW) to a low level, the I2C of the EEPROM is conducted with the BMC by default, and the FW in the EEPROM can be updated by the BMC. When the system is started (at the time, P3V3 is powered on), the I2C of the EEPROM is conducted with the timer, and the timer loads FW normally.

Fig. 5 is a circuit for updating and loading PCIe Switch FW according to an embodiment of the present application, where TXD is a transmitting data port and RXD is a receiving data port. As shown in fig. 5, the PCIe Switch uses an SPI Flash (Serial Peripheral Interface Flash) as the FW memory, the Flash is directly connected to the Switch through an SPI bus, the BMC at the tail end is connected to the PCIe Switch through a Serial port (UART), and the middle is connected to a Level shift circuit (Level shift).

It should be noted that, for an application in which a single machine is terminated by multiple machines, an independent homologous clock and non-homologous clock selection circuit may be designed for each PCIe Switch, and the Switch and the respective downstream devices share a clock scheme.

The embodiment of the application discloses a clock management method, which improves the flexibility of selecting a clock mode of an interconnection system.

Referring to fig. 6, a flowchart of a clock management method according to an exemplary embodiment is shown, as shown in fig. 6, including:

s101: acquiring output clock parameters prestored by the host computer, cable parameters prestored by the cable and demand clock parameters prestored by the target component;

the execution subject of the present embodiment is a target component (tail) in the interconnection system. The standby power supply is powered on, the BMC at the host end (head) and the BMC at the tail end work normally, the tail end evaluates the optimal clock scheme and configures the FW of PCIe devices, and the head end waits for the configuration of the tail end to be completed. In specific implementation, the tail end BMC first reads the output clock parameter of the point a at the host end, then reads the cable parameter from the cable EEPROM, and then reads the self-prestored required clock parameter of the point B.

As a preferred embodiment, this embodiment further includes: obtaining a demand clock parameter of the target component based on the inherent property test of the target component; correspondingly, the host side obtains the output clock parameters of the host side based on the inherent property test of the host side; wherein the inherent property includes any one or a combination of any several of clock routing, connector cascading, number of clock buffer cascading, device jitter, furthest away device clock specification. It can be understood that the Host output clock parameters are related to the clock routing, the connector cascade, the number of clock buffer cascades, the device jitter, etc., and are inherent attributes of the handpiece, and are obtained by actual testing before delivery and stored in the Host BMC. The tail end required clock parameters are related to tail clock routing, connector cascading, clock buffer cascading quantity, device jitter, farthest end device clock specification and the like, are inherent attributes of the tail, are obtained through actual testing before delivery, and are stored in a tail BMC.

S102: determining a clock mode according to the output clock parameter, the cable parameter and the demand clock parameter, and updating the firmware of the PCIe switcher of the target component based on the clock mode; wherein the clock modes include a homologous mode and a non-homologous mode;

in this step, the tail end comprehensively evaluates the output clock parameters, the cable parameters and the demand clock parameters to obtain the optimal clock mode, i.e. determines whether to use the homologous clock mode or the non-homologous clock mode. As a possible implementation, the determining a clock mode according to the output clock parameter, the cable parameter, and the demand clock parameter includes: judging whether a homologous mode is feasible or not according to the output clock parameter, the cable parameter and the demand clock parameter; if so, determining the clock mode as a homologous mode; if not, determining that the clock mode is a non-homologous mode. And when the default configuration is different from the evaluated optimal configuration, updating the PCIe Switch FW to be the FW corresponding to the determined clock mode, wherein the updating of the PCIe Switch FW requires system power-on, and the system power-on is performed at the moment. Namely, before the updating the firmware of the PCIe switch of the target component based on the clock mode, the method further includes: judging whether the current clock mode is consistent with the clock mode; if not, executing the step of updating the firmware of the PCIe switcher of the target component based on the clock mode.

S103: and sending the clock mode to the host side so that the host side updates firmware of the retimer and default clock configuration of the basic input output system based on the clock mode.

In this step, the method for informing the host end of the clock mode configuration by the tail end, and the host end BMC also determining the clock configuration and the default clock configuration, that is, before the host end updates the firmware of the retimer based on the clock mode, further includes: the host side judges whether the current clock mode configured by the host side is consistent with the clock mode; if not, executing the step of updating the firmware of the retimer based on the clock mode. And when the clock mode and the clock mode are not matched, updating the FW corresponding to the determined clock mode of the timer EEPROM, then updating the clock configuration corresponding to the port in the BIOS, and allowing the system to be normally started after the system clock configuration is finished.

According to the clock management method provided by the embodiment of the application, readability design is conducted on the parameters of the interconnected cables, the output clock parameters and the demand clock parameters are prestored at two ends of the interconnected system respectively, the target assembly can evaluate the optimal clock mode according to the parameters of the cables, the output clock parameters and the demand clock parameters during power-on, corresponding firmware is updated, and the problems that efficiency is low, maintenance is difficult or missing risks when the firmware is updated manually are avoided. Therefore, the clock management method provided by the embodiment of the application realizes automatic matching of the optimal clock mode among the interconnected systems, ensures the reliability of the system to the maximum extent and solves the problem of low flexibility in selecting the clock mode in the interconnected scene of the system.

On the basis of the foregoing embodiment, as a preferred implementation, the first memory corresponding to the host side includes a first memory space and a second memory space, where the first memory space is used to store firmware of a baseboard management controller at the host side, and the second memory space is used to store homologous mode firmware and non-homologous mode firmware of the retimer; the second storage corresponding to the target assembly comprises a third storage space and a fourth storage space, the third storage space is used for storing the firmware of the baseboard management controller of the target assembly, and the fourth storage space is used for storing the homologous mode firmware and the nonhomologous mode firmware of the PCIe switcher of the target assembly.

In specific implementation, BMC Flash (namely storage space of a first storage and a second storage) of a host end and a target component is subjected to partition management, storage space corresponding to FW in two clock modes of a PCIe device is reserved, and the FW updating of the PCIe device is automatically completed by a system according to a current actual clock scheme. The BMC Flash is partitioned according to the number and the size of PCIe devices FW needing to be backed up in blocks, and the Flash capacity is determined according to the size of the BMC FW and the size of the backup FW.

In specific implementation, the minimum erase unit of the BMC Flash is a sector, the selectable erase unit is a sector, a block, a full slice, and the maximum program (write) unit is a page (256 bytes), and if the maximum program (write) unit is greater than 256 bytes, cyclic write is required. Each block includes 16 sectors (64 KB), each sector including 16 pages (4 KB), each page being 256 bytes. According to the characteristics of Flash, the BMC Flash is subjected to partition management, for example, 64MB Flash, the initial 60MB space (0 x 0000000-0 x3BF FFFF) is used for storing BMC FW, the BMC FW upgrade adopts a block erasure mode, only the 60M space is operated, and the rest space is kept unchanged. Flash has 4MB space left, and every 16 blocks (256 KB) from bottom to top are used as backup space of Retimer FW or Switch FW, each Retimer or Switch backs up two FW, namely a homologous clock FW and a non-homologous clock FW, so that 4 retimers or switches occupy 8 × 256K =2M Flash space.

On this basis, the system clock automatic matching process is shown in fig. 7, and the updating the firmware of the PCIe switch of the target component based on the clock mode includes: acquiring first firmware corresponding to the clock mode of the PCIe switcher of the target component from the fourth storage space, and updating the first firmware to a third storage corresponding to the PCIe switcher of the target component; correspondingly, the host side updates the firmware of the retimer based on the clock mode, including: and the host side acquires second firmware corresponding to the clock mode of the retimer from the second storage space and updates the second firmware to a fourth memory corresponding to the retimer. In a specific implementation, the Retimer may use EEPROM to store FW, the PCIe Switch may store FW through SPI Flash, FW required by the homologous clock and the non-homologous clock modes is different, and the clock mode of each PCIe port of the CPU is configured by BIOS. When the system is powered on, the timer and the PCIe Switch load FW from respective memory spaces when the reset is released (the PERST is changed from low level to high level), and the PCIe device performs Link training (Link training) according to the setting of the configuration information.

In the following, a clock management apparatus provided by an embodiment of the present application is introduced, and a clock management apparatus described below and a clock management method described above may be referred to each other.

Referring to fig. 8, a block diagram of a clock management apparatus according to an exemplary embodiment is shown, as shown in fig. 8, including:

an obtaining module 801, configured to obtain an output clock parameter pre-stored by the host, a cable parameter pre-stored by the cable, and a demand clock parameter pre-stored by the target component;

a determining module 802, configured to determine a clock mode according to the output clock parameter, the cable parameter, and the demand clock parameter, and update a firmware of a PCIe switch of the target component based on the clock mode; wherein the clock modes include a homologous mode and a non-homologous mode;

a sending module 803, configured to send the clock mode to the host side, so that the host side updates the firmware of the retimer and the default clock configuration of the bios based on the clock mode.

The clock management device provided by the embodiment of the application can be used for performing readability design on the parameters of the interconnected cables, the output clock parameters and the demand clock parameters are pre-stored at the two ends of the interconnected system respectively, the target assembly can evaluate the optimal clock mode according to the cable parameters, the output clock parameters and the demand clock parameters during power-on, corresponding firmware is updated, and the problems that the efficiency of manual firmware updating is low, the maintenance is difficult or the omission risk exists are avoided. Therefore, the clock management device provided by the embodiment of the application realizes automatic matching of the optimal clock mode among the interconnected systems, ensures the reliability of the system to the maximum extent and solves the problem of low flexibility in selecting the clock mode in the interconnected scene of the system.

On the basis of the foregoing embodiment, as a preferred implementation, the first memory corresponding to the host side includes a first memory space and a second memory space, where the first memory space is used to store firmware of a baseboard management controller at the host side, and the second memory space is used to store homologous mode firmware and non-homologous mode firmware of the retimer;

the second storage corresponding to the target assembly comprises a third storage space and a fourth storage space, the third storage space is used for storing the firmware of the baseboard management controller of the target assembly, and the fourth storage space is used for storing the homologous mode firmware and the nonhomologous mode firmware of the PCIe switcher of the target assembly.

On the basis of the foregoing embodiment, as a preferred implementation, the determining module 802 includes:

the determining unit is used for determining a clock mode according to the output clock parameter, the cable parameter and the required clock parameter;

the updating unit is used for acquiring first firmware corresponding to the clock mode of the PCIe switcher of the target component from the fourth storage space and updating the first firmware into a third storage corresponding to the PCIe switcher of the target component;

correspondingly, the host end comprises:

and the updating module is used for acquiring second firmware corresponding to the clock mode of the retimer from the second storage space and updating the second firmware into a fourth memory corresponding to the retimer.

On the basis of the foregoing embodiment, as a preferred implementation, the host further includes: means for updating a basic input output system default clock configuration based on the clock mode.

On the basis of the foregoing embodiment, as a preferred implementation manner, the determining unit specifically determines whether a homogeneous mode is feasible according to the output clock parameter, the cable parameter, and the demand clock parameter; if so, determining the clock mode as a homologous mode; and if not, determining the clock mode as a unit of the non-homologous mode.

On the basis of the foregoing embodiment, as a preferred implementation manner, the determining module 802 further includes:

the judging unit is used for judging whether the current clock mode is consistent with the clock mode or not; if not, starting the working process of the updating unit;

correspondingly, the host end further comprises:

the judging module is used for judging whether the current clock mode configured by the judging module is consistent with the clock mode; if not, starting the work flow of the updating module.

On the basis of the above embodiment, as a preferred implementation, the method further includes:

the test module is used for testing and obtaining the required clock parameters of the target component based on the inherent properties of the target component;

correspondingly, the host end further comprises: a module for obtaining the output clock parameter of the host end based on the inherent property test of the host end;

wherein the inherent attribute comprises any one or a combination of any several of clock routing, PCIe switch cascading of the target component, clock buffer cascading number, device jitter, and clock specification of a farthest device.

With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.

Based on the hardware implementation of the program module, and in order to implement the method according to the embodiment of the present application, an embodiment of the present application further provides an electronic device, and fig. 9 is a structural diagram of an electronic device according to an exemplary embodiment, as shown in fig. 9, the electronic device includes:

a communication interface 1 capable of information interaction with other devices such as network devices and the like;

and the processor 2 is connected with the communication interface 1 to realize information interaction with other equipment, and is used for executing the clock management method provided by one or more technical schemes when running a computer program. And the computer program is stored on the memory 3.

In practice, of course, the various components in the electronic device are coupled together by the bus system 4. It will be appreciated that the bus system 4 is used to enable connection communication between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. For the sake of clarity, however, the various buses are labeled as bus system 4 in fig. 9.

The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device.

It will be appreciated that the memory 3 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The memory 2 described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The method disclosed in the above embodiment of the present application may be applied to the processor 2, or implemented by the processor 2. The processor 2 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 2. The processor 2 described above may be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 2 may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in the memory 3, and the processor 2 reads the program in the memory 3 and in combination with its hardware performs the steps of the aforementioned method.

When the processor 2 executes the program, the corresponding processes in the methods according to the embodiments of the present application are realized, and for brevity, are not described herein again.

In an exemplary embodiment, the present application further provides a storage medium, i.e. a computer storage medium, specifically a computer readable storage medium, for example, including a memory 3 storing a computer program, which can be executed by a processor 2 to implement the steps of the foregoing method. The computer readable storage medium may be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface Memory, optical disk, or CD-ROM.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.