1. A discontinuous address processing method is used for processing discontinuous addresses in nand flash, and is characterized by comprising the following steps:

s1, scanning and acquiring discontinuous addresses in the physical layer of the flash memory;

s2, acquiring the block where the discontinuous address is located;

s3, designing a bypass logic of the block where the discontinuous address is located;

and S4, according to the bypass logic, enabling the FTL layer to bypass the mapping of the discontinuous address blocks in operation.

2. The method according to claim 1, wherein the bypassing logic in step S3 is designed as a second level mapping logic, so that the FTL layer maps the target to the block where the discontinuity exists to another normal block through the second level mapping logic.

3. The method according to claim 1, wherein the bypassing logic in step S3 is configured to bypass the block mapping by including the block with the discontinuous address in a bad block so that the block with the discontinuous address is not in the FTL layer mapping target.

4. The method as claimed in claim 3, wherein the step of including the block where the discontinuous address is located in the bad block includes: and traversing and checking block addresses in the flash memory, and adding the bad blocks and the blocks where the discontinuity exists into a bad block table.

5. The method as claimed in claim 4, wherein when checking the block address in the flash memory, it is determined whether the block is the block where the discontinuous address is located, and if not, it is determined whether the block is a bad block.

6. A method and device for processing discontinuous addresses in nand flash are used for processing discontinuous addresses in nand flash, and are characterized by comprising the following steps:

the acquisition module is used for acquiring discontinuous addresses and blocks thereof in the flash memory physical layer;

the bypass module is used for setting bypass logic for bypassing the block where the discontinuous address is located;

the FTL layer module is used for carrying out physical layer mapping during nand flash operation;

the FTL layer runtime can perform physical layer mapping based on the bypass logic set by the bypass module to bypass the block where the discontinuous address is located.

7. The apparatus of claim 6, wherein the bypass module is a secondary mapping module, and is configured to generate a second-level mapping logic, and perform a second-level mapping to map the target to another normal block when the FLT layer mapping targets the block where the discontinuous address is located.

8. The apparatus according to claim 6, wherein the bypass module is a bad block management module, and the block where the discontinuous address is located is included in the bad block management module, so that the FLT layer runtime bypasses the block where the discontinuous address is located for mapping.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-5.

10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-5.

Background

As a common large-capacity memory chip, nandflash is widely used in consumer electronics products due to the continuous increase in memory density and the advantage of particle cost. The nandflash storage requirement is increased day by day under the promotion of huge requirements of novel industries such as mobile phones, notebooks, artificial intelligence, 5G communication and the like.

However, nandflash has a plurality of standards, and nand manufacturers, including intel, magnesian and hai-shi, lead the ONFI standard, while samsung and Toshiba marketing owner play the Toggle standard. Different standards make the technical rules of products have great difference, even in the same standard, different companies have some differences in product planning because the chips are limited by the semiconductor chip manufacturing process, for example, discontinuous addresses in different nand flash exist in addresses, the addresses in the discontinuous addresses are random and discontinuous, lack of orderliness, and are easy to make mistakes in address operation; whether it is a small os or linux, on the software architecture, from top to bottom, it can be divided into: application layer, file system layer, FTL, physical layer. The FTL layer obtains a logical block address corresponding to the operation command from the file system, and the FTL layer maps the target layer to the block for operation; the original complex FTL needs to consider bad block management and wear balance, and if the identification and processing method of the discontinuous address is added, the FTL is more complex and the development difficulty is large; the traditional nand flash address discontinuous processing method generally adopts MTD to manage a plurality of areas, for example, by dividing a plurality of MTD areas, setting corresponding pseudo physical block numbers, and obtaining real physical block numbers by different mapping algorithms, the method is complex and is not suitable for small system products.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method and an apparatus for processing a discontinuous address, an electronic device, and a storage medium, which utilize a simple logic method to enable an FTL layer to bypass a block where the discontinuous address is located for operation, thereby avoiding the influence of the discontinuous address on data reading and writing, and not increasing the complexity of the FTL layer, and being suitable for different products of different manufacturers.

In a first aspect, an embodiment of the present application provides a method for processing a discontinuous address, where the method is used to process a discontinuous address in a nand flash, and the method includes the following steps:

s1, scanning and acquiring discontinuous addresses in the physical layer of the flash memory;

s2, acquiring the block where the discontinuous address is located;

s3, designing a bypass logic of the block where the discontinuous address is located;

and S4, according to the bypass logic, enabling the FTL layer to bypass the mapping of the discontinuous address blocks in operation.

In the discontinuous address processing method, the bypassing logic in step S3 is designed to design the second-level mapping logic, so that when the FTL layer maps the target to the block where the discontinuity exists, the FTL layer maps the target to another normal block through the second-level mapping logic.

In the discontinuous address processing method, the bypassing logic in step S3 is to include the block where the discontinuous address is located in a bad block, so that the block where the discontinuous address is located is not in the FTL layer mapping target and bypasses the block mapping.

The discontinuous address processing method includes the following steps of: and traversing and checking block addresses in the flash memory, and adding the bad blocks and the blocks where the discontinuity exists into a bad block table.

When checking the block address in the flash memory, the method first determines whether the block is the block where the discontinuous address is located, and if not, then determines whether the block is a bad block.

In a second aspect, an embodiment of the present application further provides a device for processing a discontinuous address, where the device is used to process a discontinuous address in a nand flash, and includes:

the acquisition module is used for acquiring discontinuous addresses and blocks thereof in the flash memory physical layer;

the bypass module is used for setting bypass logic for bypassing the block where the discontinuous address is located;

the FTL layer module is used for carrying out physical layer mapping during nand flash operation;

the FTL layer runtime can perform physical layer mapping based on the bypass logic set by the bypass module to bypass the block where the discontinuous address is located.

The apparatus of the discontinuous address processing method may further include that the bypass module is a secondary mapping module, and may generate a second-level mapping logic, and perform the second-level mapping to map the target to another normal block when the FLT layer mapping target is the block where the discontinuous address is located.

The apparatus for processing discontinuous addresses, wherein the bypass module is a bad block management module, and can include a block where the discontinuous addresses are located in bad block management, so that the FLT layer bypasses the block where the discontinuous addresses are located for mapping during operation.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.

In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program runs the steps in the method provided in the first aspect when executed by a processor.

As can be seen from the above, in the processing method, by designing the bypass logic for the block where the discontinuous address is located, the block where the discontinuous address is located can be bypassed for operation when the FTL layer operates, so that the influence of the discontinuous address on data reading and writing can be avoided.

Drawings

Fig. 1 is a flowchart of a method for processing a discontinuous address according to an embodiment of the present application.

Fig. 2 is a logic diagram of an embodiment of a method for processing a discontinuous address to bypass logic according to an embodiment of the present application.

Fig. 3 is a logic diagram of another embodiment of a bypass logic in a method for processing a discontinuous address according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram of a discontinuous address processing apparatus according to an embodiment of the present application.

FIG. 5 is a table of address information for a nand flash.

FIG. 6 is a logic diagram of a bad block management process for blocks with non-consecutive addresses in the address information table of FIG. 5.

Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

In a first aspect, please refer to fig. 1, where fig. 1 is a method for processing discontinuous addresses in nand flash in some embodiments of the present application, where the method includes the following steps:

s1, scanning and acquiring discontinuous addresses in the physical layer of the flash memory;

specifically, different manufacturers' nand flash standards are different and products are different, so that corresponding scanning is required to accurately obtain the discontinuous address distribution condition in the flash memory chip.

S2, acquiring the block where the discontinuous address is located;

specifically, a Logical Block Address (LBA) corresponding to an operation command of the file system layer generally uses a sector (sector 512B) as a minimum basic unit, and the FTL layer converts the sector into a corresponding Block and page to perform an operation, so that a Block where a discontinuous Address is located needs to be obtained in the embodiment of the present application, so that the embodiment of the present application can use the Block as an operation unit, which is beneficial to the processing operation of the FTL layer, and conforms to an operation logic of the FTL layer to reduce a load of the FTL layer.

S3, designing a bypass logic of the block where the discontinuous address is located;

specifically, the bypass logic serves the FTL layer, and aims to provide a logic capable of bypassing a block where a discontinuous address is located so that the corresponding block does not participate in read/write operations.

And S4, according to the bypass logic, enabling the FTL layer to bypass the mapping of the discontinuous address blocks in operation.

Specifically, based on the bypass logic, after receiving the operation command of the file system layer, the FTL maps the operation command to a normal block other than the block where the discontinuous address exists for performing an operation, so that the block where the discontinuous address exists does not participate in the read/write operation.

The discontinuous address processing method of the embodiment of the application acquires the discontinuous address and the block where the discontinuous address is located in the flash memory, designs the bypass logic of the block, enables the block where the discontinuous address is located to be bypassed to operate when the FTL layer operates, processes the discontinuous address by adopting a direct bypass mode, can avoid the influence of the discontinuous address on data reading and writing, is simple in logic, cannot increase complexity of the FTL layer, and is suitable for different products of different manufacturers.

In some preferred embodiments, the bypass logic in step S3 includes and is not limited to two embodiments, wherein the first embodiment is: the second level mapping logic is designed such that the FTL layer maps the target to the block where the discontinuity is located into another normal block through the second level mapping logic.

Specifically, as shown in fig. 2, the FTL layer itself has a first mapping logic capable of mapping instructions to target blocks for operation, and the second mapping logic is designed to add a bypass layer, which is disposed between the FTL layer and the physical layer, and is not operated when the FTL layer maps targets to normal blocks, and is operated when the FTL layer maps targets to blocks where discontinuous addresses are located, and performs a second mapping on the mapping targets according to the second mapping logic to map the targets to normal blocks; the method of adding the bypass layer between the FTL layer and the physical layer does not increase the complexity of the FTL layer and can conveniently realize the bypass processing of discontinuous addresses.

More specifically, the second-level mapping logic is a conditional logic, that is, it is determined whether a block number of an FTL layer mapping target is within a number of a block belonging to a discontinuous address, if not, mapping is not performed, and if yes, a number value is changed correspondingly to perform the second-level mapping; the number value can be changed in a mode of increasing the number value for a fixed value or decreasing the number value for the fixed value, and the number value change range is set based on the coverage area of the block number where the discontinuous address is located; if the block where the discontinuous address in a certain nand flash is located covers the fast address with the number of n-m, the condition that the bypass layer judges whether the mapping target belongs to the discontinuous address is as follows: if (block _ num > = n & & block _ num < = m), namely whether the block number of the mapping target is between n-m is judged, when the mapping target is in the block of the discontinuous address, Phy _ num = block _ num + (m-n + 1), even if the block number of the mapping target is increased by (m-n + 1) value, thereby realizing the bypass processing of the discontinuous address, in addition, the number value change amount is designed to be (m-n + 1), thereby ensuring that the mapping target can be mapped to the address except the discontinuous address smoothly; the embodiment of the application performs the second-level mapping by setting the pseudo code, so that the FTL layer can bypass the block where the discontinuous address is located for mapping, and the FTL layer has the characteristics of simple and effective logic, and cannot increase the complexity of the FTL layer, and cannot directly influence the mapping logic of the FTL layer.

In some preferred embodiments, the second implementation of the bypass logic in step S3 is: the block where the discontinuous address is located is included in the bad block so that the block where the discontinuous address is located is not in the FTL layer mapping target but bypasses the block mapping.

Specifically, the bad block is generally an unusable block address in the flash memory, the bad block can be prevented from being used by a bad block management mode, and the FTL layer mapping can also skip the bad block for mapping, so that when the bad block is sorted, the block where the discontinuous address is located is included, and the block where the discontinuous address is located can be disguised as the bad block, so that the FTL layer can directly bypass the block where the discontinuous address is located for block address mapping when running.

In some preferred embodiments, the process of including the block where the discontinuous address is located in the bad block is as follows: and traversing and checking block addresses in the flash memory, and adding the bad blocks and the blocks where the discontinuity exists into a bad block table.

Specifically, before the step is executed and the flash memory chip is put into use, bad block scanning needs to be carried out first to avoid using the bad blocks, and a judgment condition of a block where a discontinuous address is located is added in the step, so that the block where the discontinuous address is located can be brought into bad block management, if a block where the discontinuous address is located in a nand flash covers a fast address with the number of n-m, the condition is added to judge whether the block number is between n-m, and if yes, the block number is brought into a bad block table.

In some preferred embodiments, as shown in fig. 3, when checking the block address in the flash memory, it is determined whether the block is the block where the discontinuous address is located, and if not, it is determined whether the block is a bad block.

Specifically, since the block where the discontinuous address is located is already obtained in steps S1-S2, the block where the discontinuous address is located can be managed in the bad block table according to the block number without re-identifying the address of the block where the discontinuous address is located, and determining the block where the discontinuous address is located first can reduce the amount of data analysis in the scanning process.

According to the discontinuous address processing method, by designing the bypass logic of the block where the discontinuous address is located, the block where the discontinuous address is located can be bypassed to operate when the FTL layer operates, the influence of the discontinuous address on data reading and writing can be avoided, the logic of the processing method is simple, the complexity of the FTL layer cannot be increased, and the processing method is suitable for different products of different manufacturers.

In a second aspect, please refer to fig. 4, where fig. 4 is a device for processing discontinuous addresses in nand flash provided in some embodiments of the present application, and the device includes:

the acquisition module is used for acquiring discontinuous addresses and blocks thereof in the flash memory physical layer;

the bypass module is used for setting bypass logic for bypassing the block where the discontinuous address is located;

the FTL layer module is used for carrying out physical layer mapping during nand flash operation;

the FTL layer runtime can perform physical layer mapping based on the bypass logic set by the bypass module to bypass the block where the discontinuous address is located.

According to the discontinuous address processing method and device, the discontinuous addresses and the blocks where the discontinuous addresses are located in the flash memory are obtained through the obtaining module, the bypass logic related to the blocks is designed through the bypass module, so that the blocks where the discontinuous addresses are located can be bypassed based on the bypass logic when the FTL layer module operates, the discontinuous addresses are processed in a direct bypass mode, the discontinuous addresses can be prevented from influencing data reading and writing, the logic of the processing method is simple, the complexity of the FTL layer module cannot be increased, and the processing method and device are suitable for different products of different manufacturers.

In some preferred embodiments, the bypass module includes, but is not limited to, two embodiments, wherein the first embodiment is: the bypass module is a secondary mapping module that generates second level mapping logic that maps targets to otherwise normal blocks when the FLT layer maps the target to the block where the non-consecutive address is located.

Specifically, the secondary mapping module is used as a bypass layer between the FTL layer module and the physical layer, and when the mapping target of the FTL layer module is a normal block, the bypass layer does not operate, and when the mapping target of the FTL layer module is a block where the discontinuous address is located, the bypass layer operates and performs second mapping on the mapping target according to the second mapping logic, so as to map the target to the normal block; the mode of additionally arranging the bypass layer between the FTL layer module and the physical layer does not increase the complexity of the FTL layer module and can conveniently realize the bypass processing of discontinuous addresses.

In some preferred embodiments, the second embodiment of the bypass module is: the bypass module is a bad block management module and can incorporate the block where the discontinuous address is located into bad block management so as to map the block where the discontinuous address is located by bypassing the FLT layer during operation.

Specifically, the bad block is generally an unusable block address in the flash memory, the bad block can be prevented from being used by the bad block management module, and the mapping of the FTL layer module can also skip the bad block for mapping, so that when the bad block management module arranges the bad block, the block where the discontinuous address is located is included, the block where the discontinuous address is located can be disguised as the bad block, and the FTL layer module can directly bypass the block where the discontinuous address is located for block address mapping when running.

Example 1

As shown in FIG. 5, which shows the address situation of a nand flash chip, where the discontiguous address is represented by 086400 h-0 FFFFFh, the analysis shows that the block number covered by the discontiguous address is 2148-:

if(block_num >=2148 && block_num <=4095)

Phy_num = block_num+1948;

that is, when the mapping target of the FTL layer is at block number 2148-.

Example 2

FIG. 5 shows the address situation of a nand flash chip, in which the non-consecutive addresses are represented by 086400 h-0 FFFFFh, and the analysis shows that the block numbers covered by the non-consecutive addresses are 2148-; as shown in fig. 6, to incorporate the block number (2148-.

In a third aspect, referring to fig. 5, fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.

In a fourth aspect, the present application provides a storage medium, and when being executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.