1. A CPU power supply system comprising:

a Central Processing Unit (CPU) powered by a first voltage rail and a second voltage rail;

a first voltage regulator controlled by a first Pulse Width Modulation (PWM) signal to generate a first voltage rail;

a second voltage regulator controlled by a second PWM signal to generate a second voltage rail; and

the power supply controller receives a plurality of power supply management instructions sent by the CPU through a data bus and generates a first PWM signal and a second PWM signal; the power supply controller sets a voltage value of a second voltage rail according to a first power supply management instruction sent by the CPU; the power supply controller ignores a second power supply management instruction sent by the CPU, and controls the second voltage regulator to operate in a Discontinuous Conduction Mode (DCM), where the second power supply management instruction is to control the second voltage regulator to operate in the first operating Mode.

2. The system of claim 1, wherein the first operating Mode comprises a Continuous Conduction Mode (CCM).

3. The system of claim 1, further comprising:

a third voltage regulator controlled by a third PWM signal to generate a first voltage rail, wherein the third voltage regulator and the first voltage regulator form a multi-phase voltage regulator.

4. The system of claim 3, wherein the power controller is to control the multi-phase voltage regulator to operate in the full-phase CCM mode when the CPU issues the third power management command indicating the multi-phase voltage regulator to operate in the second operating mode.

5. The system of claim 4, wherein the power controller sets the voltage value of the first voltage rail according to a fourth power management command issued by the CPU.

6. The system of claim 1, wherein a value of a rated output current of the first voltage rail is greater than a value of a rated output current of the second voltage rail.

7. The system of claim 1, wherein the data bus is a serial data transfer bus.

8. The system of claim 1, wherein the power supply controller controls the second PWM signal to have a first state, a second state, and a third state.

9. The system of claim 8, wherein the second voltage regulator comprises:

a high-side switch;

a low side switch; and

an output inductor coupled to a common node of the high-side switch and the low-side switch;

when the inductor current is reduced to zero and the second PWM signal is tristated, the low side switch is turned off.

10. A CPU power supply control method comprises the following steps:

controlling a first voltage regulator to generate a first voltage rail according to a first PWM signal, wherein the first voltage rail is used for supplying power to a CPU;

controlling a second voltage regulator to generate a second voltage rail according to a second PWM signal, wherein the second voltage rail is used for supplying power to the CPU;

controlling a first voltage regulator to work in a first working mode according to a first power management instruction sent by a CPU (Central processing Unit) so as to generate a first voltage rail; and

and ignoring a second power management instruction sent by the CPU, controlling the second voltage regulator to work in a DCM mode so as to generate a second voltage rail, wherein the second power management instruction is used for controlling the second voltage regulator to work in a second working mode.

11. The control method according to claim 10, further comprising:

and adjusting the voltage value of the second voltage rail according to a third power management instruction sent by the CPU.

12. The method of claim 10, wherein controlling the second voltage regulator to operate in DCM to generate the second voltage rail comprises:

the second PWM signal is set to insert a third state between the first state and the second state in addition to the first state and the second state.

13. The control method according to claim 12, further comprising:

during the time that the second PWM signal is in the third state, the low side switch of the second voltage regulator is turned off when the inductor current flowing through the output inductor in the second voltage regulator falls to zero.

14. The control method according to claim 10, further comprising:

and controlling a third voltage regulator to generate a first voltage rail according to the third PWM signal, wherein the first voltage regulator generates a first phase voltage of the first voltage rail, and the third voltage regulator generates a second phase voltage of the first voltage rail.

15. The control method of claim 14, wherein the first operating mode is a full phase CCM mode.

16. The control method of claim 10, wherein the second operating mode is a single-phase CCM mode.

17. A power supply controller comprising:

a data bus interface for receiving a plurality of power management instructions from the CPU; and

the control signal generator is used for generating a first control signal and a second control signal, wherein the first control signal controls the first voltage regulator to generate a first voltage rail, the second control signal controls the second voltage regulator to generate a second voltage rail, and the first voltage rail and the second voltage rail are used for supplying power to the CPU; the control signal generator sets the voltage value of the second voltage rail according to a first power management instruction sent by the CPU; the control signal generator ignores the working mode instruction sent by the CPU and controls the second voltage regulator to work in a DCM.

18. The controller of claim 17, wherein the second control signal is a pulse width modulated signal, the control signal generator to insert a third state between the first state and the second state of the second PWM signal in addition to controlling the second PWM signal to have the first state and the second state.

19. The controller of claim 17, wherein the operating mode instruction is to control the second voltage regulator to operate in CCM mode.

20. The controller of claim 17, wherein the control signal generator further generates a third control signal, wherein the third control signal controls a third voltage regulator to generate the first voltage rail.

Background

A central processing unit, also called "processor". In processor applications, a power supply is typically required to provide two or more voltage rails to power the processor. Generally, processors, such as various processor products of the advanced micro-devices (AMD), send power management commands to control the operation of a power supply via a serial or parallel voltage control bus. The power management instructions may instruct the power supply to control each voltage rail and adjust the voltage value of each voltage rail in different operating modes. The operation Mode refers to a voltage regulator operating in a Continuous Conduction Mode (CCM) of a full phase, a single-phase CCM Mode, or a Discontinuous Conduction Mode (DCM). Typically, in this case, the power supply is controlled by the processor itself (not the power supply) to communicate the power delivery condition to the processor. In some cases, however, it is not efficient to control the power delivery of the power supply entirely by the processor.

Accordingly, it is desirable to provide a more flexible and efficient processor power control solution.

Disclosure of Invention

In order to solve one or more of the problems described above, the present invention proposes a CPU power supply system and a control method and a controller different from the prior art.

One aspect of the present invention provides a CPU power supply system, including: a Central Processing Unit (CPU) powered by a first voltage rail and a second voltage rail; a first voltage regulator controlled by a first Pulse Width Modulation (PWM) signal to generate a first voltage rail; a second voltage regulator controlled by a second PWM signal to generate a second voltage rail; the power supply controller receives a plurality of power supply management instructions sent by the CPU through a data bus and generates a first PWM signal and a second PWM signal; the power supply controller sets a voltage value of a second voltage rail according to a first power supply management instruction sent by the CPU; the power supply controller ignores a second power supply management instruction sent by the CPU, and controls the second voltage regulator to operate in a Discontinuous Conduction Mode (DCM), where the second power supply management instruction is to control the second voltage regulator to operate in the first operating Mode.

In another aspect, the present invention provides a CPU power supply control method, including: controlling a first voltage regulator to generate a first voltage rail according to a first PWM signal, wherein the first voltage rail is used for supplying power to a CPU; controlling a second voltage regulator to generate a second voltage rail according to a second PWM signal, wherein the second voltage rail is used for supplying power to the CPU; controlling a first voltage regulator to work in a first working mode according to a first power management instruction sent by a CPU (Central processing Unit) so as to generate a first voltage rail; and ignoring a second power management instruction sent by the CPU, controlling the second voltage regulator to work in a DCM mode so as to generate a second voltage rail, wherein the second power management instruction is used for controlling the second voltage regulator to work in a second working mode.

Yet another aspect of the present invention provides a power supply controller including: a data bus interface for receiving a plurality of power management instructions from the CPU; the control signal generator is used for generating a first control signal and a second control signal, wherein the first control signal controls the first voltage regulator to generate a first voltage rail, the second control signal controls the second voltage regulator to generate a second voltage rail, and the first voltage rail and the second voltage rail are used for supplying power to the CPU; the control signal generator sets the voltage value of the second voltage rail according to a first power management instruction sent by the CPU; the control signal generator ignores the working mode instruction sent by the CPU and controls the second voltage regulator to work in a DCM.

Drawings

For a better understanding of the present invention, reference will now be made in detail to the following drawings, in which:

FIG. 1 is a schematic block circuit diagram of a computing device according to an embodiment of the invention;

FIG. 2 is a circuit schematic of the voltage regulator 102 according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of the PWM generator 104 according to an embodiment of the present invention;

FIG. 4 is a graph illustrating voltage regulator efficiency as a function of load current for different operating modes;

FIG. 5 is a graph illustrating voltage regulator efficiency as a function of load current for different operating modes;

FIG. 6 is a graph illustrating power loss of the voltage regulator as a function of load current;

FIG. 7 is a graph illustrating power loss of the voltage regulator as a function of load current;

FIG. 8 is a timing diagram of the PWM signal, inductor current signal, and load current signal (top to bottom) when the voltage regulator is operating in single-phase CCM mode;

FIG. 9 is a graph illustrating power loss versus load current for a voltage regulator operating in DCM;

FIG. 10 is a timing diagram of the pulse width modulated signal PWM3, the inductor current signal, and the load current signal (top to bottom);

FIG. 11 is a flowchart of a method for providing a voltage rail to a CPU according to an embodiment of the present invention.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or features.

Detailed Description

Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following detailed description of the present invention, numerous details are set forth in order to provide a better understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. A detailed description of some specific structures and functions is simplified herein for clarity in setting forth the invention. In addition, similar structures and functions that have been described in detail in some embodiments are not repeated in other embodiments. Although the terms of the present invention have been described in connection with specific exemplary embodiments, the terms should not be construed as limited to the exemplary embodiments set forth herein.

Throughout the specification, reference to "one embodiment," "an embodiment," "one embodiment," or "an embodiment" means: the particular features, structures, or characteristics described in connection with the embodiment or embodiments are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one embodiment," or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment or embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to like elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

FIG. 1 is a block circuit diagram of a computing device according to an embodiment of the invention. In the embodiment shown in FIG. 1, the computing device may comprise a handheld computer, desktop computer, server, or other computing device. Moreover, for the sake of brevity and clarity, FIG. 1 does not show other components of the computing device such as memory, input/output devices, storage devices, etc., which are not necessary to an understanding of the present invention.

In the embodiment shown in FIG. 1, the computing device includes a processor 101 and a power supply. The power supply includes, among other things, a power supply controller 103 and a plurality of voltage regulators 102(102-1, 102-2, and 102-3). In one embodiment, the power supply controller 103 and the plurality of voltage regulators 102 are each separate integrated circuits.

In one embodiment, processor 101 may be a RYZEN series processor manufactured by AMD, and voltage regulator 102 may use an lntelli-phase series voltage regulator from core source systems limited (MPS) of san jose, ca. In embodiments of the present application, the power supply controller may implement the present disclosure using a commercial power supply controller, such as an MPS-provided MP2945 power supply controller. It will be appreciated that embodiments of the invention are equally applicable to other processors, voltage regulators and power controllers.

In the embodiment of fig. 1, processor 101 is powered by first voltage RAIL1 and second voltage RAIL 2. In one embodiment, voltage regulators 102-1 and 102-2 are configured as a multi-phase voltage regulator for generating a first voltage RAIL1, where first voltage RAIL1 has a voltage of 1.55V and a current of 50A. In one embodiment, voltage regulator 102-1 provides a first phase voltage of a first voltage RAIL RAIL 1; voltage regulator 102-2 provides a second phase voltage of first voltage RAIL 1. Voltage regulator 102-3 is configured as a single-phase voltage regulator for generating a second voltage RAIL2 having a voltage of 1.55V and a current of 17A. First voltage RAIL1, which is a multi-phase voltage RAIL, is also referred to as a "high current RAIL" and second voltage RAIL2 is also referred to as a "low current RAIL".

The processor 101 sends power management instructions to the power controller 103 via a serial data bus 107, which in the embodiment of fig. 1 includes a data transmission line for sending a data signal SVD and a clock transmission line for sending a clock signal SVC. Serial data bus 107 also includes transmission lines that provide telemetry signal SVT to processor 101. In one embodiment, the serial data bus 107 conforms to the AMD SVI 2.0 serial bus standard. It will be appreciated that embodiments of the present invention may be equally applicable to other data buses, including parallel voltage identification data buses.

The processor 101 may set the voltage values of the various voltage rails by sending corresponding power management instructions to the power controller 103. Processor 101 may also send power management instructions to set the operating mode of the voltage regulator. For example, processor 101 may set the operating mode of a multi-phase voltage regulator comprised of voltage regulators 102-1 and 102-2. Such as the embodiment described in more detail below, under light load (i.e., low load current) conditions, the voltage regulator 102-3 may operate in DCM, ignoring the operating mode instruction issued by the processor 101.

In the embodiment of fig. 1, the power supply controller 103 includes a Pulse Width Modulation (PWM) generator 104, a plurality of data registers 105, and a serial data bus interface 106. Serial data bus interface 106 receives clock signal SVC and data signal SVD and cooperates with clock signal SVC to read data signal SVD to detect 101 one or more power management commands sent by the processor. The serial data bus interface 106 configures the data register 105 according to power management instructions received from the processor 101 and performs other related operations. Serial data bus interface 106 is also used to collect power telemetry data, such as operating temperature, fault conditions, etc., and transmit the telemetry data to processor 101 in the form of telemetry data signals SVT over serial data bus 107. In one embodiment, the parameters of the power controller 103 may be programmed in Firmware (Firmware)108, which includes program code stored in non-volatile memory.

In the embodiment of fig. 1, voltage regulator 102 includes pin PWM, pin VIN, pin CS, and pin VOUT. Wherein, the pin PWM is used for receiving a PWM signal from the PWM generator 104; the pin VIN is used for receiving an input voltage VIN from the outside; pin CS is used to output a current sampling signal CS to PWM generator 104, where current sampling signal CS represents the inductor current in voltage regulator 102; pin VOUT is used to provide an output voltage signal VOUT to processor 101. In addition, the PWM generator 104 detects the output voltage signal VOUT output from the voltage regulator 102 through a corresponding pin, and generates a voltage detection signal VOSEN representing the output voltage signal VOUT.

In the embodiment shown in FIG. 1, PWM generator 104 samples the output voltage signal VOUT of voltage regulators 102-1 and 102-2 (i.e., first voltage RAIL RAIL1) and generates a first voltage sense signal VOSEN1 representative of first voltage RAIL RAIL 1. Meanwhile, the PWM generator 104 samples the output voltage signal VOUT of the voltage regulator 102-3 (i.e., the second voltage RAIL2) and generates a second voltage sense signal VOSEN2 representative of the second voltage RAIL 1.

In the embodiment shown in FIG. 1, PWM generator 104 samples the inductor current signal of voltage regulator 102-1 and generates a current sample signal CS1 representative of the inductor current of voltage regulator 102-1; sampling the inductor current of the voltage regulator 102-2 and generating a current sampling signal CS2 representative of the inductor current of the voltage regulator 102-2; samples the inductor current of the voltage regulator 102-3 and generates a current sample signal CS3 representative of the inductor current of the voltage regulator 102-3. In one embodiment, the load current drawn by processor 101 from a voltage rail may be represented by the average of the sum of the inductor currents of voltage regulator 102 that generated the voltage rail. For example, in the embodiment shown in fig. 1, the average of the current sample signal CS1 and the current sample signal CS2 detected by the PWM generator 104 may represent the load current drawn by the processor 101 from the first voltage RAIL 1. In one embodiment, the summation of the current sample signals may be performed by a summation circuit (not shown), and the summed sum signal may then be averaged by the power controller 103.

In one embodiment, the PWM generator 104 is configured to generate a PWM signal to control the voltage regulator 102 by pulse width modulation. For example, in the embodiment shown in FIG. 1, the PWM generator 104 generates the pulse width modulated signal PWM1 for controlling the voltage regulator 102-1, the pulse width modulated signal PWM2 for controlling the voltage regulator 102-2, and the pulse width modulated signal PWM3 for controlling the voltage regulator 102-3. In one embodiment, the PWM generator 104 generates the PWM signal PWM for controlling one of the voltage regulators 102 according to the sampled output voltage signal VOUT of the voltage regulator 102 and the current sampling signal CS of the inductor current signal thereof. In one embodiment, the PWM signal has a first state and a second state. For example, the first state is a logic high state; the second state is a logic low state. In other embodiments, the PWM signal may also include a third state. For example: the first state is a logic high state; the second state is a logic low state; the third state is a high impedance state.

The voltage value of voltage RAIL1 or voltage RAIL2 may be set by processor 101 sending a corresponding power management command over serial data bus 107. The serial data bus interface 106 receives the power management command that sets the voltage rail voltage value and stores the command in one of the plurality of registers 105. The PWM generator 104 reads the power management command for setting the voltage value of the voltage rail from the register 105 and generates a corresponding PWM signal, thereby controlling the corresponding voltage regulator 102 to adjust its output voltage signal VOUT to the output voltage value indicated in the power management command.

Fig. 2 is a circuit schematic of the voltage regulator 102 according to an embodiment of the invention. In the embodiment of fig. 2, the voltage regulator 102 includes a high-side transistor M1 and a low-side transistor M2. When the high-side transistor M1 is turned on and the low-side transistor M2 is turned off, the input voltage VIN is coupled to the load while current flows to the load through the high-side transistor M1 and the output inductor L1. When the high-side transistor M1 is turned off and the low-side transistor M2 is turned on, current freewheels through the low-side transistor M2 and the output inductor L1. The current through the output inductor L1 is the inductor current. The inductor current is used to charge the output capacitor C1, thereby generating the output voltage signal VOUT. The current sampling circuit 204 samples the inductor current and generates a corresponding current sampling signal CS. The output inductor L1 and the output capacitor C1 may be discrete components that are separately located outside of the integrated circuit, while other components of the voltage regulator 102 may be packaged within the same integrated circuit.

The PWM logic 205 receives PWM signals generated by the PWM generator 104 (see fig. 1) that drive the high-side transistor M1 and the low-side transistor M2 via the driver circuits 201 and 202, respectively. During load transients, PWM generator 104 will maintain output voltage signal VOUT at the voltage level set by the power management command by adjusting the frequency of the PWM signal. In one embodiment, as the load current increases, the PWM generator 104 maintains the output voltage signal VOUT at the voltage value set by the power management command by increasing the frequency of the PWM signal; when the load current decreases, the PWM generator 104 maintains the output voltage signal VOUT at the voltage level set by the power management command by decreasing the frequency of the PWM signal.

In the embodiment shown in fig. 2, the voltage regulator 102 further includes a zero-crossing current detection circuit 203 for detecting whether the inductor current crosses zero. In one embodiment, when the PWM signal is in the first state, the high-side transistor M1 is turned on and the low-side transistor M2 is turned off. When the PWM signal is in the second state, the high-side transistor M1 is turned off and the low-side transistor M2 is turned on. When the PWM signal is tristated, the high-side transistor M1 is turned off, and whether the low-side transistor M2 is turned off is determined by the inductor current. When the PWM signal is tristated, if the inductor current is reduced to zero, the PWM logic 205 will turn off the low side transistor M2 to prevent inductor current from flowing in the reverse direction.

Fig. 3 is a schematic circuit diagram of the PWM generator 104 according to an embodiment of the present invention. Fig. 3 is a schematic diagram of a circuit in which the PWM generator 104 generates a phase PWM signal for controlling a corresponding one of the voltage regulators 102 (see fig. 1). Circuits for generating PWM signals for other phases are similar and will not be described again for the sake of brevity.

In the embodiment shown in fig. 3, PWM generator 104 receives an output voltage sample signal VOSEN that is representative of the output voltage signal VOUT of voltage regulator 102. The analog-to-digital converter 271 converts the output voltage sampling signal VOSEN into a digital signal and sends the digital signal to the PWM control circuit 273. Similarly, the analog-to-digital converter 272 converts the LOAD CURRENT signal LOAD CURRENT to a digital signal and provides the digital signal to the PWM control circuit 273. In one embodiment, for voltage regulators 102-1 and 102-2, LOAD CURRENT signal LOAD CURRENT is the average of CURRENT sampling signal CS1 and CURRENT sampling signal CS 2; for voltage regulator 102-3, LOAD CURRENT signal LOAD CURRENT is an average value of CURRENT sampling signal CS 3.

In the embodiment of fig. 3, the power management instruction received from processor 101 will be stored in register 105. The processor 101 issues power management instructions for each voltage rail, such as a set voltage rail voltage value instruction, a set operating mode instruction, and so forth. Register 105 may store an instruction issued by processor 101 to set the voltage rail voltage value, for example, in the embodiment shown in FIG. 3, the instruction to set the voltage rail voltage value is a value represented by an 8-bit binary code ("SVID [ 7: 0 ]"). The PWM control circuit 273 will cause the voltage regulator 102 to maintain the voltage of the voltage rail at the voltage value commanded by the command as the load current changes by adjusting the pulse width of the PWM signal.

The register 105 may also store operating mode instructions from the processor 101. In the embodiment of fig. 3, register 105 includes two operating mode indication bits PSI0 and PSI 1. The operating mode indicating bits PSI0 and PSI1 are used to indicate operating mode instructions issued by the processor 101 that comply with the SVI 2.0 standard specified by AMD, and indicate the status as follows:

PSI0 ═ 0, PSI1 ═ 0 denotes full phase CCM mode;

PSI0 ═ 1, PSI1 ═ 0 denotes single-phase CCM mode;

PSI0 ═ 1, PSI1 ═ 1 denotes single-phase DCM mode.

Specifically, when the operating mode indicator bits PSIO and PSl1 are not asserted (i.e., both are "0"), the voltage regulator operates in full phase CCM mode; when both PSI0 and PSI1 are assigned values (i.e., both "1"), the voltage regulator operates in single-phase DCM; when the PSI0 is assigned (i.e., is "1") and the PSI1 is not assigned (i.e., is "0"), the voltage regulator operates in single-phase CCM. In one embodiment, a full phase CCM mode refers to a multi-phase voltage regulator in which all phase circuits (i.e., voltage regulators) operate in CCM mode. For example, in the embodiment shown in FIG. 1, when a multi-phase voltage regulator consisting of voltage regulator 102-1 and voltage regulator 102-2 operates in a full-phase CCM mode, it means that both voltage regulator 102-1 and voltage regulator 102-2 operate in CCM mode. It will be appreciated by those skilled in the art that the present application illustrates only a multi-phase voltage regulator comprising a two-phase voltage regulator, and that in other embodiments, the multi-phase voltage regulator may comprise any number of phase voltage regulators. In one embodiment, single-phase CCM mode refers to only one voltage regulator operating in CCM mode; single-phase DCM mode refers to only one voltage regulator operating in DCM mode.

In one embodiment, the power controller 103 controls the voltage regulators 102-1 and 102-2 to generate the first voltage RAIL RAIL1 according to the operating mode instructions issued by the processor 101. That is to say: when neither of the operating mode indicator bits PSIO and PSl1 is asserted, the power controller 103 will control the voltage regulators 102-1 and 102-2 to operate in the full phase CCM mode; when the operating mode indication bits PSIO and PSl1 are both asserted, the power controller 103 will control the voltage regulators 102-1 and 102-2 to operate in the single-phase DCM mode; when the operating mode indicator bit PSI0 is asserted and PSI1 is not asserted, the power controller 103 will control the voltage regulators 102-1 and 102-2 to operate in single-phase CCM mode.

In one embodiment, power controller 103 ignores the operating mode instruction issued by processor 101 and independently controls voltage regulator 102-3 to generate second voltage RAIL RAIL 2. That is to say: the power controller 103 controls the power regulator 102-3 to generate the second voltage RAIL RAIL2 independent of the processor-issued operating mode command. For example, even if the operating mode command issued by the processor 101 requires the voltage regulator 102-3 to operate in the single-phase CCM mode, the power controller 103 may still independently control the voltage regulator 102-3 to operate in the DCM mode. In addition to this operating mode instruction, power controller 103 needs to follow other power management instructions issued by the processor for voltage RAIL2, such as a power management instruction that changes the voltage value of voltage RAIL 2. In one embodiment, various actions by power controller 103 to control voltage regulator 102-3 may be implemented by programming in firmware 108.

Fig. 4 is a graph illustrating the efficiency of the voltage regulator as a function of load current in different operating modes. In the embodiment of fig. 4, the vertical axis represents the change in efficiency in percent and the horizontal axis represents the change in load current in amperes. In one embodiment, the voltage regulators 102-1 and 102-2 may be configured as multi-phase voltage regulators operating in a full-phase CCM mode, a single-phase CCM mode, or a single-phase DCM mode. The voltage regulator 102-3, on the other hand, is a single-phase voltage regulator and may be configured to operate in either a single-phase CCM mode or a single-phase DCM mode.

In the embodiment shown in fig. 4, curve 301 is the efficiency-current curve of the voltage regulator operating in single-phase DCM mode; curve 302 is the efficiency-current curve of the voltage regulator operating in single-phase CCM mode; curve 303 is the efficiency-current curve for the voltage regulator operating in full phase CCM mode. As shown in fig. 4, the voltage regulator will preferably operate in full phase CCM mode at high load currents; will preferably operate in single phase CCM mode at medium load current; it will be preferable to operate in single phase DCM mode at low load currents. Processor 101 places the voltage regulator in an operating state that processor 101 considers best suited for its current load requirements by setting the operating mode indicator bits (PSI0 and PSI 1).

Fig. 5 is a graph illustrating the efficiency of the voltage regulator as a function of load current for different operating modes. In the embodiment of fig. 5, the vertical axis represents the change in efficiency in percent and the horizontal axis represents the change in load current in amperes. Curve 301 is the efficiency versus current curve for a voltage regulator operating in single-phase DCM, while curve 302 is the efficiency versus current curve for a voltage regulator operating in single-phase CCM. As shown in fig. 5, when the load current decreases to the intersection 311 of the curve 301 and the curve 302, the processor 101 transitions the control voltage regulator from the single-phase CCM mode to the single-phase DCM mode. In the embodiment shown in fig. 5, the processor 101 may switch between different modes by assigning or not assigning PSI0 and PSI1 to the operating mode indicator bits.

Fig. 6 and 7 are graphs showing power loss of the voltage regulator as a function of load current, wherein the vertical axis represents power loss in watts and the horizontal axis represents load current in amperes. Curve 301 is the power loss versus current curve for a voltage regulator operating in single-phase DCM, while curve 302 is the power loss versus current curve for a voltage regulator operating in single-phase CCM.

As shown in fig. 6, at low load currents, the processor 101 should simultaneously assign the operating mode indicator bits PSI0 and PSI1 (i.e., both assign "1") such that the voltage regulator operates in single-phase DCM to reduce power loss. In the embodiment shown in fig. 6, the low load current refers to the region left of the intersection point 321 between the curve 301 and the curve 302. However, as shown in fig. 7, in some cases, if the processor 101 does not timely assign the operating mode indicator bit PSI1 under low load current conditions, the voltage regulator can only continue to operate in single-phase CCM mode. At this point, the single-phase CCM mode will cause the voltage regulator to add additional power loss (as indicated by arrow 322) compared to the single-phase DCM mode.

Fig. 8 is a timing diagram of the PWM signal, the inductor current signal, and the load current signal (top to bottom) when the voltage regulator is operating in single-phase CCM mode. In the embodiment of fig. 8, the power controller 103 generates a PWM signal to control the voltage regulator to operate in the single-phase CCM mode according to the operating mode command issued by the processor 101. In CCM mode, the PWM signal generated by the power controller 103 controls the high-side and low-side transistors (such as the high-side transistor M1 and the low-side transistor M2 shown in fig. 2) of the voltage regulator to switch synchronously. That is, in CCM mode, the PWM signal is either in a first state (e.g., a logic high state) or a second state (e.g., a logic low state) to maintain continuity of the inductor current without the presence of a third state. As shown in fig. 8, when the PWM signal is logic high, the high-side transistor M1 is turned on, the low-side transistor M2 is turned off, and the inductor current increases; when the PWM signal is logic low, the high-side transistor M1 is turned off, the low-side transistor M2 is turned on, and the inductor current decreases. Meanwhile, it is also apparent from the inductor current waveform in fig. 8 that: in the low load current situation (as indicated by arrow 453 in fig. 8), the inductor current will reverse to become negative because the voltage regulator is still operating in CCM mode, which will result in increased power loss.

Fig. 9 is a graph illustrating power loss versus load current for a voltage regulator operating in DCM, where the vertical axis represents power loss in watts and the horizontal axis represents load current in amperes. Curve 301 is the power loss versus current curve for a voltage regulator operating in single-phase DCM, while curve 302 is the power loss versus current curve for a voltage regulator operating in single-phase CCM.

In one embodiment, the voltage regulator 102-3 is not affected by the change in the operating mode indicator bit assignment state and can be independently controlled to transition from the single-phase CCM mode to the single-phase DCM mode. More specifically, under low load current conditions, even if the operating mode indicator bits PSI0 and PSI1 indicate that the processor 101 requires the voltage regulator 102-3 to operate in the single-phase CCM mode, the power controller 103 can independently generate the pulse width modulation signal PWM3 to control the voltage regulator 102-3 to operate in the single-phase DCM mode. The power loss of the voltage regulator 102-3 operating in the single-phase DCM mode is significantly reduced compared to operating in the single-phase CCM mode (see arrow 324).

Fig. 10 is a timing diagram of the PWM signal PWM3, the inductor current signal, and the load current signal (top to bottom). In the embodiment of fig. 10, the power controller 103 ignores the operation mode instruction issued by the processor 101 and the independent control voltage regulator 102-3 operates in the single-phase DCM mode.

As shown in fig. 10, the pulse width modulated signal PWM3 generated by the power supply controller 103 has a third state in addition to the first and second states. While adjusting the frequency of the pulse width modulation signal PWM3 such that the voltage of the second voltage RAIL2 is maintained at the voltage value indicated by the power management command issued by the processor 101. When the pulse width modulation signal PWM3 is high, the inductor current increases; when the pulse width modulated signal PWM3 is low, the inductor current decreases. In the case of a low load current, the switching frequency of the pulse width modulated signal PWM3 is reduced, and at the same time, the power supply controller 103 inserts the third state between the first state and the second state of the pulse width modulated signal PWM 3. In one embodiment, the duration that the PWM signal PWM3 is tristated is at least as long as the inductor current is reduced to zero. In one embodiment, if the inductor current is reduced to zero while the PWM signal PWM3 is in the tristate state (as shown by arrow 451), the voltage regulator 102-3 will turn off the low-side transistor M2 to prevent the inductor current from reversing (as shown by arrow 452). At this time, since both the high-side transistor M1 and the low-side transistor M2 are in an off state at this time, no inductor current flows, and thus the voltage regulator 102-3 enters a single-phase DCM mode of operation. As the load current increases, the frequency of the PWM3 signal increases to maintain the voltage RAIL2 at the voltage level indicated by the power management command. Meanwhile, when the frequency of the PWM signal PWM3 increases, the inductor current increases, and the voltage regulator 102-3 automatically enters the single-phase CCM mode. It can also be seen from the waveform diagram that even if the pulse width modulated signal PWM3 is tristated, the voltage regulator 102-3 will not turn off the low side transistor M2 if the inductor current is not reduced to zero. From the above, the voltage regulator 102-3 can automatically switch between the single-phase DCM mode and the single-phase CCM mode without following the operation mode command issued by the processor 101.

FIG. 11 is a flowchart of a method for providing a voltage rail to a CPU according to an embodiment of the present invention. The method shown in fig. 11 may be implemented by the modules shown in fig. 1. It is to be understood that other modules may be used to implement the invention without detracting from the advantages of the invention. The method comprises steps 501-504.

In step 501, a first control signal (e.g., PWM1) drives a first voltage regulator to generate a first voltage rail, where the first voltage rail is used to supply power to a CPU.

Step 502, the second control signal drives the second voltage regulator to generate a second voltage rail for supplying power to the CPU, wherein the second voltage rail is used for supplying power to the CPU.

Step 503, controlling the first voltage regulator to work in the first working mode according to the first power management instruction sent by the CPU. The power management instructions may be received from the CPU over a serial data bus. Wherein the first operating mode comprises instructing the first voltage regulator to operate in a CCM mode or other conduction mode.

Step 504, ignoring a second working mode indicated by a second power management instruction sent by the CPU, and controlling the second voltage regulator to work in the DCM mode. For example, the second operating mode includes instructing the second voltage regulator to operate in CCM mode instead of DCM mode. As another example, at low load current, the second power management command issued by the CPU will be ignored and the second voltage regulator will operate in DCM.

In one embodiment, the second voltage regulator is required to follow other power management instructions received from the CPU. For example, the method for providing the voltage rail by the CPU further includes step 505. In step 505, the second voltage regulator adjusts a voltage level of a second voltage rail generated by the second voltage regulator according to a third power management command issued by the CPU.

While the system and method for providing a voltage rail to a CPU has been described with reference to several exemplary embodiments, it is to be understood that the terminology used is that of the specification and examples, rather than of the limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.