1. A clock domain synchronization method of an FPGA chip based on a recovered clock is applied to the FPGA chip, and is characterized in that the FPGA chip comprises a SerDes receiving module and a clock selection module, and the method comprises the following steps:

the SerDes receiving module extracts a recovered clock from a digital signal sent by an opposite end, performs clock jitter removal and locking signal generation on the recovered clock after the recovered clock is determined to be stable, and outputs the locking signal and the jitter-removed recovered clock to the clock selection module;

and when the clock selection module receives the locking signal, setting the received recovery clock as a working reference clock, so that other modules in the FPGA chip can perform in-chip data transmission on the digital signal by using the working reference clock.

2. The recovered clock-based FPGA chip clock domain synchronization method of claim 1, wherein the FPGA chip further comprises a SerDes transmitter module, further comprising, after setting the received recovered clock to the working reference clock:

and the SerDes sending module sends the digital signals generated by the other modules to the opposite terminal by using the working reference clock.

3. The method for synchronizing clock domains of an FPGA chip based on recovered clocks of claim 1, wherein before said SerDes receiving module extracts a recovered clock from a digital signal transmitted from an opposite end, further comprising:

when the FPGA chip is powered on, the clock selection module sets a default reference clock of the FPGA chip as an initialization reference clock so that each module in the FPGA chip is initialized by using the initialization reference clock;

and the SerDes receiving module executes the step of extracting the recovered clock from the digital signal sent from the opposite end after the initialization is finished.

4. The FPGA chip clock domain synchronization method based on a recovered clock of claim 1, wherein the clock debounce the recovered clock and output the debounced recovered clock to the clock selection module comprises:

the SerDes receiving module outputs the recovered clock to an off-chip clock chip;

and the off-chip clock chip is used for carrying out clock jitter removal on the recovered clock and outputting the recovered clock subjected to clock jitter removal to the clock selection module.

5. The recovered clock-based FPGA chip clock domain synchronization method of claim 1, wherein the clock selection module is implemented using a PLL module or a SerDes reconfiguration interface of the FPGA chip.

6. An FPGA chip clock domain synchronization system based on a recovered clock is characterized by comprising an FPGA chip, wherein the FPGA chip comprises a SerDes receiving module and a clock selection module,

the SerDes receiving module is configured to extract a recovered clock from a digital signal sent by an opposite end, perform clock debouncing and generate a locking signal for the recovered clock after it is determined that the recovered clock is stable, and output the locking signal and the debouncing recovered clock to the clock selection module;

and the clock selection module is used for setting the received recovery clock as a working reference clock when the locking signal is received, so that other modules in the FPGA chip can carry out on-chip data transmission on the digital signal by using the working reference clock.

7. The recovered clock based FPGA chip clock domain synchronization system of claim 6, wherein the FPGA chip further comprises a SerDes transmit module, wherein,

and the SerDes sending module is used for sending the digital signals generated by the other modules to the opposite terminal by using the working reference clock.

8. The recovered clock based FPGA chip clock synchronization system of claim 6,

the clock selection module is further configured to set a default reference clock of the FPGA chip as an initialization reference clock when the FPGA chip is powered on, so that each module in the FPGA chip is initialized by using the initialization reference clock;

the SerDes receiving module is further configured to perform the step of extracting the recovered clock from the digital signal sent from the opposite end after the initialization is completed.

9. The clock domain synchronization system of a recovered clock based FPGA chip of claim 6, further comprising: an off-chip clock chip, wherein,

the SerDes receiving module is also used for outputting the recovered clock to the off-chip clock chip;

the off-chip clock chip is used for performing clock jitter removal on the recovered clock and outputting the recovered clock after clock jitter removal to the clock selection module.

10. A storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the recovered clock based FPGA chip clock domain synchronization method of any one of claims 1 to 5.

Background

With the continuous development of financial technology, the demand of low-delay transaction in the financial field is increasingly strong. Based on the delayed income brought by the traditional software acceleration technology, the requirements of various transaction processing and response are more and more difficult to meet. Therefore, the technology based on FPGA hardware parallel acceleration gradually enters the field of security trading and becomes a new trend in the field of financial science and technology.

In the related technology, each module inside the FPGA chip is independent of each other, and uses its own clock domain to perform data transmission, and the modules use asynchronous FIFO buffers to perform clock domain conversion. The mode needs clock domain conversion when data transmission between modules is carried out each time, transmission time delay in the chip is increased, overall data response and processing efficiency of the FPGA chip are reduced, and low-time-delay application effect of the FPGA chip in the financial field is affected.

Disclosure of Invention

The invention aims to provide a clock domain synchronization method, a clock domain synchronization system and a storage medium of an FPGA chip based on a recovered clock, which can adopt a clock selection module to unify working reference clocks in the FPGA chip, further ensure that clock domain conversion is not needed during data transmission between modules, and finally effectively improve the efficiency of data transmission in a chip.

In order to solve the technical problem, the invention provides a clock domain synchronization method of an FPGA chip based on a recovered clock, which is applied to the FPGA chip, wherein the FPGA chip comprises a SerDes receiving module and a clock selection module, and the method comprises the following steps:

the SerDes receiving module extracts a recovered clock from a digital signal sent by an opposite end, performs clock jitter removal and locking signal generation on the recovered clock after the recovered clock is determined to be stable, and outputs the locking signal and the jitter-removed recovered clock to the clock selection module;

and when the clock selection module receives the locking signal, setting the received recovery clock as a working reference clock, so that other modules in the FPGA chip can perform in-chip data transmission on the digital signal by using the working reference clock.

Optionally, the FPGA chip further includes a SerDes sending module, and after setting the received recovered clock as a working reference clock, further includes:

and the SerDes sending module sends the digital signals generated by the other modules to the opposite terminal by using the working reference clock.

Optionally, before the SerDes receiving module extracts the recovered clock from the digital signal transmitted from the opposite end, the method further includes:

when the FPGA chip is powered on, the clock selection module sets a default reference clock of the FPGA chip as an initialization reference clock so that each module in the FPGA chip is initialized by using the initialization reference clock;

and the SerDes receiving module executes the step of extracting the recovered clock from the digital signal sent from the opposite end after the initialization is finished.

Optionally, the clock debounce the recovered clock, and output the debounced recovered clock to the clock selection module, where the clock debounce includes:

the SerDes receiving module outputs the recovered clock to an off-chip clock chip;

and the off-chip clock chip is used for carrying out clock jitter removal on the recovered clock and outputting the recovered clock subjected to clock jitter removal to the clock selection module.

Optionally, the clock selection module is implemented by using a PLL module or a SerDes reconfiguration interface of the FPGA chip.

The invention also provides an FPGA chip clock domain synchronization system based on the recovered clock, which comprises an FPGA chip, wherein the FPGA chip comprises a SerDes receiving module and a clock selection module,

the SerDes receiving module is configured to extract a recovered clock from a digital signal sent by an opposite end, perform clock debouncing and generate a locking signal for the recovered clock after it is determined that the recovered clock is stable, and output the locking signal and the debouncing recovered clock to the clock selection module;

and the clock selection module is used for setting the received recovery clock as a working reference clock when the locking signal is received, so that other modules in the FPGA chip can carry out on-chip data transmission on the digital signal by using the working reference clock.

Optionally, the FPGA chip further includes a SerDes transmit module, wherein,

and the SerDes sending module is used for sending the digital signals generated by the other modules to the opposite terminal by using the working reference clock.

Alternatively,

the clock selection module is further configured to set a default reference clock of the FPGA chip as an initialization reference clock when the FPGA chip is powered on, so that each module in the FPGA chip is initialized by using the initialization reference clock;

the SerDes receiving module is further configured to perform the step of extracting the recovered clock from the digital signal sent from the opposite end after the initialization is completed.

Optionally, the method further comprises: an off-chip clock chip, wherein,

the SerDes receiving module is also used for outputting the recovered clock to the off-chip clock chip;

the off-chip clock chip is used for performing clock jitter removal on the recovered clock and outputting the recovered clock after the clock jitter removal to the clock selection module.

The invention also provides a storage medium, wherein the storage medium is stored with a computer program, and the computer program is executed by a processor to realize the steps of the FPGA chip clock domain synchronization method based on the recovered clock.

The invention discloses a clock domain synchronization method of an FPGA chip, which is applied to the FPGA chip, wherein the FPGA chip comprises a SerDes receiving module and a clock selection module, and the method comprises the following steps: the SerDes receiving module extracts a recovered clock from a digital signal sent by an opposite end, performs clock jitter removal on the recovered clock and generates a locking signal after the recovered clock is determined to be stable, and finally outputs the locking signal and the jitter-removed recovered clock to the clock selection module; and when the clock selection module receives the locking signal, setting the received recovery clock as a working reference clock, so that other modules in the FPGA chip can perform in-chip data transmission on the digital signal by using the working reference clock.

Therefore, the method firstly unifies the working reference clocks of the modules in the FPGA chip by adopting the clock selection module, so that the working reference clocks of the modules are synchronous, thereby ensuring that clock domain conversion is not needed when data transmission is carried out among the modules, effectively avoiding the clock domain conversion operation existing when data transmission in the chip is carried out in the related technology, reducing the data transmission time delay in the FPGA chip and improving the data transmission efficiency; meanwhile, the working reference clock in the method is extracted from the digital signal sent by the opposite terminal, so that the digital signal can be received by the FPGA chip and can be subjected to data transmission in the chip without clock domain conversion, the transmission efficiency of the digital signal in the chip can be further ensured, the FPGA chip can also be ensured to directly work according to the signal transmission condition of the opposite terminal, the data transmission time delay in the FPGA chip can be further reduced, the data transmission efficiency in the chip can be improved, the response and processing efficiency of the integral data of the FPGA chip can be improved, and the FPGA chip can be better adapted to the low time delay requirement in the financial field. The invention also provides an FPGA chip clock domain synchronization system based on the recovered clock and a storage medium, and has the beneficial effects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic diagram of an FPGA clock domain setting in the prior art according to an embodiment of the present invention;

fig. 2 is a flowchart of a clock domain synchronization method of an FPGA chip based on a recovered clock according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an FPGA clock domain setting according to an embodiment of the present invention;

fig. 4 is a block diagram of a clock domain synchronization system of an FPGA chip based on a recovered clock according to an embodiment of the present invention;

fig. 5 is a block diagram of a second clock domain synchronization system of an FPGA chip based on a recovered clock according to an embodiment of the present invention;

fig. 6 is a block diagram of a third clock domain synchronization system of an FPGA chip based on a recovered clock according to an embodiment of the present invention;

fig. 7 is a block diagram of a fourth clock domain synchronization system of an FPGA chip based on a recovered clock according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the related technology, each module inside the FPGA chip is independent of each other, and uses its own clock domain to perform data transmission, and the modules use asynchronous FIFO buffers to perform clock domain conversion. Referring to fig. 1, fig. 1 is a schematic diagram of a clock domain setting of an FPGA in the prior art according to an embodiment of the present invention. In this example, the FPGA may be divided into 4 parts according to the clock domain, which are a service logic part, an ethernet mac, a physical layer receiving part, and a physical layer transmitting part, where the reference clocks of the parts are clk _ ref0, clk _ ref1, clk _ ref2, and clk _ ref3 respectively when data transmission is performed, and the clocks used when data processing are clk _ sys, clk _ mac, clk _ servers _ rx, and clk _ servers _ tx respectively; asynchronous FIFO (First In First out) buffers (a sending buffer 1, a sending buffer 2 and a receiving buffer 1, a receiving buffer 2) are arranged among the parts, the asynchronous FIFO buffers are used for clock domain conversion, when the business logic needs to send data, the data needs to be processed by two stages of clock domain crossing, the data firstly crosses to a clk _ mac clock domain through the sending buffer 1 from a clk _ sys clock domain, after the mac internal processing is finished, the data crosses to the clk _ serdes _ tx clock domain through the sending buffer 2 from the clk _ mac clock domain, and finally the data is sent and output through a physical layer; when the service logic receives data, it also needs to be processed by two-stage clock domain crossing, and the data of the physical layer receiving module firstly crosses to the clk _ mac clock domain from the clk _ servers _ rx clock domain through the receiving buffer 1, and then crosses to the clk _ sys clock domain from the clk _ mac clock domain through the receiving buffer 2. According to the mode, clock domain conversion is needed when data transmission between the modules is carried out each time, so that the data transmission efficiency between the modules is reduced, and the overall data processing efficiency of the FPGA chip is reduced. In view of this, the present invention provides a clock domain synchronization method for an FPGA chip, which can unify a working reference clock in the FPGA chip by using a clock selection module, thereby ensuring that clock domain conversion is not required during data transmission between modules, and finally, the efficiency of data transmission in a chip can be effectively improved. Referring to fig. 2, fig. 2 is a flowchart of a clock domain synchronization method of an FPGA chip based on a recovered clock according to an embodiment of the present invention, where the method is applied to the FPGA chip, and the FPGA chip includes a SerDes receiving module and a clock selecting module, and may include:

s201, the SerDes receiving module extracts a recovered clock from the digital signal sent by the opposite terminal, after the recovered clock is determined to be stable, the recovered clock is subjected to clock jitter removal and a locking signal is generated, and the locking signal and the jitter-removed recovered clock are output to the clock selection module.

It can be understood that, in order to unify the reference clock for data transmission inside the FPGA chip, a reference clock source needs to be determined first, and then the reference clock source can be set as the unified reference clock. In the embodiment of the invention, a recovery clock is extracted from a digital signal sent by an opposite terminal, and the recovery clock is used as a reference clock source, because a SerDes receiving module (SerDes _ rx) processes the digital signal, the recovery clock is used as a reference clock for data transmission, and the processed digital signal is output, so that if the recovery clock is set as a uniform reference clock, the digital signal can be freely transmitted in an FPGA chip without time domain conversion, and the on-chip transmission efficiency of the digital signal can be ensured; meanwhile, the recovery clock is a clock signal embedded in the digital signal when the digital sending end sends the signal, and the fluctuation condition of the recovery clock can reflect the sending condition of the digital sending end and the transmission condition of the channel, so that the recovery clock is used as a uniform reference clock, the FPGA chip can be ensured to be dynamically adjusted according to the sending condition of the opposite end and the transmission condition of the channel, and the FPGA chip and the opposite end can be ensured to keep the link synchronization.

It should be noted that, the opposite end performing data transmission with the FPGA chip should use the SerDes sending module (SerDes _ tx) to perform data sending, so that it can be ensured that the same data type is used between the opposite end and the FPGA chip to perform data transmission. In addition, the embodiment of the present invention does not limit other hardware structures of the peer end. It should be noted that the embodiments of the present invention do not limit the respective working modes of the SerDes transmitting module and the SerDes receiving module, and refer to the related technology of the FPGA SerDes; the embodiment of the invention also does not limit the specific mode and process of embedding the SerDes sending module into the recovery clock and extracting the recovery clock by the SerDes receiving module, and specifically refers to the related technologies of the FPGA SerDes and the CDR circuit; the embodiment of the invention also does not limit the specific mode that the SerDes receiving module determines the stability of the recovered clock, and can refer to the related technology of the FPGA SerDes. The invention also does not limit the specific parameter value of the recovered clock and can be set according to the actual application requirements.

Further, the embodiment of the present invention does not limit the specific form of the locking signal, for example, the locking signal may be a specific high level or low level, a specific flag bit, or a small string of code strings, and may be set according to the actual application requirement as long as the information of locking the recovered clock can be transmitted to the clock selection module.

Further, in the embodiment of the present invention, the clock selection module is first configured to manage a reference clock inside the FPGA chip and send a unified reference clock to each module inside the FPGA chip. It should be noted that the embodiment of the present invention does not limit the implementation manner of the clock selection module, and may be implemented by, for example, a PLL module inside an FPGA chip, or by using a SerDes reconfiguration interface, where a PLL (phase Locked loop) represents a phase-Locked loop circuit, and may be used to manage multiple input clocks and select a specific input clock for output according to requirements; the SerDes reconfiguration interface may also implement the above-described functionality. It should be noted that, the embodiments of the present invention do not limit the specific PLL module and SerDes reconfiguration interface, and refer to the related technologies of PLL and SerDes.

In one possible case, the clock selection module is implemented using a PLL module or SerDes reconfiguration interface of an FPGA chip.

Further, it can be understood that, under the influence of factors such as channel and signal transmission strength, the recovered clock extracted by using the digital signal may have problems of poor signal quality and more jitter, and therefore, after the SerDes receiving module obtains the recovered clock, the recovered clock needs to be subjected to clock jitter removal and then input to the clock selection module. It should be noted that the embodiment of the present invention does not limit the specific process manner of clock jitter removal, and reference may be made to the related art of clock jitter removal. It is understood that the SerDes receiver module may connect the clock output pin to a separate clock debounce device and use the separate clock debounce device for clock debounce, in other words, the SerDes receiver module may output the recovered clock from the clock output pin to the clock debounce device for clock debounce as described above. It should be noted that the embodiment of the present invention does not limit the specific implementation form of the clock jitter removal apparatus, and for example, the clock jitter removal apparatus may be implemented by using a PLL module in an FPGA chip, or may be implemented by an off-chip clock chip independent from the FPGA chip. Because the off-chip clock chip can be specially used for clock debouncing, a better debouncing effect can be obtained, and the internal resources of the FPGA chip are not occupied, the off-chip clock chip can be used for realizing clock debouncing in the embodiment of the invention.

In one possible case, clock debouncing the recovered clock, outputting the debounced recovered clock to the clock selection module, may include:

step 11: the SerDes receiving module outputs the recovered clock to an off-chip clock chip;

step 12: the off-chip clock chip is used for carrying out clock jitter removal on the recovered clock and outputting the recovered clock subjected to clock jitter removal to the clock selection module.

It will be appreciated that the off-chip clock chip may connect the clock output pin to the clock input pin of the clock selection module to output the recovered clock that completes clock debounce to the clock selection module.

S202, when the clock selection module receives the locking signal, the received recovery clock is set as a working reference clock, so that other modules in the FPGA chip can carry out on-chip data transmission on the digital signal by using the working reference clock.

It should be noted that the embodiment of the present invention does not limit the specific process of setting the recovered clock to the working reference clock by the clock selection module, and may refer to the related technologies of PLL and SerDes reconfiguration interface. It will be appreciated that the clock selection module should be connected to the clock input pins of other modules in the FPGA chip in order to deliver the working reference clock to the other modules.

Further, the embodiment of the present invention does not limit other modules in the FPGA chip, and for example, the present invention may include a service module for implementing a specific service function, an ethernet mac module for parsing a data packet, or a SerDes sending module for transmitting a digital signal generated by another module to an opposite terminal, and the present invention may be configured according to actual application requirements. It can be understood that the modules all use a unified working reference clock to perform data transmission between the modules; when the module is a SerDes sending module, the SerDes sending module can also send the digital signal to the opposite end according to the working reference clock, specifically, the working reference clock can be embedded into the digital signal for sending, so that the opposite end can also utilize the working reference clock to carry out on-chip data transmission, the data transmission efficiency between the two ends can be further improved, and the link synchronization is ensured.

In one possible case, the FPGA chip further includes a SerDes transmitting module, and after setting the recovered clock as the working reference clock, the method may further include:

step 21: and the SerDes sending module sends the digital signals generated by other modules to an opposite terminal by using the working reference clock.

Finally, it can be understood that when the FPGA chip is just powered on, the internal chip also needs to refer to the clock to complete initialization. The embodiment of the invention does not limit whether each module in the FPGA chip uses the same initialization reference clock for initialization, and can be the same reference clock or different reference clocks. In order to improve the execution efficiency of the initialization stage and avoid the clock domain conversion of the initialization stage, in the embodiment of the present invention, each module in the FPGA chip may also be initialized by using the same initialization reference clock. It will be appreciated that a default reference clock internal to the FPGA chip may be used as the initialization reference clock, as the initialization phase does not involve the transfer of digital signals to the FPGA chip from an opposite end. It should be noted that, the embodiment of the present invention does not limit the specific parameter value of the default reference clock, and can be set according to the actual application requirement; the embodiment of the invention also does not limit the generation mode of the default reference clock, for example, the default reference clock can be generated by a PLL module in an FPGA chip, or can be generated by an off-chip clock chip, and can be set according to the actual application requirements.

Before the SerDes receiving module extracts the recovered clock from the digital signal transmitted from the opposite end, in one possible case, the method may further include:

step 31: when the FPGA chip is powered on, the clock selection module sets a default reference clock of the FPGA chip as an initialization reference clock so that each module in the FPGA chip is initialized by using the initialization reference clock;

step 32: and after the initialization is finished, the SerDes receiving module performs the step of extracting a recovered clock from the digital signal sent by the opposite terminal.

Based on the embodiment, the method firstly unifies the working reference clocks of the modules in the FPGA chip by adopting the clock selection module, so that the working reference clocks of the modules are synchronous, thereby ensuring that clock domain conversion is not needed when data transmission is carried out between the modules, effectively avoiding the clock domain conversion operation existing when data transmission is carried out in the chip in the related technology, reducing the data transmission time delay in the FPGA chip and improving the data transmission efficiency; meanwhile, the working reference clock in the method is extracted from the digital signal sent by the opposite terminal, so that the digital signal can be received by the FPGA chip and can be subjected to data transmission in the chip without clock domain conversion, the transmission efficiency of the digital signal in the chip can be further ensured, the FPGA chip can also be ensured to directly work according to the signal transmission condition of the opposite terminal, the data transmission time delay in the FPGA chip can be further reduced, the data transmission efficiency in the chip can be improved, the integral data response and processing efficiency of the FPGA chip can be improved, and the FPGA chip can be better adapted to the low-time-delay requirement in the financial field.

The above method is explained below with reference to a specific example. Referring to fig. 3, fig. 3 is a schematic diagram of an FPGA clock domain setup according to an embodiment of the present invention. In the figure, the FPGA chip clock domain synchronization system includes 6 parts, which are respectively a service logic, an ethernet mac, a physical layer transmission (SerDes transmission module), a physical layer reception (SerDes reception module), a clock selection module, and a clock jitter removal device, and compared with the FPGA clock domain setting manner shown in fig. 1, the system reduces asynchronous FIFO buffers between modules. When the system is powered on, the FPGA chip sends the default reference clock clk _ ref0 to the clock selection module, and the clock selection module sets clk _ ref0 as the initialization reference clock and sends the initialization reference clock to the service logic, the ethernet mac, the physical layer sending (i.e., SerDes _ tx, SerDes sending module) and the physical layer receiving (i.e., SerDes _ rx, SerDes receiving module) modules for initialization (i.e., clk _ ref ═ clk _ ref 0). Firstly, the service logic transmits data connected with the opposite terminal to the opposite terminal through the Ethernet mac and the physical layer transmission module by using the initialization reference clock clk _ ref so as to establish data connection with the opposite terminal; after the initialization is completed, the phy receiving module receives the digital signal sent by the peer end, extracts the recovered clock cdr _ clk from the digital signal, and after it is determined that cdr _ clk is stable, sends a lock flag to the clock selecting module, and inputs cdr _ clk to the clock debounce apparatus, and the clock debounce apparatus completes clock debounce. The clock jitter removing device can be realized by a PLL circuit in an FPGA chip, and can also be realized by an off-chip clock chip. After clock debounce is complete, the clock debounce sends the processed recovered clock cdr _ clk _ clear to the clock selection module. After receiving the lock flag, the clock selection module sets the working reference clock to the processed recovery clock (i.e., clk _ ref: cdr _ clk _ clear), so that each module performs on-chip data transmission by using the unified working reference clock.

The FPGA chip clock domain synchronizing system and the storage medium based on the recovered clock according to the embodiments of the present invention are introduced below, and the FPGA chip clock domain synchronizing system and the storage medium based on the recovered clock described below and the FPGA chip clock domain synchronizing method described above may be referred to in correspondence with each other.

Referring to fig. 4, fig. 4 is a block diagram of a clock domain synchronization system of an FPGA chip based on a recovered clock according to an embodiment of the present invention, which includes an FPGA chip 410 including a SerDes receiving module 411 and a clock selecting module 412, wherein,

a SerDes receiving module 411, configured to extract a recovered clock from a digital signal sent by an opposite end, perform clock debouncing and generate a locking signal for the recovered clock after it is determined that the recovered clock is stable, and output the locking signal and the debouncing recovered clock to a clock selecting module 412;

and the clock selection module 412 is configured to set the received recovered clock as a working reference clock when the lock signal is received, so that other modules in the FPGA chip perform on-chip data transmission on the digital signal by using the working reference clock.

Optionally, referring to fig. 5, fig. 5 is a block diagram of a clock domain synchronization system of a second FPGA chip based on a recovered clock according to an embodiment of the present invention, where the FPGA chip 410 further includes a SerDes sending module 413, where,

and a SerDes transmitting module 413, configured to transmit the digital signals generated by the other modules to an opposite end by using the working reference clock.

Optionally, in the system:

the clock selection module is also used for setting a default reference clock of the FPGA chip as an initialization reference clock when the FPGA chip is powered on so as to enable each module in the FPGA chip to be initialized by utilizing the initialization reference clock;

the SerDes receiving module 411 is further configured to perform a step of extracting a recovered clock from the digital signal sent from the opposite end after the initialization is completed.

Optionally, referring to fig. 6, fig. 6 is a block diagram of a third clock domain synchronization system of an FPGA chip based on a recovered clock according to an embodiment of the present invention, where the system may further include: an off-chip clock chip 420, wherein,

SerDes receive module 411, further configured to output the recovered clock to off-chip clock chip 420;

the off-chip clock chip 420 is configured to perform clock jitter removal on the recovered clock, and output the recovered clock with the clock jitter removed to the clock selection module 412.

Of course, based on the above embodiments, the present invention further provides an FPGA chip clock domain synchronization system based on the recovered clock shown in fig. 7. It should be noted that the embodiment of the present invention does not limit the specific internal components and structures of the FPGA chip; the embodiments of the present invention also do not limit the specific internal components and structures of the off-chip clock chip, as long as the functions described above can be accomplished.

The embodiment of the invention also provides a storage medium, wherein a computer program is stored on the storage medium, and when being executed by a processor, the computer program realizes the steps of the FPGA chip clock domain synchronization method based on the recovered clock in any embodiment.

Since the embodiment of the storage medium portion corresponds to the embodiment of the FPGA chip clock domain synchronization method portion, reference is made to the description of the embodiment of the FPGA chip clock domain synchronization method portion based on the recovered clock for the embodiment of the storage medium portion, and details are not described here for the moment.

The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The present invention provides a clock domain synchronization method, system and storage medium for an FPGA chip based on a recovered clock. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.