1. A semiconductor memory device, comprising:

a memory core configured to perform reading and writing of data;

a data transfer and training block coupled between the first pad and the memory core; and

at least one data transfer, clock generation, and training block connected between the at least one second pad and the memory core,

wherein, in the first training operation, the data transfer and training block outputs the first training data received through the first pad as the second training data,

wherein in the second training operation, at least one of the data transfer and training blocks outputs, through at least one of the first pads, third training data received through at least one second pad as fourth training data, and

wherein the second training data and the fourth training data are output in synchronization with the read data strobe signal output through the at least one second pad.

2. The semiconductor memory device according to claim 1, wherein each of the data transfer and training blocks includes a first-in first-out FIFO register,

wherein the at least one data transfer, clock generation and training block comprises a second FIFO register, and

wherein the first training operation and the second training operation are performed according to a FIFO register write command and a FIFO register read command.

3. The semiconductor memory device according to claim 2, wherein in the first training operation, the data transfer and training block stores the first training data received from the first pad in a corresponding first FIFO register of the data transfer and training block in response to the FIFO register write command, and

wherein, in the first training operation, the data transfer and training block is responsive to the FIFO register read command to output the first training data stored in the first FIFO register as the second training data through the first pad.

4. The semiconductor memory device according to claim 2, wherein in the second training operation, at least one of the data transfer and training block stores the third training data received from the at least one second pad in at least one first FIFO register of the at least one of the data transfer and training block in response to the FIFO register write command, and

wherein, in the second training operation, at least one of the data transfer and training blocks is responsive to the FIFO register read command to output the third training data stored in the at least one first FIFO register as the fourth training data through at least one of the first pads.

5. The semiconductor memory device according to claim 2, wherein the FIFO register write command includes different respective options in the first training operation and the second training operation.

6. The semiconductor memory device according to claim 2, wherein in the second training operation, the at least one data transfer, clock generation, and training block stores the third training data received from the at least one second pad in the second FIFO register in response to the FIFO register write command, and

wherein, in the second training operation, at least one of the data transfer and training blocks is responsive to the FIFO register read command to output the third training data stored in the second FIFO register as the fourth training data through at least one of the first pads.

7. The semiconductor memory device according to claim 2, wherein in the first training operation, the at least one data transfer, clock generation, and training block stores the third training data received from the at least one second pad in the second FIFO register in response to the FIFO register write command, and

wherein, in the second training operation, at least one of the data transfer and training blocks is responsive to the FIFO register read command to output the third training data stored in the second FIFO register as the fourth training data through at least one of the first pads.

8. The semiconductor memory device according to claim 2, wherein the FIFO register read command includes different respective options in the first training operation and the second training operation.

9. The semiconductor memory device according to claim 2, wherein the memory core includes a mode register, and

wherein the first training operation is selected in response to the mode register being programmed with a first option and the second training operation is selected in response to the mode register being programmed with a second option.

10. The semiconductor memory device according to claim 1, wherein a first one of the data transfer and training blocks sends a data bit between a first one of the first pads and the memory core, the data bit to be written to or read from the memory core.

11. The semiconductor memory device according to claim 10, wherein the data bit includes a data portion and a parity portion of the data portion.

12. The semiconductor memory device of claim 10, wherein the at least one data transfer, clock generation, and training block transmits write parity transmitted from the at least one second pad to the memory core and outputs at least one read data strobe signal through the at least one second pad.

13. The semiconductor memory device according to claim 10, wherein a second one of the data transfer and training blocks sends a data mask inversion signal sent from a second one of the first pads to the memory core, and outputs a read parity sent from the memory core to the second one of the first pads.

14. The semiconductor memory device according to claim 1, further comprising:

at least one clock generation block connected to at least one third pad,

wherein the second training data and the fourth training data are output in synchronization with a second read data strobe signal output through the at least one third pad.

15. A memory system, comprising:

a semiconductor memory; and

a controller configured to control the semiconductor memory,

wherein the semiconductor memory and the controller communicate with each other through data input and output lines, data mask inversion lines, and read data strobe lines,

wherein, in a first training operation, the controller transmits first data to the semiconductor memory through the data input and output line and the data mask inversion line and reads the first data from the semiconductor memory through the data input and output line and the data mask inversion line, and

wherein, in a second training operation, the controller transmits second data to the semiconductor memory through the read data gate line and reads the second data from the semiconductor memory through at least two of the data input and output line and the data mask inversion line.

16. The memory system of claim 15, wherein the semiconductor memory outputs a read data strobe signal through the read data strobe line, and outputs the first data and the second data in synchronization with the read data strobe signal through the data input and output lines and the data mask inversion line.

17. The memory system according to claim 16, wherein the controller transmits a clock signal to the semiconductor memory through a clock line, and transmits a write clock signal to the semiconductor memory through a write clock line, and

wherein the semiconductor memory adjusts the write clock signal to output the read data strobe signal.

18. The memory system of claim 15, wherein the controller selects one of the first training operation or the second training operation in response to one of a receive FIFO register write command, a receive FIFO register read command, and programming of a mode register.

19. A semiconductor memory device, comprising:

a memory core configured to perform reading and writing of data;

a first data transfer and training block connected between a first pad and the memory core;

a second data transfer and training block connected between a second pad and the memory core; and

a data transfer, clock generation, and training block connected between the third pad and the memory core,

wherein, in a training input operation, the first and second data transfer and training blocks receive first and second training data through the first and second pads, respectively, and the data transfer, clock generation, and training block receives third training data through the third pad,

wherein, in a training output operation, the first data transfer and training block outputs the first training data through the first pad, and the second data transfer and training block combines the second training data and the third training data to generate fourth training data and outputs the fourth training data through the second pad.

20. The semiconductor memory device of claim 19, wherein in the training output operation, the data transfer, clock generation and training block outputs a read data strobe signal through the third pad, and

wherein the first and second data transfer and training blocks output the first and fourth training data, respectively, in synchronization with the read data strobe signal.

Background

Semiconductor memory devices are used in various electronic devices. Semiconductor memory devices may be used to store data for operation by an electronic device. In addition, the semiconductor memory may be used to load code executable by the electronic device, such as an operating system, firmware, software, and so forth.

As the quality of content used in electronic devices increases, the demand for the performance of semiconductor memories is increasing. For example, there is an increasing demand for improving the speed and reliability of semiconductor memories. In order to meet the demand, various new functions for semiconductor memories have been developed and adopted.

Some new functions may use one or more pads (pads) that the semiconductor memory may use to communicate with the controller. The number of pads for the semiconductor memory may increase if the new pads are used for some functions. If the number of pads is increased, the size of the semiconductor memory may be increased, and thus the manufacturing cost of the semiconductor memory may be increased.

Disclosure of Invention

Embodiments of the inventive concept provide a semiconductor memory having improved reliability without increasing the number of pads, a memory system including the semiconductor memory, and an operating method of the semiconductor memory.

According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes a memory core that performs reading and writing of data; a data transfer and training block connected between the first pad and the memory core; and at least one data transfer, clock generation, and training block connected between the at least one second pad and the memory core. In the first training operation, the data transfer and training block outputs, through the first pad, the first training data received through the first pad as second training data. In the second training operation, at least one of the data transfer and training blocks outputs, through at least one of the first pads, third training data received through at least one second pad as fourth training data. The second training data and the fourth training data are output in synchronization with the read data strobe signal output through the at least one second pad.

According to an exemplary embodiment of the inventive concept, a memory system includes a semiconductor memory; and a controller configured to control the semiconductor memory. The semiconductor memory and the controller communicate with each other through the data input and output lines, the data mask inversion lines, and the read data strobe lines. In the first training operation, the controller transmits first data to the semiconductor memory through the data input and output lines and the data mask inversion line, and reads the first data from the semiconductor memory through the data input and output lines and the data mask inversion line. In the second training operation, the controller transmits second data to the semiconductor memory through the read data gate line and reads the second data from the semiconductor memory through at least two of the data input and output line and the data mask inversion line.

According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes a memory core that performs reading and writing of data; a first data transfer and training block connected between the first pad and the memory core; a second data transfer and training block connected between the second pad and the memory core; and a data transfer, clock generation, and training block connected between the third pad and the memory core. In the training input operation, the first and second data transfer and training blocks receive first and second training data through the first and second pads, respectively, and the data transfer, clock generation, and training block receives third training data through the third pad. In the training output operation, the first data transfer and training block outputs first training data through the first pad, and the second data transfer and training block combines the second training data and the third training data to generate fourth training data and outputs the fourth training data through the second pad.

Drawings

The above and other objects and features of the present inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a block diagram illustrating a memory system according to an embodiment of the inventive concept.

Fig. 2 is a flowchart illustrating an operating method of a semiconductor memory according to an embodiment of the inventive concept.

Fig. 3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the inventive concept.

Fig. 4A illustrates an example of one of the first data transfer and training blocks according to an embodiment of the inventive concept.

FIG. 4B illustrates an application of one of the first data transfer and training blocks shown in FIG. 4A.

Fig. 5A illustrates another example of one of the first data transfer and training blocks according to an embodiment of the inventive concept.

Fig. 5B illustrates an application of the other of the first data transfer and training blocks illustrated in fig. 5A.

Fig. 6A illustrates an example of one of a data transfer, clock generation, and training block according to an embodiment of the inventive concept.

FIG. 6B illustrates the application of one of the data transfer, clock generation, and training blocks.

Fig. 7 is a flowchart illustrating a write training method according to an embodiment of the inventive concept.

Fig. 8 shows an example in which the controller sends a FIFO register write command to the semiconductor memory.

FIG. 9 shows an example of command and address signals for a FIFO register write command.

Fig. 10 shows an example in which the controller transmits the first training data to the semiconductor memory according to the FIFO register write command.

Fig. 11 shows an example in which the controller sends a FIFO register read command to the semiconductor memory.

FIG. 12 shows an example of command and address signals for a FIFO register read command.

Fig. 13 shows an example in which the semiconductor memory transmits the second training data to the controller according to the FIFO register read command.

Fig. 14 shows an example in which the controller transmits the third training data to the semiconductor memory according to the FIFO register write command.

Fig. 15 shows an example in which the semiconductor memory transmits the fourth training data to the controller according to the FIFO register read command.

Fig. 16A illustrates an example of one of the second data transfer and training blocks according to an embodiment of the inventive concept.

Fig. 16B illustrates another example of one of the second data transfer and training blocks according to an embodiment of the inventive concept.

Fig. 17A illustrates an example of another of the second data transfer and training blocks according to an embodiment of the inventive concept.

Fig. 17B illustrates an application of one of the second data transfer and training blocks according to an embodiment of the inventive concept.

Fig. 18A illustrates another example of one of a data transfer, clock generation, and training block according to an embodiment of the inventive concept.

Fig. 18B illustrates an application of one of a data transfer, clock generation, and training block according to an embodiment of the inventive concept.

Fig. 19 is a flowchart illustrating a write training method according to an embodiment of the inventive concept.

FIG. 20 shows an example of command and address signals for a FIFO register write command.

FIG. 21 shows an example of command and address signals for a FIFO register read command.

Fig. 22 is a flowchart illustrating a write training method according to an embodiment of the inventive concept.

Fig. 23 shows an example of transmitting the first training data and the third training data to the semiconductor memory according to the FIFO register write command.

Fig. 24 is a flowchart illustrating a write training method according to an embodiment of the inventive concept.

Fig. 25 is a flowchart illustrating a write training method according to an embodiment of the inventive concept.

Fig. 26A illustrates another example of one of the first data transfer and training blocks according to an embodiment of the inventive concept.

Fig. 26B illustrates an application of the other of the first data transfer and training blocks illustrated in fig. 25.

Fig. 27A illustrates an example of one of the second data transfer and training blocks according to an embodiment of the inventive concept.

Fig. 27B illustrates an example of one of the second data transfer and training blocks according to an embodiment of the inventive concept.

Detailed Description

Embodiments of the inventive concept will be described in detail and clearly below so that those skilled in the art can practice the embodiments of the inventive concept.

Fig. 1 is a block diagram illustrating a memory system 10 according to an embodiment of the inventive concept. Referring to fig. 1, a memory system 10 may include a controller 20 and a semiconductor memory device 100 (also referred to herein as semiconductor memory 100). For example, semiconductor memory 100 may include Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and low power DDR SDRAM (LPDDR SDRAM).

The controller 20 may communicate with the semiconductor memory 100 through the first to sixth controller pads 21 to 26. The semiconductor memory 100 may communicate with the controller 20 through the first to sixth memory pads 101 to 106. As described herein, each of the second through sixth controller pads 22-26 and the second through sixth memory pads 102-106 may include more than one pad, respectively (e.g., the pads of fig. 1 may represent a set of pads). The first controller pad 21 may be connected with the first memory pad 101. The controller 20 may supply the clock signal CK to the semiconductor memory 100 through the first controller pad 21. The clock signal CK may be periodically switched between a low level and a high level. In some embodiments, the pads (e.g., first to sixth controller pads 21 to 26 and/or first to sixth memory pads 101 to 106) may refer to conductive regions of the semiconductor memory 100, which may be used to attach signal transmission elements of the semiconductor memory 100.

The second controller pad 22 may be connected with the second memory pad 102. For example, the second controller pad 22 may include 7 controller pads. The second memory pads 102 may include 7 memory pads connected to 7 controller pads, respectively. The controller 20 may provide command and address signals CA 0:6 to the semiconductor memory 100 through the second controller pad 22.

The third controller pad 23 may be connected with the third memory pad 103. For example, the third controller pad 23 may include 2 controller pads. The third memory pad 103 may include 2 memory pads connected to the 2 controller pads, respectively. The controller 20 may supply the write clock signals WCK [0:1] to the semiconductor memory 100 through the third controller pad 23.

The write clock signals WCK [0:1] may be periodically switched between a high level and a low level. The controller 20 may provide the write clock signals WCK [0:1] to the semiconductor memory 100 when data is read from the semiconductor memory 100 or data is written in the semiconductor memory 100.

The fourth controller pad 24 may be connected with the fourth memory pad 104. For example, the fourth controller pad 24 may include 16 controller pads. The fourth memory pad 104 may include 16 memory pads connected to the 16 controller pads, respectively. The controller 20 and the semiconductor memory 100 may exchange data signals DQ [0:15] with each other through the fourth controller pad 24 and the fourth memory pad 104.

The fifth controller pad 25 may be connected with the fifth memory pad 105. For example, the fifth controller pad 25 may include 2 controller pads. The fifth memory pad 105 may include 2 memory pads connected to the 2 controller pads, respectively. The controller 20 may provide the data mask inversion signal DMI [0:1] to the semiconductor memory 100 through the fifth controller pad 25. The semiconductor memory 100 may provide the read parity signal PARR [0:1] to the controller 20 through the fifth controller pad 25.

The sixth controller pad 26 may be connected with the sixth memory pad 106. For example, the sixth controller pad 26 may include 2 controller pads. The sixth memory pad 106 may include 2 memory pads connected to the 2 controller pads, respectively. The controller 20 may provide the write parity signal PARW [0:1] to the semiconductor memory 100 through the sixth controller pad 26. Semiconductor memory 100 may provide read data strobe signals RDQS [0:1] to controller 20 through sixth controller pad 26.

The semiconductor memory 100 includes a mode register (MRx)110 and a redirector 120. The mode register 110 may store various information used in the operation of the semiconductor memory 100. Mode register 110 may be programmed by controller 20.

In training, redirector 120 may operate under the control of controller 20. For example, in training, redirector 120 may output a signal received through at least one pad through at least one other pad. Examples of the input and output of the redirect signal by redirector 120 are described more fully below.

The controller 20 includes a link Error Correction Code (ECC) controller 27. The link error correction code controller 27 may determine whether an error correction code is applied to communication between the controller 20 and the semiconductor memory 100. In the case where an error correction code is applied, the controller 20 may transmit a write parity signal PARW [0:1] to the semiconductor memory 100 through the sixth controller pad 26 during a write operation.

The link error correction code controller 27 may generate the write parity signals PARW [0:1] by applying one of various error correction codes, such as a Cyclic Redundancy Code (CRC), Hamming code, and Bose-Chaudhuri-Hockvernahme (BCH) code, to the data signals DQ [0:15 ].

The write parity signals PARW [0:1] may be generated from the data signals DQ [0:15 ]. For example, each write parity signal PARW [0:1] may correspond to 8 data signals. The semiconductor memory 100 may correct errors of the data signals DQ [0:15] based on the write parity signals PARW [0:1] and the data signals DQ [0:15 ].

In the case where an error correction code is applied, the semiconductor memory 100 may transmit a read parity signal PARR [0:1] to the controller 20 through the fifth controller pad 25 during a read operation. The read parity signals PARR [0:1] may be generated by applying an error correction code to the data signals DQ [0:15 ]. The controller 20 may correct errors of the data signals DQ [0:15] based on the read parity signals PARR [0:1] and the data signals DQ [0:15 ].

In the case where no error correction code is applied, the controller 20 does not send the write parity signal PARW [0:1] during the write operation. In addition, the semiconductor memory 100 does not transmit the read parity signal PARR [0:1] during the read operation. For example, the LINK error correction code controller 27 may adjust whether the error correction code is applied by adjusting the LINK error correction code configuration (LINK _ ECC)111 of the mode register 110 in the semiconductor memory 100.

In some embodiments, the read parity signals PARR [0:1] and the write parity signals PARW [0:1] may be used to correct errors that occur during communication between the controller 20 and the semiconductor memory 100. The read parity signals PARR [0:1] and the write parity signals PARW [0:1] may be distinguished from the storage parity because they are not stored in the memory array 130 (refer to FIG. 3) of the semiconductor memory 100.

The write parity signals PARW [0:1] may be used to correct errors occurring when the controller 20 transmits the data signals DQ [0:15] to the semiconductor memory 100. The read parity signals PARR [0:1] may be used to correct errors occurring when the semiconductor memory 100 transmits the data signals DQ [0:15] to the controller 20.

In contrast, the memory parity may be used to correct errors that occur when the data signals DQ [0:15] are stored in the semiconductor memory 100. The memory parity included as part of the data signals DQ [0:15] may be written in the memory array 130 of the semiconductor memory 100 and may be read from the memory array 130 of the semiconductor memory 100.

The training controller 28 may control training between the controller 20 and the semiconductor memory 100. For example, the training may include write training to adjust the timing between write clock signals WCK [0:1] and data signals DQ [0:15] during a write operation; and read training for adjusting the timing between the read data strobe signals RDQS [0:1] and the data signals DQ [0:15] during a read operation.

The write training may be performed by transmitting a preset pattern signal to the semiconductor memory 100 and receiving the transmitted signal again from the semiconductor memory 100. For example, write training may be performed with respect to signals exchanged between the controller 20 and the semiconductor memory 100 in synchronization with the write clock signals WCK [0:1] or the read data strobe signals RDQS [0:1 ].

For example, the controller 20 may transmit the mode signal to the semiconductor memory 100 through the fourth and fifth controller pads 24 and 25 connected to the fourth and fifth memory pads 104 and 105 in synchronization with the write clock signals WCK [0:1 ]. For example, the mode signals may be transmitted as data signals DQ [0:15] and data mask inversion signals DMI [0:1 ].

The controller 20 may receive the mode signal from the semiconductor memory 100 in synchronization with the read data strobe signals RDQS [0:1] through the fourth and fifth controller pads 24 and 25 connected to the fourth and fifth memory pads 104 and 105. For example, mode signals may be received from the semiconductor memory 100 as data signals DQ [0:15] and read parity signals PARR [0:1 ].

Write training may be performed on signals exchanged through the fourth controller pad 24 and the fifth controller pad 25 by writing and reading mode signals through the fourth controller pad 24 and the fifth controller pad 25. For example, write training may be performed on the transmission timing of the data signals DQ [0:15], the data mask invert signals DMI [0:1], and/or the read parity signals PARR [0:1 ].

In the case where the link error correction code controller 27 activates application of an error correction code, the controller 20 may also transmit a write parity signal PARW [0:1] to the semiconductor memory 100 in synchronization with the write clock signal WCK [0:1 ]. Therefore, in the case where the application of the error correction code is activated, it is necessary to perform write training on the sixth controller pad 26 connected to the sixth memory pad 106, and the controller 20 and the semiconductor memory 100 exchange the write parity signal PARW [0:1] through the sixth controller pad 26 connected to the sixth memory pad 106.

For write training associated with write parity signals PARW [0:1], controller 20 may send a mode signal to semiconductor memory 100 through sixth controller pad 26, which is connected to sixth memory pad 106. For example, the mode signal may be transmitted to the semiconductor memory 100 as a write parity signal PARW [0:1 ].

However, even though controller 20 intends to read the mode signal from semiconductor memory 100 through sixth controller pad 26 connected to sixth memory pad 106, semiconductor memory 100 may be designated to transmit read data strobe signals RDQS [0:1] through sixth memory pad 106 connected to sixth controller pad 26. Therefore, the controller 20 cannot receive the mode signal from the semiconductor memory 100 through the sixth controller pad 26 connected to the sixth memory pad 106.

The semiconductor memory 100 includes a redirector 120 for the purpose of performing write training on the sixth controller pads 26 connected to the sixth memory pads 106. Training controller 28 may control redirector 120 to receive a mode signal via a different memory pad or controller pad (the mode signal being sent to semiconductor memory 100 via sixth controller pad 26 connected to sixth memory pad 106). Thus, write training may be performed on the write parity signals PARW [0:1] in addition to the data signals DQ [0:15] and the data mask invert signals DMI [0:1 ].

The pad type and the number of pads are specifically depicted in fig. 1. However, the pad type and the number of pads described in fig. 1 are examples and do not limit the technical idea of the inventive concept. Pads not shown in fig. 1 may be included in the memory system 10, and a portion of the pads shown in fig. 1 may be removed from the memory system 10. In addition, the number of pads shown in fig. 1 may be variously changed.

Fig. 2 is a flowchart illustrating an operation method of the semiconductor memory 100 according to an embodiment of the inventive concept. For example, an example of an operation method of the semiconductor memory 100 in write training is shown in fig. 2. Referring to fig. 1 and 2, the semiconductor memory 100 may receive first training data from the controller 20 through the first pad in operation S110. For example, the first pads may include the fourth memory pad 104 and the fifth memory pad 105.

For example, the first training data may be received as data signals DQ [0:15] and data mask inversion signals DMI [0:1 ]. The first training data may include a pattern signal having a write training pattern. The controller 20 may output the preset mode signal as the first training data to the semiconductor memory 100.

The first training data may be received in synchronization with write clock signals WCK [0:1 ]. If the difference between the switching timing of the write clock signal WCK [0:1] and the transmission timing of the training data received through one of the first pads is within a threshold (e.g., falls within a normal reception range), the training data transmitted through the corresponding pad can be normally received in the semiconductor memory 100.

If the difference between the switching timing of the write clock signal WCK [0:1] and the transmission timing of the training data received through the other pad in the first pads exceeds a threshold value (e.g., does not fall within a normal reception range), the training data transmitted through the corresponding pad cannot be normally received in the semiconductor memory 100. For example, training data may be received as an error value.

In operation S120, the semiconductor memory 100 may output the received first training data to the controller 20 through the first pad as second training data. The second training data may include the same or different values as the first training data depending on the transmission timing of the first training data and the switching timing of the write clock signals WCK [0:1] transmitted by the controller 20.

The first pads may include fourth memory pads 104 and fifth memory pads 105. The second training data may be output in synchronization with the read data strobe signals RDQS [0:1 ]. For example, assume that read training is completed before write training. That is, it is assumed that the difference between the switching timing of the read data strobe signals RDQS [0:1] output from the semiconductor memory 100 and the transmission timing of the first training data is within the threshold.

The controller 20 may compare the second training data received from the semiconductor memory 100 with the first training data transmitted from the controller 20. If the second training data and the first training data are matched, it may be determined that the difference between the switching timing of the write clock signals WCK [0:1] and the transmission timing of the first training data is within a threshold. If the second training data and the first training data are not matched, it may be determined that a difference between a switching timing of the write clock signal WCK [0:1] and a transmission timing of at least a portion of the first training data exceeds a threshold.

The controller 20 may detect a difference between the switching timing of the write clock signals WCK [0:1] and the transmission timing of the first training data while scanning the switching timing of the write clock signals WCK [0:1] and the transmission timing of the first training data. The controller 20 may adjust the transmission timing through the first pad, for example, the transmission timing of the data signals DQ [0:15] and the data mask inversion signal DMI [0:1], depending on the detected difference.

In operation S130, the semiconductor memory 100 may receive third training data from the controller 20 through the at least one second pad. For example, the at least one second pad may include a sixth memory pad 106. The third training data may be received as a write parity signal PARW [0:1 ]. The third training data may be received in synchronization with write clock signals WCK [0:1 ].

If the difference between the switching timing of the write clock signals WCK [0:1] and the transmission timing of the training data received through the at least one second pad is within a threshold value (e.g., falls within a normal reception range), the training data transmitted through the corresponding pad can be normally received in the semiconductor memory 100.

If the difference between the switching timing of the write clock signals WCK [0:1] and the transmission timing of the training data received through the at least one second pad exceeds a threshold value (e.g., does not fall within a normal reception range), the training data transmitted through the corresponding pad cannot be normally received in the semiconductor memory 100. For example, training data may be received as an error value.

In operation S140, the semiconductor memory 100 may output the received third training data to the controller 20 through the at least one first pad as fourth training data. The at least one first pad may be at least one of the first pads described above. For example, the at least one first pad may include at least one of the fourth memory pad 104 and the fifth memory pad 105.

The fourth training data may be output in synchronization with the read data strobe signals RDQS [0:1] transmitted through the at least one second pad. The controller 20 may compare the fourth training data received from the semiconductor memory 100 with the third training data transmitted from the controller 20.

The controller 20 may detect a difference between the switching timing of the writing clock signal WCK [0:1] and the transmission timing of the third training data while sweeping the switching timing of the writing clock signal WCK [0:1] and the transmission timing of the third training data. The controller 20 may adjust a transmission timing through the at least one second pad, for example, a transmission timing of the write parity signal PARW [0:1], depending on the detected difference.

As described above, the fourth memory pad 104 and the fifth memory pad 105 may be used for data communication (or communication of additional information/data associated with data communication) between the semiconductor memory 100 and the controller 20, and are free from input (or reception) and output of data. Accordingly, the training of the fourth memory pad 104 and/or the fifth memory pad 105 may be performed by the reception (or input) and the transmission (or output) of the training data (operation S110 and 120).

The sixth memory pad 106 may be used for data communication (or communication of additional information/data associated with data communication) between the semiconductor memory 100 and the controller 20, and freely input (or receive) and output data, but is not used for transmitting (or outputting) data in training of the sixth memory pad 106. Accordingly, the training of the sixth memory pad 106 may be performed by the reception (or input) of the training data (operation S130) and the transmission (or output) of the training data via another pad (e.g., at least one first pad) (operation S140).

By outputting the received (or input) data to another pad via redirection, write training associated with the sixth memory pad 106 that is not used to output data may be performed. Accordingly, the reliability of the semiconductor memory 100 and the memory system 10 including the semiconductor memory 100 can be improved.

Furthermore, since the read data strobe signals RDQS [0:1] and the write parity signals PARW [0:1] commonly use the sixth memory pads 106, the number of pads of the semiconductor memory 100 can be prevented from increasing, and an increase in the manufacturing cost of the semiconductor memory 100 can be reduced and/or suppressed.

Fig. 3 is a block diagram illustrating a semiconductor memory 100 according to an embodiment of the inventive concept. Referring to fig. 1 and 3, the semiconductor memory 100 includes: redirector 120, memory array 130, input and output drivers and sense amplifiers 140, bus controller and error correction engine 150, first block 160, second block 170, third block 180a, fourth block 180b, and control logic 190.

The memory array 130 includes memory cells. The memory cells may be arranged in a matrix form or may be stacked in a three-dimensional structure. The memory array 130 is connected to input and output drivers and sense amplifiers 140 by input and output lines IO. The input and output drivers and sense amplifiers 140 may perform read operations and write operations on the memory cells of the memory array 130.

The bus controller and error correction engine 150 may be connected with the first block 160, the second block 170, and the third block 180 a. The bus controller and error correction engine 150 may receive input data DIN from the first block 160 and may transmit the received input data DIN to the input and output drivers and sense amplifiers 140.

The bus controller and error correction engine 150 may receive the output data DOUT from the input and output drivers and sense amplifiers 140 and may transmit the received output data DOUT to the first block 160. The bus controller and error correction engine 150 may receive the data mask inversion signal DMI from the second block 170.

The data mask inversion signal DMI may indicate whether inversion of data or write mask of data is to be used. The data mask inversion signal DMI may be set by programming the mode register 110. When the data mask inversion signal DMI indicates the data mask, the bus controller and error correction engine 150 does not transmit the input data DIN to the input and output driver and sense amplifier 140.

When the data mask inversion signal DMI indicates inversion, the bus controller and error correction engine 150 may invert the input data DIN, or may transmit the data mask inversion signal DMI to the input and output driver and sense amplifier 140 together with the input data DIN.

In a read operation, bus controller and error correction engine 150 may generate a read parity PARR based on output data DOUT. The bus controller and error correction engine 150 may send the read parity PARR to the second block 170.

In a write operation, bus controller and error correction engine 150 may receive a write parity PARW from third block 180 a. Bus controller and error correction engine 150 may perform error correction based on write parity PARW and input data DIN. Memory array 130, input and output drivers and sense amplifiers 140, and bus controller and error correction engine 150 may constitute a memory core MC of semiconductor memory 100.

Control logic 190 may receive clock signal CK through first memory pad 101. Control logic 190 may receive command and address signals CA [0:6] through second memory pads 102. For example, control logic 190 may receive command and address signals CA [0:6] in synchronization with clock signal CK.

Control logic 190 may control the operation of memory core MC, redirector 120, first and second blocks 160, 170, and third and fourth blocks 180a, 180b in response to command and address signals CA [0:6 ].

In some embodiments, mode register 110 is shown as being included in control logic 190. However, the mode register 110 is not limited to being included in the control logic 190. Mode register 110 may be located external to control logic 190 or may be included within any other component than control logic 190.

First block 160 may include first data transfer and training blocks 160_1 through 160_15 that operate in synchronization with write clock signals WCK [0:1 ]. The first data transfer and training blocks 160_1 to 160_15 may be connected to the fourth memory pads 104_0 to 104_15, respectively. The first data transfer and training blocks 160_1 through 160_15 may exchange data signals DQ [0:15] with the fourth memory pads 104_0 through 104_15, respectively.

In a write operation, the first block 160 may transmit data signals DQ0 through DQ15 as input data DIN to the memory core MC. In a read operation, the first block 160 may output the output data DOUT transmitted from the memory core MC as data signals DQ0 to DQ 15.

In a write operation of write training, the first data transfer and training blocks 160_1 to 160_15 may receive and store training data from the fourth memory pads 104_0 to 104_15, respectively. In a write-trained read operation, the first data transfer and training blocks 160_1 to 160_15 may output the stored training data to the fourth memory pads 104_0 to 104_15, respectively.

The second block 170 may include second data transfer and training blocks 170_0 and 170_1 that operate in synchronization with the write clock signals WCK [0:1 ]. The second data transfer and training blocks 170_0 and 170_1 may be connected to the fifth memory pads 105_0 and 105_1, respectively.

The second data transfer and training blocks 170_0 and 170_1 may transmit the read parity signals PARR0 and PARR1 to the fifth memory pads 105_0 and 105_1, and may receive the data mask inversion signals DMI0 and DMI1 from the fifth memory pads 105_0 and 105_ 1.

In the write operation, the second block 170 may transmit the data mask inversion signals DMI0 and DMI1 to the memory core MC as the data mask inversion signal information DMI. In a read operation, the second block 170 may output the read parity PARR transmitted from the memory core MC as read parity signals PARR0 and PARR 1.

In a write operation of write training, the second data transfer and training blocks 170_0 and 170_1 may receive and store training data from the fifth memory pads 105_0 and 105_1, respectively. In a write-trained read operation, the second data transfer and training blocks 170_0 and 170_1 may output the stored training data to the fifth memory pads 105_0 and 105_1, respectively.

The third block 180a may include data transfer, clock generation, and training blocks 180_0 and 180_1 that operate in synchronization with the write clock signals WCK [0:1 ]. The fourth block 180b may include clock generation blocks 180_2 and 180_3 operating in synchronization with the write clock signals WCK [0:1 ].

The blocks 180_0 to 180_3 may be connected to the sixth memory pads 106_0 to 106_3, respectively. The data transfer, clock generation, and training blocks 180_0 and 180_1 may receive write parity signals PARW0 and PARW1 from the sixth memory pads 106_0 and 106_1 and may transmit read data strobe signals RDQS0 and RDQS1 to the sixth memory pads 106_0 and 106_ 1.

Clock generation blocks 180_2 and 180_3 may transmit read data strobe signals RDQS2 and RDQS3 to sixth memory pads 106_2 and 106_ 3. Compared to FIG. 1, sixth memory pads 106_2 and 106_3 may also be included, which do not transmit write parity signals PARW0 and PARW1 and transmit only read data strobe signals RDQS2 and RDQS 3.

In a write operation, third block 180a may send write parity signals PARW0 and PARW1 to memory core MC as write parity PARWs. In a read operation, the third block 180a may generate and output read data strobe signals RDQS0 and RDQS1 according to a write clock signal WCK [0:1 ]. In a read operation, the fourth block 180b may generate and output read data strobe signals RDQS2 and RDQS3 according to the write clock signals WCK [0:1 ].

Redirector 120 may support data transfer, clock generation, and training blocks 180_0 and 180_1 of third block 180 a. For example, in a write operation of write training, redirector 120 may allow training data received from sixth memory pads 106_0 and 106_1 to be redirected to and stored in first block 160 or second block 170.

As another example, in a write-trained read operation, redirector 120 may allow training data stored in third block 180a to be output through at least one of fourth memory pads 104_0 through 104_15 or fifth memory pads 105_0 and 105_ 1. That is, the redirector 120 may allow training data received through the sixth memory pads 106_0 and 106_1 to be output to other memory pads, for example, the fourth memory pads 104_0 to 104_15 or the fifth memory pads 105_0 and 105_ 1.

In fig. 3, the redirector 120 is shown as a block that exists outside the first block 160, the second block 170, and the third block 180a for ease of description. However, redirectors 120 may be distributed and located within first block 160, second block 170, and/or third block 180 a. That is, redirector 120 may be included in at least one of first block 160, second block 170, and/or third block 180 a.

Fig. 4A illustrates an example of one of the first data transfer and training blocks 160_0 to 160_15 according to an embodiment of the inventive concept. In some embodiments, an example of a first data transfer and training block 160_ i not associated with redirector 120 is shown in fig. 4A. Referring to fig. 3 and 4A, the first data transfer and training block 160_ i includes a data buffer 161_ i, a first-in first-out (FIFO) register 162_ i, a deserializer 163_ i, and a serializer 164_ i.

The data buffer 161_ i may temporarily store data (e.g., data signals DQi or training data) transmitted from the FIFO register 162_ i, and may transmit the stored data to the fourth memory pad 104_ i. The data buffer 161_ i may temporarily store data (e.g., data signals DQi or training data) received from the fourth memory pad 104_ i, and may transmit the stored data to the FIFO register 162_ i. The data buffers 161_ i may operate in synchronization with one WCK of the write clock signals WCK [0:1 ].

The FIFO register 162_ i can compensate for the speed difference between the relatively high-speed data buffer 161_ i and the relatively low-speed memory core MC. In a data input or write operation, the FIFO register 162_ i may store data transmitted from the data buffer 161_ i in response to a write command WR transmitted from the control logic 190, and may output the stored data to the parallelizer 163_ i in a FIFO manner.

Also, in a data output or read operation, the FIFO register 162_ i may store data transmitted from the serializer 164_ i in response to the read command RD transmitted from the control logic 190, and may output the stored data to the data buffer 161_ i in a FIFO manner.

The FIFO register 162_ i may support write training. In response to a FIFO register write command WR _ FIFO received from the control logic 190, the FIFO register 162_ i may store data (e.g., training data) received from the data buffer 161_ i. The FIFO register 162_ i may not send the storage data to the parallelizer 163_ i.

In response to a FIFO register read command RD _ FIFO received from the control logic 190, the FIFO register 162_ i may output storage data (e.g., training data) to the data buffer 161_ i. That is, in the write training, the training data may be transmitted to the FIFO register 162_ i and may not be transmitted to the memory core MC.

In response to the write command WR, the deserializer 163_ i may parallelize the data sequentially sent from the FIFO register 162_ i and may output the parallelized data to the memory core MC as part of the input data DIN. In response to the read command RD, the serializer 164_ i may serialize a portion of the output data DOUT received from the memory core MC and may transmit the serialized data to the FIFO register 162_ i.

In some embodiments, the first data transfer and training block of first data transfer and training blocks 160_0 through 160_15 that is not associated with redirector 120 may have the same structure as shown in fig. 4A and may operate in the same manner as described with reference to fig. 4A. Likewise, the second data transfer and training block of second data transfer and training blocks 170_0 and 170_1 that is not associated with redirector 120 may have the same structure as shown in FIG. 4A and may operate in the same manner as described with reference to FIG. 4A, except for the signals and component reference numbers exchanged with memory core MC.

Fig. 4B illustrates an application of one of the first data transfer and training blocks 160_0 to 160_15 illustrated in fig. 4A. In some embodiments, an example of a first data transfer and training block 160_ i' not associated with redirector 120 is shown in fig. 4B. Referring to fig. 3 and 4B, the first data transfer and training block 160_ i' includes a data buffer 161_ i, a FIFO register 162_ i, a deserializer 163_ i, a serializer 164_ i, and an encoder 165_ i.

In response to a write command WR or a read command RD from the control logic 190, the encoder 165_ i may connect the deserializer 163_ i and the serializer 164_ i with the data buffer 161_ i. The encoder 165_ i may connect the FIFO register 162_ i with the data buffer 161_ i in response to a FIFO register write command WR _ FIFO or a FIFO register read command RD _ FIFO.

The parallelizer 163_ i may parallelize the data signals DQi into the input data DIN according to the write command WR. The serializer 164_ i may serialize the output data DOUT into the data signal DQi according to the read command RD. The FIFO register 162_ i may store the training data in response to a FIFO register write command WR _ FIFO and may output the stored data as the training data in response to a FIFO register read command RD _ FIFO.

That is, in the write or read operation, the data signal DQi may be transmitted to the serializer 164_ i or the deserializer 163_ i without passing through the FIFO register 162_ i. The FIFO register 162_ i may be a separate register provided for training. In some embodiments, and within the detailed description, first data transfer and training block 160_ i of fig. 4A and first data transfer and training block 160_ i' of fig. 4B may be used interchangeably.

Fig. 5A illustrates another example of one of the first data transfer and training blocks 160_0 to 160_15 according to an embodiment of the inventive concept. In some embodiments, an example of a first data transfer and training block 160_ j associated with redirector 120 is shown in fig. 5A. Referring to fig. 3 and 5A, the first data transfer and training block 160_ j includes a data buffer 161_ j, a first-in-first-out (FIFO) register 162_ j, a deserializer 163_ j, and a serializer 164_ j.

In normal operation (e.g., not training), data buffer 161_ j may communicate data signal DQj with fourth memory pad 104_ j. In training, the data buffer 161_ j may communicate training data with the fourth memory pad 104_ j.

The data buffer 161_ j, the FIFO register 162_ j, the deserializer 163_ j, and the serializer 164_ j may operate in the same manner as described with reference to fig. 4A, and thus, a description thereof will not be repeated here.

The first encoder 121 of the redirector 120 may be located on a path through which the data buffer 161_ j sends data to the FIFO register 162_ j. The first encoder 121 may operate in response to a FIFO register write command WR _ FIFO. When the FIFO register write command WR _ FIFO has the first option, the first encoder 121 may send the output of the data buffer 161_ j to the FIFO register 162_ j.

In training, when the FIFO register write command WR _ FIFO has the second option, the first encoder 121 may store the training data transmitted from the data transfer, clock generation, and training block 180_ k (refer to fig. 6A), and may output the stored training data to the fourth memory pad 104_ j. Thus, write training associated with the fourth memory pad 104_ j may be performed.

In training, when the FIFO register write command WR _ FIFO has the second option, the FIFO register 162_ i may store the training data transferred from the data transfer, clock generation, and training block 180_ k, and may output the stored training data through the fourth memory pad 104_ j. Write training may be performed on the sixth memory pad 106_0 or 106_1 by redirecting the output of the training data.

In some embodiments, the second one of second data transfer and training blocks 170_0 and 170_1 associated with redirector 120 may have the same structure as shown in fig. 5A and may operate in the same manner as described with reference to fig. 5A, except for the signals and reference numbers of components exchanged with memory core MC. That is, the training data may be redirected to the first block 160 or the second block 170.

Fig. 5B illustrates an application of another one of the first data transfer and training blocks 160_0 to 160_15 illustrated in fig. 5A. In some embodiments, an example of a first data transfer and training block 160_ j' associated with redirector 120 is shown in fig. 5B. Referring to fig. 3 and 5B, the first data transfer and training block 160_ j' includes a data buffer 161_ j, a FIFO register 162_ j, a deserializer 163_ j, a serializer 164_ j, and an encoder 165_ j.

In response to a write command WR or a read command RD from the control logic 190, the encoder 165_ j may connect the deserializer 163_ j and the serializer 164_ j with the data buffer 161_ j. In response to the FIFO register write command WR _ FIFO or the FIFO register read command RD _ FIFO, the encoder 165_ j may connect the output of the FIFO register 162_ j with the data buffer 161_ j, and may connect the output of the data buffer 161_ j with the first encoder 121.

The parallelizer 163_ j may parallelize the data signals DQj into the input data DIN according to the write command WR. The serializer 164_ j may serialize the output data DOUT into the data signal DQj according to the read command RD.

When the FIFO register write command WR _ FIFO has the first option, the first encoder 121 may transmit the training data transmitted through the encoder 165_ j from the data buffer 161_ j to the FIFO register 162_ j. When the FIFO register write command WR _ FIFO has the second option, the first encoder 121 may transmit the training data transmitted from the data transfer, clock generation, and training block 180_ k' (refer to fig. 6B) to the FIFO register 162_ j.

The FIFO register 162_ j may store the training data transmitted from the first encoder 121 in response to a FIFO register write command WR _ FIFO, and may output the stored data as the training data to the encoder 165_ j in response to a FIFO register read command RD _ FIFO.

In some embodiments, and within the detailed description, first data transfer and training block 160_ j of fig. 5A and first data transfer and training block 160_ j' of fig. 5B may be used interchangeably.

Fig. 6A illustrates an example of one of the data transfer, clock generation, and training blocks 180_0 and 180_1 according to an embodiment of the inventive concept. Referring to fig. 3 and 6A, the data transfer, clock generation and training block 180_ k includes a data buffer 181_ k, a FIFO register 182_ k, a deserializer 183_ k, a read data strobe signal generator 184_ k and a read data strobe signal driver 185_ k.

The second encoder 122 of the redirector 120 may be located between the data buffer 181_ k and the FIFO register 182_ k. The data buffer 181_ k may temporarily store data (e.g., a write parity signal PARWk or training data) received from the sixth memory pad 106_ k, and may transmit the stored data to the second encoder 122. The data buffer 181_ k may operate in synchronization with one WCK of the write clock signals WCK [0:1 ].

The second encoder 122 may operate in response to a FIFO register write command WR _ FIFO. When the FIFO register write command WR _ FIFO has the first option or when the FIFO register write command WR _ FIFO does not exist, the second encoder 122 may transmit the data output from the data buffer 181_ k to the FIFO register 182_ k.

When the FIFO register write command WR _ FIFO has the second option, the second encoder 122 may transmit the data output from the data buffer 181_ k to the first data transfer and training block 160_ j (refer to fig. 5A). As another example, the second encoder 122 may send data output from the data buffer 181_ k to the second data transfer and training block 170_0 or 170_1 associated with the redirector 120.

The FIFO register 182_ k may compensate for a speed difference between the relatively high speed data buffer 181_ k and the relatively low speed memory core MC. In a data input or write operation, the FIFO register 182_ k may store data (e.g., a write parity signal park) transmitted from the data buffer 181_ k in response to a write command WR transmitted from the control logic 190, and may output the stored data to the deserializer 183_ k in a FIFO manner.

In response to a FIFO register write command WR _ FIFO received from the control logic 190, the FIFO register 182_ k may store data (e.g., training data) received from the data buffer 181_ k. The FIFO register 182_ k may not send the stored data to the parallelizer 183_ k. In response to the write command WR, the deserializer 183_ k may parallelize the data sequentially sent from the FIFO register 182_ k and may output the parallelized data to the memory core MC as part of the write parity PARW.

The read data strobe signal generator 184_ k may generate the read data strobe signal RDQSk in response to one of the write clock signals WCK [0:1 ]. In response to the read command RD or the FIFO register read command RD _ FIFO from the control logic 190, the read data strobe signal RDQSk is output to the sixth memory pad 106_ k through the read data strobe signal driver 185_ k.

In some embodiments, the data transfer, clock generation, and training blocks 180_0 and 180_1 may have the structure described with reference to fig. 6A and may operate in the manner described with reference to fig. 6A. Only the clock generation blocks 180_2 and 180_3 associated with the read data strobe signals RDQS2 and RDQS3 may include the read data strobe signal generator 184_ k and read data strobe signal driver 185_ k of the components shown in FIG. 6A.

FIG. 6B illustrates the application of one of the data transfer, clock generation and training blocks 180_0 and 180_ 1. Referring to FIGS. 3 and 6B, the data transfer, clock generation and training block 180_ k' includes a data buffer 181_ k, a FIFO register 182_ k, a deserializer 183_ k, a read data strobe signal generator 184_ k, a read data strobe signal driver 185_ k and an encoder 186_ k.

In response to a write command WR or a read command RD from the control logic 190, the encoder 186_ k may connect the data buffer 181_ k with the parallelizer 183_ k. In response to the FIFO register write command WR _ FIFO, the encoder 186_ k may send the output of the data buffer 181_ k to the second encoder 122. The parallelizer 183_ k may parallelize the write parity signal PARWk into the write parity PARW according to the write command WR.

When the FIFO register write command WR _ FIFO has the first option, the first encoder 122 may transmit the training data transmitted through the encoder 186_ k from the data buffer 181_ k to the FIFO register 182_ k. When the FIFO register write command WR _ FIFO has the second option, the second encoder 122 may send the training data sent by the encoder 186_ k from the data buffer 181_ k to the data transfer and training block 160_ j' (refer to fig. 5B) associated with the redirector 120 in the first block 160 or the data transfer and training block in the second block 170.

In some embodiments, and within the detailed description, the data transfer, clock generation, and training block 180_ k of fig. 6A and the data transfer, clock generation, and training block 180_ k' of fig. 6B may be used interchangeably.

As described with reference to fig. 4A through 6B, the third block 180a may transmit the training data received through the sixth memory pads 106_0 and 106_1 to the first block 160 or the second block 170 in response to the FIFO register write command WR _ FIFO. The FIFO register of the first block 160 or the second block 170 may store training data.

The FIFO register of the first block 160 or the second block 170 may output the stored training data in response to a FIFO register read command RD _ FIFO. That is, the training data received through the sixth memory pads 106_0 and 106_1 in the third block 180a may be output to the outside after being redirected to the first block 160 or the second block 170. Therefore, the write training may be performed on the sixth memory pads 106_0 and 106_ 1.

Fig. 7 is a flowchart illustrating a write training method according to a first example of the inventive concept. Referring to fig. 1, 3 and 4A to 7, in operation S210, the controller 20 may transmit a FIFO register write command WR _ FIFO having a first option to the semiconductor memory 100. The FIFO register write command WR _ FIFO may be sent multiple times.

The controller 20 may transmit the first training data to the semiconductor memory 100 together with the FIFO register write command WR _ FIFO. For example, the first training data may be transmitted through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_ 1. The semiconductor memory 100 may store the first training data in the FIFO register (e.g., 162_ i and/or 162_ j) in response to the FIFO register write command WR _ FIFO.

In operation S220, the controller 20 may transmit a FIFO register read command RD _ FIFO to the semiconductor memory 100. In response to the FIFO register read command RD _ FIFO, the semiconductor memory 100 may output data stored in the FIFO register (e.g., 162_ i and/or 162_ j) to the controller 20 as second training data. The second training data may be transmitted through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_ 1. The FIFO register read command RD _ FIFO may be sent multiple times.

Operations S210 and S220 may constitute a first training operation targeting the unimpeded pad to output training data. Thereafter, in operations S230 and S240, a second training operation may be performed on the unimpeded pad to output training data. The second training operation may be a redirection training in which the input pads and output pads of the training data are redirected.

In operation S230, the controller 20 may transmit a FIFO register write command WR _ FIFO having the second option to the semiconductor memory 100. The controller 20 may transmit the third training data to the semiconductor memory 100 together with the FIFO register write command WR _ FIFO. For example, the third training data may be transmitted to the semiconductor memory 100 through the sixth memory pads 106_0 and 106_ 1. The FIFO register write command WR _ FIFO may be sent multiple times.

In response to the FIFO register write command WR _ FIFO having the second option, the semiconductor memory 100 may store the third training data in the FIFO register 162_ j of at least one of the first data transfer and training block 160_0 to 160_15 in the first block 160 or the second data transfer and training block 170_0 and 170_1 in the second block 170.

In operation S240, the controller 20 may transmit a FIFO register read command RD _ FIFO to the semiconductor memory 100. In response to the FIFO register read command RD _ FIFO, at least one of the first data transfer and training blocks 160_0 to 160_15 or at least one of the second data transfer and training blocks 170_0 and 170_1 in the second block 170 may output the data stored in the FIFO register 162_ j to the controller 20 as fourth training data. The fourth training data may be transmitted through at least one of the fourth memory pads 104_0 to 104_15 or at least one of the fifth memory pads 105_0 and 105_ 1. The FIFO register read command RD _ FIFO may be sent multiple times.

Fig. 8 shows an example in which the controller 20 transmits a FIFO register write command WR _ FIFO to the semiconductor memory 100. In fig. 8, "CK _ t" indicates the clock signal CK, and "CK _ c" indicates an inverted version of the clock signal CK. "CS" refers to a chip select signal for selecting the semiconductor memory 100. "CMD" is conceptually represented as command and address signals CA [0:6] and does not refer to the signals actually communicated by controller 20 and semiconductor memory 100.

Referring to fig. 1, 3, and 8, when the chip select signal CS transitions to a high level, the controller 20 may transmit a FIFO register write command WR _ FIFO to the semiconductor memory 100. The FIFO register write command WR _ FIFO is sent over the command and address signals CA [0:6 ]. The FIFO register write command WR _ FIFO may be transmitted during one period of the clock signal CK _ t or CK _ c. The FIFO register write command WR _ FIFO will be described more fully with reference to fig. 9.

For write training, the controller 20 may send the FIFO register write command WR _ FIFO multiple times. An example is shown in fig. 8, where the controller 20 sends a FIFO register write command WR _ FIFO two or more times. However, the controller 20 may transmit the FIFO register write command WR _ FIFO once to perform the first training operation or the second training operation.

Fig. 9 shows examples of command and address signals CA0 to CA6 of the FIFO register write command WR _ FIFO. Referring to fig. 8 and 9, the option of the FIFO register write command WR _ FIFO may be determined according to whether the command and address signals CA0 through CA6 have any value after the chip select signal CS has a high level "H" at the falling edge "F" of the clock signal CK _ t.

For example, at the rising edge "R" of the clock signal CK _ t, when the chip select signal CS has the high level "H", the command and address signals CA0 to CA6 of the FIFO register write command WR _ FIFO may sequentially have the low level "L", the high level "H", and the high level "H".

At the falling edge "F" of the clock signal CK _ t, the command and address signal CA0 of the FIFO register write command WR _ FIFO having the first option has the low level "L" regardless of the level of the chip select signal CS ("X"). The remaining command and address signals CA1 through CA6 may have an active level "V" corresponding to any one of a high level and a low level.

At the falling edge "F" of the clock signal CK _ t, the command and address signal CA0 of the FIFO register write command WR _ FIFO having the second option has a high level "H" regardless of the level of the chip select signal CS ("X"). The remaining command and address signals CA1 through CA6 may have an active level "V" corresponding to any one of a high level and a low level.

As described with reference to fig. 9, the option of the FIFO register write command WR _ FIFO is selected according to whether the command and address signal CA0 has a high level "H" or a low level "L" at the falling edge "F" of the clock signal CK _ t. Since no additional period of the clock signal CK _ t or additional pad is required, overhead caused by the option of the FIFO register write command WR _ FIFO is suppressed.

Fig. 10 shows an example in which the controller 20 transmits the first training data to the semiconductor memory 100 according to the FIFO register write command WR _ FIFO. In some embodiments, an example of sending the first training data according to the FIFO register write command WR _ FIFO with the first option is shown in fig. 10. In FIG. 10, "WCK _ t" indicates one of the write clock signals WCK [0:1], and "WCK _ c" indicates an inverted version of the write clock signal WCK _ t.

Referring to fig. 1, 3, 8, and 10, when a certain time elapses after the FIFO register write command WR _ FIFO is transmitted, the controller 20 may transmit a plurality of pieces of first training data to the semiconductor memory 100. The first training data may be transmitted to the semiconductor memory 100 in synchronization with the write clock signal WCK _ t or WCK _ c.

The controller 20 may transmit a portion of the first training data as the data signals DQ [0:15] to the semiconductor memory 100 through the fourth memory pads 104_0 to 104_15 in synchronization with the rising and falling edges of the write clock signal WCK _ t. The controller 20 may transmit the remaining portion of the first training data as the data mask inversion signals DQ [0:15] to the semiconductor memory 100 through the fifth memory pads 105_0 and 105_1 in synchronization with the rising and falling edges of the write clock signal WCK _ t.

One embodiment is shown in FIG. 10, where the first training data is not sent to the semiconductor memory 100 through the sixth memory pads 106_0 and 106_1 or as write parity signals PARW [0:1 ]. However, the controller 20 may be changed to transmit another part of the first training data or dummy data as the write parity signal PARW [0:1] to the semiconductor memory 100 through the sixth memory pads 106_0 and 106_ 1.

Fig. 11 shows an example in which the controller 20 sends a FIFO register read command RD _ FIFO to the semiconductor memory 100. In fig. 11, "CK _ t" indicates the clock signal CK, and "CK _ c" indicates an inverted version of the clock signal CK. "CS" refers to a chip select signal for selecting the semiconductor memory 100. "CMD" is conceptually represented as command and address signals CA [0:6] and does not refer to the signals actually communicated by controller 20 and semiconductor memory 100.

Referring to fig. 1, 3, and 11, when the chip select signal CS transitions to a high level, the controller 20 may transmit a FIFO register read command RD _ FIFO to the semiconductor memory 100. The FIFO register read command RD _ FIFO is sent via the command and address signals CA [0:6 ]. The FIFO register read command RD _ FIFO may be transmitted during one cycle of the clock signal CK _ t or CK _ c. The FIFO register read command RD _ FIFO will be described more fully with reference to fig. 12.

For write training, the controller 20 may send the FIFO register read command RD _ FIFO multiple times. An example is shown in fig. 11, where the controller 20 sends a FIFO register read command RD _ FIFO two or more times. However, the controller 20 may transmit the FIFO register read command RD _ FIFO once to perform the first training operation or the second training operation.

Fig. 12 shows examples of command and address signals CA0 to CA6 of the FIFO register read command RD _ FIFO. Referring to fig. 11 and 12, at the rising edge "R" of the clock signal CK _ t, when the chip select signal CS has a high level "H", the command and address signals CA0 to CA6 of the FIFO register read command RD _ FIFO may sequentially have a low level "L", a high level "H", and a low level "L".

At the falling edge "F" of the clock signal CK _ t, the command and address signals CA0 to CA6 of the FIFO register read command RD _ FIFO may have an effective value "V" corresponding to any one of a high level and a low level, regardless of the level of the chip select signal CS ("X"). For example, a FIFO register read command RD _ FIFO without an option may not be associated with a falling edge of the clock signal CK _ t.

Fig. 13 shows an example in which the semiconductor memory 100 transmits the second training data to the controller 20 according to the FIFO register read command RD _ FIFO. In some embodiments, an example of sending the second training data according to the FIFO register read command RD _ FIFO after the FIFO register write command WR _ FIFO with the first option is shown in fig. 13. In FIG. 13, "WCK _ t" indicates one of the write clock signals WCK [0:1], and "WCK _ c" indicates an inverted version of the write clock signal WCK _ t.

Referring to fig. 1, 3, 11, and 13, the semiconductor memory 100 may receive a FIFO register read command RD _ FIFO and may transmit second training data to the controller 20 when a certain time elapses. The second training data may be transmitted in synchronization with the read data strobe signals RDQS [0:1] (or RDQS0 and RDQS1) output through the sixth memory pads 106_0 and 106_1 or the read data strobe signals RDQS2 and RDQS3 output through the sixth memory pads 106_2 and 106_ 3.

The semiconductor memory 100 may transmit a portion of the second training data as the data signals DQ [0:15] to the controller 20 through the fourth memory pads 104_0 to 104_15 in synchronization with rising and falling edges of the read data strobe signals RDQS [0:1 ]. The semiconductor memory 100 may transmit the remaining portion of the second training data as the read parity signal PARR [0:1] to the controller 20 through the fifth memory pads 105_0 and 105_1 in synchronization with the rising and falling edges of the read data strobe signals RDQS [0:1 ].

Fig. 14 shows an example in which the controller 20 transmits the third training data to the semiconductor memory 100 according to the FIFO register write command WR _ FIFO. In some embodiments, an example of sending the third training data according to the FIFO register write command WR _ FIFO with the second option is shown in fig. 14. In FIG. 14, "WCK _ t" indicates one of the write clock signals WCK [0:1], and "WCK _ c" indicates an inverted version of the write clock signal WCK _ t.

Referring to fig. 1, 3, 8, and 14, the controller 20 may transmit a FIFO register write command WR _ FIFO and may transmit third training data to the semiconductor memory 100 when a certain time elapses. The third training data may be transmitted to the semiconductor memory 100 in synchronization with the write clock signal WCK _ t or WCK _ c.

The controller 20 may transmit the third training data as the write parity signal PARW [0:1] to the semiconductor memory 100 through the sixth memory pads 106_0 and 106_1 in synchronization with the rising and falling edges of the write clock signal WCK _ t. One embodiment is shown in fig. 14, where the third training data is not transmitted to the semiconductor memory 100 through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_ 1. However, the controller 20 may be changed to transmit another part of the third training data or the dummy data to the semiconductor memory 100 through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_ 1.

Fig. 15 shows an example in which the semiconductor memory 100 transmits the fourth training data to the controller 20 according to the FIFO register read command RD _ FIFO. In some embodiments, an example of sending the fourth training data according to the FIFO register read command RD _ FIFO after the FIFO register write command WR _ FIFO with the second option is shown in fig. 15. In FIG. 15, "WCK _ t" indicates one of the write clock signals WCK [0:1], and "WCK _ c" indicates an inverted version of the write clock signal WCK _ t.

Referring to fig. 1, 3, 11, and 15, the semiconductor memory 100 may receive a FIFO register read command RD _ FIFO and may transmit fourth training data to the controller 20 when a certain time elapses. The fourth training data may be transmitted in synchronization with the read data strobe signals RDQS [0:1] (or RDQS0 and RDQS1) output through the sixth memory pads 106_0 and 106_1 or the read data strobe signals RDQS2 and RDQS3 output through the sixth memory pads 106_2 and 106_ 3.

The semiconductor memory 100 may transmit the fourth training data to the controller 20 in synchronization with the rising and falling edges of the read data strobe signals RDQS [0:1] through at least one selected from the data signals DQ [0:15] and the read parity signals PARR [0:1 ]. Signals not selected from the data signals DQ [0:15] and the read parity signals PARR [0:1] may not be used to transmit the fourth training data.

In some embodiments, the third training data received through one sixth memory pad 106_0 or 106_1 may be output through two or more pads. For example, the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_1 may output fourth training data (or a copy of the fourth training data) as data signals DQ [0:15] and read parity signals PARR [0:1 ].

Fig. 16A illustrates an example of one of the second data transfer and training blocks 170_0 and 170_1 according to an embodiment of the inventive concept. In some embodiments, an example of a second data transfer and training block 170_ m not associated with redirector 120 is shown in fig. 16A. Referring to fig. 3 and 16A, the second data transfer and training block 170_ m includes a data buffer 171_ m, a first-in-first-out (FIFO) register 172_ m, a deserializer 173_ m, and a serializer 174_ m.

In normal operation (e.g., not training), the data buffer 171_ m may communicate the write parity signal PARWm and the data mask inversion signal DMIm with the fifth memory pad 105_ m. In training, the data buffer 171_ m may transfer training data with the fifth memory pad 105_ m.

In some embodiments, the second data transfer and training block 170_ m may operate in the same manner as the first data transfer and training block 160_ i described with reference to fig. 4A, and thus, a description thereof will not be repeated here.

In some embodiments, except for the reference numbers of the signals and components exchanged with memory core MC, the first data transfer and training block of first data transfer and training blocks 160_0 to 160_15 that is not associated with redirector 120 may have the same structure as shown in fig. 16A and may operate in the same manner as described with reference to fig. 16A.

Fig. 16B illustrates another example of one of the second data transfer and training blocks 170_0 and 170_1 according to an embodiment of the inventive concept. In some embodiments, an example of a second data transfer and training block 170_ m' not associated with redirector 120 is shown in fig. 16B. Referring to fig. 3 and 16B, the second data transfer and training block 170_ m' includes a data buffer 171_ m, a FIFO register 172_ m, a deserializer 173_ m, a serializer 174_ m, and an encoder 175_ m.

In some embodiments, the second data transfer and training block 170_ m 'may operate in the same manner as the first data transfer and training block 160_ i' described with reference to fig. 4B, and thus, a description thereof will not be repeated here.

In some embodiments, except for the reference numbers of the signals and components exchanged with memory core MC, the first data transfer and training block of first data transfer and training blocks 160_0 to 160_15 that is not associated with redirector 120 may have the same structure as shown in fig. 16B and may operate in the same manner as described with reference to fig. 16B.

In some embodiments, the second data transfer and training block 170_ m of fig. 16A and the second data transfer and training block 170_ m' of fig. 16B may be used interchangeably in the detailed description.

Fig. 17A illustrates an example of one of the second data transfer and training blocks 170_0 and 170_1 according to an embodiment of the inventive concept. In some embodiments, an example of a second data transfer and training block 170_ n associated with redirector 120 is shown in fig. 17A. Referring to fig. 3 and 17A, the second data transfer and training block 170_ n includes a data buffer 171_ n, a first-in-first-out (FIFO) register 172_ n, a deserializer 173_ n, and a serializer 174_ n.

In normal operation (not training), the data buffer 171_ n may communicate the write parity signal PARRn and the data mask inversion signal DMIn with the fifth memory pad 105_ n. In training, the data buffer 171_ n may transfer training data with the fifth memory pad 105_ n.

The data buffer 171_ n, the FIFO register 172_ n, the deserializer 173_ n, and the serializer 174_ n may operate in the same manner as described with reference to fig. 4A, and thus, a description thereof will not be repeated here.

The third encoder 123 of the redirector 120 may be located on a path through which the FIFO register 172_ n sends data to the data buffer 171_ n. The third encoder 123 may operate in response to the FIFO register read command RD _ FIFO. When the FIFO register read command RD _ FIFO has the first option, the third encoder 123 may send the output of the FIFO register 172_ n to the data buffer 171_ n.

When the FIFO register read command RD _ FIFO has the second option, the third encoder 123 may transmit data (e.g., training data) transmitted from the data transfer, clock generation, and training block 180_ o (refer to fig. 18B) to the data buffer 171_ n.

That is, if the FIFO register write command WR _ FIFO is received after the FIFO register read command RD _ FIFO having the first option, the data buffer 171_ n may output the training data transmitted from the FIFO register 172_ n to the fifth memory pad 105_ n. Thus, the write training associated with the fifth memory pad 105_ n is performed.

If the FIFO register write command WR _ FIFO is received after the FIFO register read command RD _ FIFO having the second option, the data buffer 171_ n may output the training data transmitted from the data transfer, clock generation, and training block 180_ o (refer to fig. 18A) to the fifth memory pad 105_ n. Write training may be performed on the sixth memory pad 106_0 or 106_1 by redirecting the output of the training data.

In some embodiments, the first one of first data transfer and training blocks 160_0 through 160_15 associated with redirector 120 may have the same structure as shown in fig. 17A and may operate in the same manner as described with reference to fig. 17A, except for the signals and reference numbers of components exchanged with memory core MC. That is, the training data may be redirected to the first block 160 or the second block 170.

Fig. 17B illustrates an example of one of the second data transfer and training blocks 170_0 and 170_1 according to an embodiment of the inventive concept. In some embodiments, an example of a second data transfer and training block 170_ n' associated with redirector 120 is shown in fig. 17B. Referring to fig. 3 and 17B, the second data transfer and training block 170_ n' includes a data buffer 171_ n, a FIFO register 172_ n, a deserializer 173_ n, a serializer 174_ n, and an encoder 175_ n.

In response to a write command WR or a read command RD from the control logic 190, the encoder 175_ n may connect the parallelizer 173_ n and the serializer 174_ n with the data buffer 171_ n. In response to the FIFO register write command WR _ FIFO or the FIFO register read command RD _ FIFO, the encoder 175_ n may connect the output terminal of the data buffer 171_ n with the FIFO register 172_ n and may transmit the training data transmitted through the third encoder 123 to the data buffer 171_ n.

The parallelizer 173_ n may parallelize the data mask inversion signal DMIn into the data mask inversion signal DMI according to the write command WR. The serializer 174_ n may serialize the read parity PARR into the read parity signal PARRn according to the read command RD.

When the FIFO register read command RD _ FIFO has the first option, the third encoder 123 may transmit the training data transmitted from the FIFO register 172_ n to the data buffer 171_ n through the encoder 175_ n. When the FIFO register read command RD _ FIFO has the second option, the third encoder 123 may transmit training data transmitted from the data transfer, clock generation, and training block 180_ o (refer to fig. 18B) to the data buffer 171_ n.

In some embodiments, and within the detailed description, the second data transfer and training block 170_ n of fig. 17A and the second data transfer and training block 170_ n' of fig. 17B may be used interchangeably.

Fig. 18A illustrates an example of one of the data transfer, clock generation, and training blocks 180_0 and 180_1 according to an embodiment of the inventive concept. Referring to FIG. 3 and FIG. 18A, the data transfer, clock generation and training block 180_ o includes a data buffer 181_ o, a FIFO register 182_ o, a deserializer 183_ o, a read data strobe signal generator 184_ o and a read data strobe signal driver 185_ o.

The fourth encoder 124 of the redirector 120 may be located between the data buffer 181_ o and the FIFO register 182_ o. The data buffer 181_ o may temporarily store data (e.g., the write parity signal PARWo or training data) received from the sixth memory pad 106_ o, and may transmit the stored data to the fourth encoder 124. The data buffer 181_ o may operate in synchronization with one WCK of the write clock signals WCK [0:1 ].

The fourth encoder 124 may operate in response to a FIFO register read command RD _ FIFO. The fourth encoder 124 may connect the data buffer 181_ o and the FIFO register 182_ o when the FIFO register read command RD _ FIFO has the first option or when the FIFO register read command RD _ FIFO is not present.

When the FIFO register read command RD _ FIFO has the second option, the fourth encoder 124 may connect the FIFO register 182_ o and the second data transfer and training block 170_ n of fig. 17A. For example, the fourth encoder 124 may send data (e.g., training data) sent from the FIFO register 182_ o to the second data transfer and training block 170_ n associated with the redirector 120.

As another example, the fourth encoder 124 may send data (e.g., training data) sent from the FIFO register 182_ o to a first one of the first data transfer and training blocks 160_0 through 160_15 associated with the redirector 120.

In normal operation (e.g., not training), the data buffer 181_ o may receive the write parity signal PARWo from the sixth memory pad 106_ o. In training, data buffer 181_ o may receive training data from sixth memory pad 106_ o. The read data strobe signal driver 185_ o may output the read data strobe signal RDQSo when data is output regardless of training.

The operations of the FIFO register 182_ o, the deserializer 183_ o, the read data strobe signal generator 184_ o and the read data strobe signal driver 185_ o are the same as those described with reference to fig. 6A, and thus, the description thereof will not be repeated here.

In some embodiments, the data transfer, clock generation, and training blocks 180_0 and 180_1 may have the structure described with reference to fig. 18A and may operate in the manner described with reference to fig. 18A. The clock generation blocks 180_2 and 180_3 associated with the read data strobe signals RDQS2 and RDQS3 may include a read data strobe signal generator 184_ o and a read data strobe signal driver 185_ o in the assembly shown in FIG. 18A.

Fig. 18B illustrates an application of one of the data transfer, clock generation, and training blocks 180_0 and 180_1 according to an embodiment of the inventive concept. Referring to FIGS. 3 and 18B, the data transfer, clock generation and training block 180_ o' includes a data buffer 181_ o, a FIFO register 182_ o, a deserializer 183_ o, a read data strobe signal generator 184_ o, a read data strobe signal driver 185_ o, and an encoder 186_ o.

In response to a write command WR from the control logic 190, the encoder 186_ o can connect the data buffer 181_ o with the parallelizer 183_ o. In response to the FIFO register write command WR _ FIFO, the encoder 186_ o may send the output of the data buffer 181_ o to the fourth encoder 124. The parallelizer 183_ o may parallelize the write parity signal PARWo into the write parity PARW according to the write command WR.

When the FIFO register read command RD _ FIFO has the first option, the FIFO register 182_ o may not operate. As another example, the FIFO register 182_ o may output stored training data, and the fourth encoder 124 may block the training data output from the FIFO register 182_ o.

When the FIFO register read command RD _ FIFO has the second option, the FIFO register 182_ o may output the stored training data. The fourth encoder 124 may send the training data output from the FIFO register 182_ o to either the data transfer and training block associated with the redirector 120 in the first block 160 or the data transfer and training block 170_ n' in the second block 170.

In some embodiments, the data transfer, clock generation, and training block 180_ o of fig. 18A and the data transfer, clock generation, and training block 180_ o' of fig. 18B may be used interchangeably in the detailed description.

As described with reference to fig. 16A through 18B, the third block 180a may store the training data received through the sixth memory pads 106_0 and 106_1 in the FIFO register in response to the FIFO register write command WR _ FIFO. The third block 180a may send the stored training data to the first block 160 or the second block 170 according to a FIFO register read command RD _ FIFO.

The first block 160 or the second block 170 may output the training data transmitted from the third block 180 a. That is, the training data received through the sixth memory pads 106_0 and 106_1 in the third block 180a may be output to the outside after being redirected to the first block 160 or the second block 170. Therefore, the write training may be performed on the sixth memory pads 106_0 and 106_ 1.

Fig. 19 is a flowchart illustrating a write training method according to an embodiment of the inventive concept. Referring to fig. 1, 3 and 16A to 19, in operation S310, the controller 20 may transmit a FIFO register write command WR _ FIFO to the semiconductor memory 100. The controller 20 may transmit the first training data to the semiconductor memory 100 together with the FIFO register write command WR _ FIFO.

For example, the first training data may be transmitted through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_ 1. The semiconductor memory 100 may store the first training data in the FIFO registers 172_ m and 172_ n in response to the FIFO register write command WR _ FIFO.

In operation S320, the controller 20 may transmit a FIFO register read command RD _ FIFO having a first option to the semiconductor memory 100. In response to the FIFO register read command RD _ FIFO, the semiconductor memory 100 may output the data stored in the FIFO registers 172_ m and/or 172_ n to the controller 20 as second training data. The second training data may be transmitted through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_ 1.

Operations S310 and S320 may constitute a first training operation targeting the unimpeded pad to output training data. Thereafter, in operations S330 and S340, a second training operation may be performed on the obstructed pad to output training data. The second training operation may be a redirection training in which the input pads and output pads of the training data are redirected.

In operation S330, the controller 20 may transmit a FIFO register write command WR _ FIFO to the semiconductor memory 100. The controller 20 may transmit the third training data to the semiconductor memory 100 together with the FIFO register write command WR _ FIFO. For example, the third training data may be transmitted to the semiconductor memory 100 through the sixth memory pads 106_0 and 106_ 1. The semiconductor memory 100 may store the third training data in the FIFO register 182_ o in response to the FIFO register write command WR _ FIFO.

In operation S340, the controller 20 may transmit a FIFO register read command RD _ FIFO having the second option to the semiconductor memory 100. In response to the FIFO register read command RD _ FIFO having the second option, at least one of the first data transfer and training blocks 160_0 to 160_15 or at least one of the second data transfer and training blocks 170_0 and 170_1 in the second block 170 may output the third training data stored in the FIFO register 182_ o of the third block 180a to the controller 20 as fourth training data. The fourth training data may be output through at least one of the fourth memory pads 104_0 to 104_15 or at least one of the fifth memory pads 105_0 and 105_ 1.

Fig. 20 shows examples of command and address signals CA0 to CA6 of the FIFO register write command WR _ FIFO. Referring to fig. 11 and 20, at the rising edge "R" of the clock signal CK _ t, when the chip select signal CS has a high level "H", the command and address signals CA0 to CA6 of the FIFO register write command WR _ FIFO may sequentially have a low level "L", a high level "H", and a low level "L".

At the falling edge "F" of the clock signal CK _ t, the command and address signals CA0 to CA6 of the FIFO register write command WR _ FIFO may have an effective value "V" corresponding to any one of a high level and a low level regardless of the level of the chip select signal CS ("X"). For example, a FIFO register write command WR _ FIFO with no option may not be associated with a falling edge of the clock signal CK _ t.

Fig. 21 shows examples of command and address signals CA0 to CA6 of the FIFO register read command RD _ FIFO. Referring to fig. 8 and 21, the option of the FIFO register read command RD _ FIFO may be determined according to whether the command and address signals CA0 through CA6 have any value after the chip select signal CS has the high level "H" at the falling edge "F" of the clock signal CK _ t.

For example, at the rising edge "R" of the clock signal CK _ t, when the chip select signal CS has the high level "H", the command and address signals CA0 to CA6 of the FIFO register read command RD _ FIFO may sequentially have the low level "L", the high level "H", and the high level "H".

At the falling edge "F" of the clock signal CK _ t, the command and address signal CA0 of the FIFO register write command WR _ FIFO having the first option has the low level "L" regardless of the level of the chip select signal CS ("X"). The remaining command and address signals CA1 through CA6 may have an active level "V" corresponding to any one of a high level and a low level.

At the falling edge "F" of the clock signal CK _ t, the command and address signal CA0 of the FIFO register read command RD _ FIFO having the second option has a high level "H" regardless of the level of the chip select signal CS ("X"). The remaining command and address signals CA1 through CA6 may have an active level "V" corresponding to any one of a high level and a low level.

As described with reference to fig. 21, the option of the FIFO register read command RD _ FIFO is selected according to whether the command and address signal CA0 has a high level "H" or a low level "L" at the falling edge "F" of the clock signal CK _ t. Since no additional period of the clock signal CK _ t or additional pad is required, overhead caused by the option of the FIFO register write command WR _ FIFO is suppressed.

In some embodiments, the first training data stream according to the FIFO register write command WR _ FIFO may be the same as shown in fig. 10. The second training data stream according to the FIFO register read command RD _ FIFO with the first option may be the same as shown in fig. 13.

The third training data stream according to the FIFO register write command WR _ FIFO may be the same as shown in fig. 14. The fourth training data stream according to the FIFO register read command RD _ FIFO with the second option may be the same as shown in fig. 15.

Fig. 22 is a flowchart illustrating a write training method according to an embodiment of the inventive concept. Referring to fig. 1, 3, 16A through 18B, and 22, the controller 20 may transmit a FIFO register write command WR _ FIFO to the semiconductor memory 100 in operation S410. The controller 20 may transmit the first training data to the semiconductor memory 100 together with the FIFO register write command WR _ FIFO.

For example, the first training data may be transmitted through the fourth memory pads 104_0 to 104_15, the fifth memory pads 105_0 and 105_1, and the sixth memory pads 106_0 and 106_ 1. The semiconductor memory 100 may store the first training data in the FIFO registers 172_ m, 172_ n, and/or 182_ o in response to the FIFO register write command WR _ FIFO.

In operation S420, the controller 20 may transmit a FIFO register read command RD _ FIFO having a first option to the semiconductor memory 100. According to the FIFO register read command RD _ FIFO, the semiconductor memory 100 may output part of the stored first training data corresponding to the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_1 to the controller 20 as second training data. The second training data may be transmitted through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_ 1.

In operation S430, the controller 20 may transmit a FIFO register read command RD _ FIFO having the second option to the semiconductor memory 100. In response to the FIFO register read command RD _ FIFO having the second option, at least one of the first data transfer and training blocks 160_0 to 160_15 or at least one of the second data transfer and training blocks 170_0 and 170_1 in the second block 170 may output the remaining portion of the first training data stored in the FIFO register 182_ o of the third block 180a as fourth training data to the controller 20.

The fourth training data may be output through at least one of the fourth memory pads 104_0 to 104_15 or at least one of the fifth memory pads 105_0 and 105_ 1. That is, according to the third embodiment shown in fig. 22, the first training data and the third training data may be simultaneously transmitted to the semiconductor memory 100.

Fig. 23 shows an example of transmitting the first training data and the third training data to the semiconductor memory 100 according to the FIFO register write command WR _ FIFO. In FIG. 23, "WCK _ t" indicates one of the write clock signals WCK [0:1], and "WCK _ c" indicates an inverted version of the write clock signal WCK _ t.

Referring to fig. 1, 3, 11, and 23, when a certain time elapses after the FIFO register write command WR _ FIFO is transmitted, the controller 20 may transmit the first training data and the third training data to the semiconductor memory 100. The controller 20 may transmit a portion of the first training data as the data signals DQ [0:15] to the semiconductor memory 100 through the fourth memory pads 104_0 to 104_15 in synchronization with the rising and falling edges of the write clock signal WCK _ t.

The controller 20 may transmit the remaining portion of the first training data as the data mask inversion signal DMI [0:1] to the semiconductor memory 100 through the fifth memory pads 105_0 and 105_1 in synchronization with the rising and falling edges of the write clock signal WCK _ t. The controller 20 may transmit the third training data as the write parity signal PARW [0:1] to the semiconductor memory 100 through the sixth memory pads 106_0 and 106_1 in synchronization with the rising and falling edges of the write clock signal WCK _ t.

In some embodiments, the second training data stream according to the FIFO register read command RD _ FIFO with the first option may be the same as shown in fig. 13. The fourth training data stream according to the FIFO register read command RD _ FIFO with the second option may be the same as shown in fig. 15.

Fig. 24 is a flowchart illustrating a write training method according to an embodiment of the inventive concept. Referring to fig. 1, 3 and 24, the controller 20 may program the mode register 110 of the semiconductor memory 100 in operation S510. For example, the controller 20 may program the mode register 110 such that the option of the FIFO register write command WR _ FIFO or the option of the FIFO register read command RD _ FIFO is set to the first option. Training is then performed according to the programmed options.

In operation S520, the controller 20 may transmit a FIFO register write command WR _ FIFO to the semiconductor memory 100. The controller 20 may transmit the first training data to the semiconductor memory 100 according to the FIFO register write command WR _ FIFO. The first training data may be transmitted through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_1, as described with reference to fig. 10.

In operation S530, the controller 20 may transmit a FIFO register read command RD _ FIFO to the semiconductor memory 100. According to the FIFO register read command RD _ FIFO, the semiconductor memory 100 may transmit the second training data to the controller 20. The second training data may be transmitted through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_1, as described with reference to fig. 13.

In operation S540, the controller 20 may program the mode register 110 of the semiconductor memory 100. For example, the controller 20 may program the mode register 110 such that the option of the FIFO register write command WR _ FIFO or the option of the FIFO register read command RD _ FIFO is set to the second option. Thereafter, training continues according to the programming options.

In operation S550, the controller 20 may transmit a FIFO register write command WR _ FIFO to the semiconductor memory 100. The controller 20 may transmit the third training data to the semiconductor memory 100 according to the FIFO register write command WR _ FIFO. The third training data may be transmitted through the sixth memory pads 106_0 and 106_1, as described with reference to fig. 14.

In operation S560, the controller 20 may transmit a FIFO register read command RD _ FIFO to the semiconductor memory 100. According to the FIFO register read command RD _ FIFO, the semiconductor memory 100 may transmit the fourth training data to the controller 20. The fourth training data may be transmitted through at least one pad selected from the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_1, as described with reference to fig. 15.

Fig. 25 is a flowchart illustrating a write training method according to an embodiment of the inventive concept. Referring to fig. 1, 3 and 25, the controller 20 may program the mode register 110 of the semiconductor memory 100 in operation S610. For example, the controller 20 may program the mode register 110 such that the option of the FIFO register read command RD _ FIFO is set to the first option.

In operation S620, the controller 20 may transmit a FIFO register write command WR _ FIFO to the semiconductor memory 100. The controller 20 may transmit the first training data to the semiconductor memory 100 according to the FIFO register write command WR _ FIFO. The first training data may be transmitted through the fourth memory pads 104_0 to 104_15, the fifth memory pads 105_0 and 105_1, and the sixth memory pads 106_0 and 106_1, as described with reference to fig. 23.

In operation S630, the controller 20 may transmit a FIFO register read command RD _ FIFO to the semiconductor memory 100. According to the FIFO register read command RD _ FIFO, the semiconductor memory 100 may transmit the second training data to the controller 20. The second training data may be transmitted through the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_1, as described with reference to fig. 13.

In operation S640, the controller 20 may program the mode register 110 of the semiconductor memory 100. For example, the controller 20 may program the mode register 110 such that the option of the FIFO register read command RD _ FIFO is set to the second option. Training continues according to the programming options.

In operation S650, the controller 20 may transmit a FIFO register read command RD _ FIFO to the semiconductor memory 100. According to the FIFO register read command RD _ FIFO, the semiconductor memory 100 may transmit the fourth training data to the controller 20. The fourth training data may be transmitted through at least one pad selected from the fourth memory pads 104_0 to 104_15 and the fifth memory pads 105_0 and 105_1, as described with reference to fig. 15.

Fig. 26A illustrates another example of one of the first data transfer and training blocks 160_0 to 160_15 according to an embodiment of the inventive concept. In some embodiments, an example of a first data transfer and training block 160_ p associated with redirector 120 is shown in fig. 26A. Referring to fig. 3 and 26A, the first data transfer and training block 160_ p includes a data buffer 161_ p, a first-in first-out (FIFO) register 162_ p, a deserializer 163_ p, and a serializer 164_ p.

In normal operation (e.g., not training), data buffer 161_ p may communicate data signal DQp with fourth memory pad 104_ p. In training, the data buffer 161_ p may communicate training data with the fourth memory pad 104_ p.

The data buffer 161_ p, the FIFO register 162_ p, the deserializer 163_ p, and the serializer 164_ p may operate in the same manner as described with reference to fig. 5A, and thus, a description thereof will not be repeated here.

In some embodiments, the first data transfer and training block 160_ p may complete training with the data transfer, clock generation and training block 180_ k (refer to fig. 6A) according to one FIFO register write command WR _ FIFO and one FIFO register read command RD _ FIFO.

In training, when transmitting the FIFO register write command WR _ FIFO, the controller 20 may transmit training data to the fourth memory pads 104_0 to 104_15, the fifth memory pads 105_0 and 105_1, and the sixth memory pads 106_0 to 106_ 3. That is, the controller 20 may send training data to all pads for training.

If a FIFO register write command WR _ FIFO is received, the data transfer, clock generation, and training block 180_ k may output training data (e.g., a first combined training data) to the fifth encoder 125. In addition, the data buffer 161_ p may output training data (e.g., second combined training data) received through the fourth memory pad 104_ p to the fifth encoder 125.

If a FIFO register write command, WR _ FIFO, is received, the fifth encoder 125 may perform encoding on the first and second pieces of combined training data. For example, the fifth encoder 125 may perform an XOR operation on the plurality of pieces of first combined training data and the second combined training data. The fifth encoder 125 may store the encoding result (e.g., the third combined data) in the FIFO register 162_ p.

If the FIFO register read command RD _ FIFO is received, the FIFO register 162_ p may output the storage data to the data buffer 161_ p as fourth combined data. The data buffer 161_ p may transmit the fourth combined data through the fourth memory pad 104_ p.

That is, the first data transfer and training blocks 160_0 to 160_15, the second data transfer and training blocks 170_0 and 170_1, and the data transfer, clock generation, and training blocks 180_0 and 180_1 may perform (or complete) training according to a FIFO register write command WR _ FIFO of one option-less (i.e., without or regardless of the first option or the second option as described herein) and a FIFO register read command RD _ FIFO of one option-less (i.e., without or regardless of the first option or the second option as described herein).

Fig. 26B illustrates an application of another one of the first data transfer and training blocks 160_0 to 160_15 illustrated in fig. 25. In some embodiments, an example of a first data transfer and training block 160_ p' associated with redirector 120 is shown in fig. 26B. Referring to fig. 3 and 26B, the first data transfer and training block 160_ p' includes a data buffer 161_ p, a FIFO register 162_ p, a deserializer 163_ p, a serializer 164_ p, and an encoder 165_ p.

In response to a write command WR or a read command RD from the control logic 190, the encoder 165_ p may connect the deserializer 163_ p and the serializer 164_ p with the data buffer 161_ p. In response to the FIFO register write command WR _ FIFO or the FIFO register read command RD _ FIFO, the encoder 165_ p may connect the output of the FIFO register 162_ p with the data buffer 161_ p, and may connect the output of the data buffer 161_ p with the fifth encoder 125.

Parallelizer 163_ p can parallelize data signal DQp into input data DIN according to write command WR. The serializer 164_ p may serialize the output data DOUT into the data signal DQp according to the read command RD.

If a FIFO register write command WR _ FIFO is received, the data transfer, clock generation, and training block 180_ k' (referring to FIG. 6B) may output training data (e.g., a first combined training data) to the fifth encoder 125. Further, the data buffer 161_ p may output training data (e.g., second combined training data) received through the fourth memory pad 104_ p as a data signal DQp to the fifth encoder 125.

If a FIFO register write command, WR _ FIFO, is received, the fifth encoder 125 may perform encoding on the first and second pieces of combined training data. For example, the fifth encoder 125 may perform an XOR operation on the plurality of pieces of first combined training data and the second combined training data. The fifth encoder 125 may store the encoding result (e.g., the third combined data) in the FIFO register 162_ p.

If the FIFO register read command RD _ FIFO is received, the FIFO register 162_ p may output the storage data to the data buffer 161_ p as fourth combined data. The data buffer 161_ p may send the fourth combined data as the data signal DQp through the fourth memory pad 104_ p.

Fig. 27A illustrates an example of one of the second data transfer and training blocks 170_0 and 170_1 according to an embodiment of the inventive concept. In some embodiments, an example of a second data transfer and training block 170_ q associated with redirector 120 is shown in fig. 27A. Referring to fig. 3 and 27A, the second data transfer and training block 170_ q includes a data buffer 171_ q, a first-in-first-out (FIFO) register 172_ q, a deserializer 173_ q, and a serializer 174_ q.

In normal operation (e.g., not training), the data buffer 171_ q may communicate the read parity signal PARWq and the data mask inversion signal DMIq with the fifth memory pad 105_ q. In training, the data buffer 171_ q may transfer training data with the fifth memory pad 105_ q.

The data buffer 171_ q, the FIFO register 172_ q, the deserializer 173_ q, and the serializer 174_ q may operate in the same manner as described with reference to fig. 4A, and thus, a description thereof will not be repeated here.

In some embodiments, the second data transfer and training block 170_ q may complete training with the data transfer, clock generation and training block 180_ o (refer to fig. 18A) according to one FIFO register write command WR _ FIFO and one FIFO register read command RD _ FIFO.

When transmitting the FIFO register write command WR _ FIFO, the controller 20 may transmit the training data to the fourth memory pads 104_0 to 104_15, the fifth memory pads 105_0 and 105_1, and the sixth memory pads 106_0 to 106_ 3. That is, the controller 20 may send training data to all pads for training.

If a FIFO register write command WR _ FIFO is received, the data transfer, clock generation, and training block 180_ o may store training data (e.g., a first combined training data) in the FIFO register 182_ o. In addition, the data buffer 171_ q may store training data (e.g., second combined training data) received through the fifth memory pad 105_ q in the FIFO register 172_ q.

If a FIFO register read command RD _ FIFO is received, the data transfer, clock generation, and training block 180_ o may output the first combined training data to the fifth encoder 125. The FIFO register 172_ q may output the second combined training data to the fifth encoder 125.

Fifth encoder 125 may perform encoding on the plurality of pieces of first combined training data and second combined training data. For example, the fifth encoder 125 may perform an XOR operation on the plurality of pieces of first combined training data and the second combined training data. The fifth encoder 125 may output an encoding result (e.g., third combined data) to the fifth memory pad 105_ q through the data buffer 171_ q.

That is, the first data transfer and training blocks 160_0 to 160_15, the second data transfer and training blocks 170_0 and 170_1, and the data transfer, clock generation, and training blocks 180_0 and 180_1 may perform (or complete) training according to a FIFO register write command WR _ FIFO of one option-less (i.e., without or regardless of the first option or the second option as described herein) and a FIFO register read command RD _ FIFO of one option-less (i.e., without or regardless of the first option or the second option as described herein).

Fig. 27B illustrates an example of one of the second data transfer and training blocks 170_0 and 170_1 according to an embodiment of the inventive concept. In some embodiments, an example of a second data transfer and training block 170_ q' associated with redirector 120 is shown in fig. 27B. Referring to fig. 3 and 27B, the second data transfer and training block 170_ q' includes a data buffer 171_ q, a FIFO register 172_ q, a deserializer 173_ q, a serializer 174_ q, and an encoder 175_ q.

In response to a write command WR or a read command RD from the control logic 190, the encoder 175_ q may connect the deserializer 173_ q and the serializer 174_ q with the data buffer 171_ q. In response to the FIFO register write command WR _ FIFO or the FIFO register read command RD _ FIFO, the encoder 175_ q may connect the output terminal of the data buffer 171_ q with the FIFO register 172_ q and may transmit the training data transmitted through the fifth encoder 125 to the data buffer 171_ q.

The parallelizer 173_ q may parallelize the data mask inversion signal DMIq into the data mask inversion signal DMI according to the write command WR. The serializer 174_ q may serialize the read parity PARR into a read parity signal PARRq according to the read command RD.

If a FIFO register write command WR _ FIFO is received, the data transfer, clock generation, and training block 180_ o' (referring to FIG. 18B) may store training data (e.g., a first combined training data) in the FIFO register 182_ o. In addition, the data buffer 171_ q may store training data (e.g., second combined training data) received through the fifth memory pad 105_ q in the FIFO register 172_ q.

If a FIFO register read command RD _ FIFO is received, the data transfer, clock generation, and training block 180_ o' may output the first combined training data to the fifth encoder 125. The FIFO register 172_ q may output the second combined training data to the fifth encoder 125.

Fifth encoder 125 may perform encoding on the plurality of pieces of first combined training data and second combined training data. For example, the fifth encoder 125 may perform an XOR operation on the plurality of pieces of first combined training data and the second combined training data. The fifth encoder 125 may output an encoding result (e.g., third combined data) to the fifth memory pad 105_ q through the data buffer 171_ q.

As described above, according to the embodiments of the inventive concept, write training may be performed on a pad designated not to transmit data in reading and designated to transmit data in writing. Accordingly, a semiconductor memory having improved reliability, a memory system including the semiconductor memory, and an operating method of the semiconductor memory are provided.

In the above embodiments, components of embodiments using the inventive concept are referenced by using the terms "block," "engine," "logic," and the like. The "blocks," "engines," or "logic" may be implemented in various hardware devices, such as Integrated Circuits (ICs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and Complex Programmable Logic Devices (CPLDs), firmware driven in hardware devices, software such as applications, or a combination of hardware devices and software. Further, "block," "engine," or "logic" may include circuitry or Intellectual Property (IP) implemented with a semiconductor device.

According to the inventive concept, the read data strobe signal and the write parity data are communicated through the same pad, and training for the write parity is performed by using the other pad. Accordingly, reliability of the semiconductor memory is improved by applying the read data strobe signal and the write parity data to the semiconductor memory without increasing the number of pads.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe members, regions, layers, portions, sections, components and/or elements of exemplary embodiments of the invention, these terms should not be construed as limiting the members, regions, layers, portions, sections, components and/or elements. These terms are only used to distinguish one element, region, portion, section, component or element from another element, region, portion, section, component or element. Thus, a first component, region, portion, section, component or element described below could also be termed a second component, region, portion, section, component or element without departing from the scope of the inventive concept. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While certain exemplary embodiments may be implemented differently, the particular order of the processes may be performed differently than described. For example, two processes described in succession may be executed substantially concurrently or in the reverse order to that described.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" modify the entire list of elements before the list of elements and do not modify individual elements of the list.

It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other words used to describe the relationship between such elements or layers should be interpreted in a similar manner (e.g., "between" and "directly between," adjacent "and" directly adjacent, "" on.

Like numbers refer to like elements throughout. Accordingly, the same or similar numbers may be described with reference to other figures, even if neither mentioned nor described in the corresponding figures. Further, elements not denoted by reference numerals may be described with reference to other drawings.

While the inventive concept has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.