1. A reference current determining method of a nonvolatile memory unit is applied to a mass production test stage of a memory chip, and comprises the following steps:

receiving a test reference current instruction sent by a tester, wherein the test reference current instruction comprises a minimum gear number;

generating a plurality of reference current values with different gears;

traversing the reference current value to execute reading operation on the memory chip, respectively performing reading operation verification on the memory chip, and recording the number of gears of the reference current value capable of passing verification, the maximum reference current value capable of passing verification and the minimum reference current value capable of passing verification;

and when the gear number is larger than or equal to the minimum current gear number, determining the optimal reference current value applied to the memory chip according to the maximum reference current value and the minimum reference current value.

2. The reference current determination method according to claim 1, wherein the test reference current command further includes a verify data command code for instructing writing of data for read operation verification to the memory chip.

3. The reference current determination method according to claim 1, wherein the reference current values of the plurality of stages different from each other are linearly changed in magnitude.

4. The method for determining the reference current according to any one of claims 1 to 3, wherein traversing the reference current values to perform a read operation on the memory chips and performing a read operation check on the memory chips respectively comprises:

traversing from the reference current value of the lowest first gear;

and taking the currently selected reference current value as the current reference current value in each traversal, executing read operation on the memory chip by using the current reference current value, and performing data verification on the read data.

5. The reference current determination method according to claim 4, wherein the recording of the number of shift stages of the reference current value that can pass the verification, the maximum reference current value that can pass the verification, and the minimum reference current value that can pass the verification includes:

when the reading operation corresponding to the current reference current value passes the verification, adding one to the gear number;

if the read operation verification corresponding to the current reference current value is the read operation verification which is passed for the first time in the traversal process, recording the current reference current value as a minimum reference current value and a maximum reference current value;

and if the current reference current value is larger than the maximum reference current value, recording the current reference current value as the maximum reference current value.

6. The reference current determination method of claim 1, wherein determining an optimal reference current value to apply to the memory chip based on the maximum reference current value and the minimum reference current value comprises:

determining a median gear between the maximum reference current value and the minimum reference current value according to the gear of the reference current value;

shifting the median gear according to a preset shifting rule;

the reference current value obtained by the offset is used as an optimal reference current value.

7. The method of claim 1, wherein after obtaining the optimal reference current value, further comprising:

receiving a reference current value curing instruction sent by the tester;

and solidifying the optimal reference current value to a parameter configuration area of the memory chip according to the reference current value solidification instruction.

8. The reference current determination method according to claim 1, further comprising:

and when the gear number is smaller than the minimum current gear number, returning error information to the testing machine.

9. A reference current determination apparatus comprising at least one processor and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the reference current determination method of any one of claims 1 to 8.

10. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the reference current determination method according to any one of claims 1 to 8.

Background

In a read operation of a memory cell of a nonvolatile memory chip, a reference current is usually compared with a read current of the memory cell to indicate data stored in the memory cell (for example, when the read current of the memory cell is greater than the reference current, it indicates that stored data is 1, and when the read current of the memory cell is less than the reference current, it indicates that stored data is 0). In the prior art, a reference current is usually set at a CP Test (Circuit combining Test) stage of mass production of memory chips, a Circuit is first designed in a memory chip to generate a series of reference current values, and then a reference current relatively good for a read operation is obtained according to batch chip engineering Test data and experience of an engineer and is used as a reference current for factory setting of the batch memory chips.

However, due to different production processes, the actual optimal reference current values of different memory chips are different, and the reference current values of some memory chips are not optimal due to the above method, which affects the accuracy of the read operation.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the invention provides a method and a device for determining reference current of a nonvolatile memory unit and a storage medium, so that each memory chip can set the reference current value according to the actual condition in the memory chip, thereby making up performance difference caused by factors such as production process fluctuation and the like and improving the reliability of the chip.

In a first aspect, an embodiment of the present invention provides a reference current determining method, which is applied to a mass production test stage of a memory chip, and the reference current determining method includes:

receiving a test reference current instruction sent by a tester, wherein the test reference current instruction comprises a minimum gear number;

generating a plurality of reference current values with different gears;

traversing the reference current value to execute reading operation on the memory chip, respectively performing reading operation verification on the memory chip, and recording the number of gears of the reference current value capable of passing verification, the maximum reference current value capable of passing verification and the minimum reference current value capable of passing verification;

and when the gear number is larger than or equal to the minimum current gear number, determining the optimal reference current value applied to the memory chip according to the maximum reference current value and the minimum reference current value.

The reference current determining method provided by the embodiment of the invention at least has the following beneficial effects: the method comprises the steps that a minimum gear position number is set in a test reference current instruction, so that a memory chip is subjected to chip screening in a test process in a mode that the gear number of a reference current value passing data verification meets the minimum gear position number, and on the other hand, for the memory chip meeting the minimum gear position number, an optimal reference current value is determined based on the maximum reference current value and the minimum reference current value which can pass verification, so that the obtained optimal reference current value is suitable for the current memory chip, therefore, the problem caused by batch setting of the reference current value according to experience of engineers in the prior art can be avoided, the reference current value can be set for the memory chips with different production processes according to the internal actual conditions of the memory chips, the performance difference caused by factors such as production process fluctuation is made up, and the reliability of the chips is improved.

In some embodiments, the test reference current instruction further includes a verification data instruction code for instructing to write data for read operation verification to the memory chip.

In some embodiments, the reference current values of the plurality of gears different from each other vary linearly in magnitude.

In some embodiments, the traversing the reference current value to perform a read operation on a memory chip and perform a read operation verification on the memory chip respectively includes:

traversing from the reference current value of the lowest first gear;

and taking the currently selected reference current value as the current reference current value in each traversal, executing read operation on the memory chip by using the current reference current value, and performing data verification on the read data.

In some embodiments, the recording the number of gear positions of the reference current value that can pass the verification, the maximum reference current value that can pass the verification, and the minimum reference current value that can pass the verification includes:

when the reading operation corresponding to the current reference current value passes the verification, adding one to the gear number;

if the read operation verification corresponding to the current reference current value is the read operation verification which is passed for the first time in the traversal process, recording the current reference current value as a minimum reference current value and a maximum reference current value;

and if the current reference current value is larger than the maximum reference current value, recording the current reference current value as the maximum reference current value.

In some embodiments, said determining an optimal reference current value to apply to said memory chip as a function of said maximum reference current value and said minimum reference current value comprises:

determining a median gear between the maximum reference current value and the minimum reference current value according to the gear of the reference current value;

shifting the median gear according to a preset shifting rule;

the reference current value obtained by the offset is used as an optimal reference current value.

In some embodiments, after obtaining the optimal reference current value, the method further includes:

receiving a reference current value curing instruction sent by the tester;

and solidifying the optimal reference current value to a parameter configuration area of the memory chip according to the reference current value solidification instruction.

In some embodiments, further comprising:

and when the gear number is smaller than the minimum current gear number, returning error information to the testing machine.

In a second aspect, an embodiment of the present invention further provides a reference current determining apparatus, including at least one processor and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the reference current determination method of the first aspect.

In a third aspect, the present invention also provides a computer-readable storage medium, which stores computer-executable instructions for causing a computer to execute the reference current determination method according to the first aspect.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is an overall flow chart of a reference current determination method provided by an embodiment of the invention;

FIG. 2 is a flowchart of a method for traversing a reference current value according to an embodiment of the present invention;

FIG. 3 is a flowchart for recording the number of gears, the minimum reference current value and the maximum reference current value according to an embodiment of the present invention;

FIG. 4 is a flow chart of a method for determining an optimal reference current value provided by an embodiment of the present invention;

FIG. 5 is a flowchart of a method for solidifying an optimal reference current value according to an embodiment of the present invention;

FIG. 6 is an overall flow chart of a reference current determination method provided by an example of the present invention;

fig. 7 is a schematic block diagram of a reference current determining apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The embodiment of the invention provides a reference current determining method and device for a nonvolatile memory unit and a storage medium, and the method and device are used for calculating the optimal reference current value suitable for the current memory unit according to the maximum reference current value and the minimum reference current value which pass the test in the memory unit, so that the performance difference caused by factors such as production process fluctuation is made up, and the reliability of a chip is improved.

The embodiments of the present invention will be further explained with reference to the drawings.

Referring to fig. 1, an embodiment of the present invention provides a reference current determining method applied to a mass production test stage of a memory chip, where the reference current determining method includes, but is not limited to, the following steps S100, S200, S300, and S400.

Step S100, receiving a test reference current instruction sent by a tester, wherein the test reference current instruction comprises a minimum gear number;

step S200, generating a plurality of reference current values with different gears;

step S300, reading operation is executed on the memory chips by traversing the reference current values, reading operation verification is respectively carried out on the memory chips, and the gear number of the reference current values capable of passing verification, the maximum reference current value capable of passing verification and the minimum reference current value capable of passing verification are recorded;

and S400, when the gear number is larger than or equal to the minimum current gear number, determining the optimal reference current value applied to the memory chip according to the maximum reference current value and the minimum reference current value.

The nonvolatile memory unit is widely applied to the current mainstream memory products, the nonvolatile memory unit is obtained through semiconductor process production, a plurality of memory chips are divided from a wafer in the production process, and the memory chips are tested and assembled into the memory products after leaving a factory.

In the mass production test process of the memory chip, the mass production test is performed by contacting the memory chip with a tester, for example, by contacting a contact on the memory chip with a metal needle, the tester sends a test instruction to the memory chip and receives a result returned by the memory chip, thereby determining whether the memory chip passes the test. The above Test is generally called a CP Test (Circuit combining Test), in which one loop is to set a reference current for the memory chip. The current reference current is usually set according to test data of a batch of memory chips in the CP test and the judgment of the experience of an engineer, and the reference current is applied to the batch of memory chips. Obviously, even if the memory chips in the same batch are influenced by the production process, the optimal reference currents suitable for different memory chips are different, and the set reference currents are not optimal for part of the memory chips, so that the read operation of the memory chips is influenced.

In order to solve the problem of inaccurate reference current, in the CP test process, the optimal reference current value is determined according to the maximum reference current value and the minimum reference current value recorded by each memory chip during the test, specifically, a test reference current instruction sent by a tester is received under the condition that the memory chip is connected to the tester, and the reference current test is started according to the test reference current instruction. The test reference current command may be composed according to the following command format:

instruction code + check data selection code + minimum number of bits

The instruction code is used for identifying the test items of the memory chip, the check data selection code is used for generating corresponding check data (related to the preprocessed write-in custom data) by the memory chip, whether the data read out by the reading operation is correct or not is judged according to the check data, and the minimum gear number is used for judging whether the gear number verified by the reading operation meets the requirement or not by the memory chip.

It can be understood that the memory chip for CP test is subjected to the preprocessing process and then the reference current test; the pretreatment process comprises multiple times of cyclic erasing and writing of the whole chip, writing of test data, high-temperature baking and the like. For example, in some cases, multiple erase cycles include multiple erase-program operations on all memory cells of the memory chip, with the number of erase cycles typically varying from a few times to hundreds of times as desired; writing test data, writing corresponding data according to different requirements, such as writing all 0 data, all 1 data or random data; the high-temperature baking is performed by setting different baking temperatures and baking times according to different requirements, for example, baking at 250 ℃ for 2 hours. After the memory chip is pretreated, the memory chip can be connected with a testing machine to start testing.

After the memory chip receives the test reference current instruction, a plurality of different reference current values are generated in the internal circuit, and the reference current values change according to a certain rule, for example, the reference current values are in a linear change relation of an equal difference series, the reference current value of the lowest gear is 1mA, the reference current value of the highest gear is 20mA, and the reference current values are divided into 20 reference current values which are 1mA, 2mA, 3mA, 4mA, … … and 20mA respectively when the reference current values change in a mode that the difference between the gears is 1 mA. Through the gear division, the reference current value can be traversed sequentially.

And comparing the data obtained by each reading operation with the verification data generated by the verification data selection code, and indicating that the reference current value of the current first gear is valid through verification. Therefore, when the read operation and the read operation verification are carried out on the reference current values of all the gears once, which reference current values pass the verification can be determined, so that the number of the gears, the maximum reference current value and the minimum reference current value of the reference current values passing the verification are determined.

It can be understood that, since the test reference current command specifies the minimum gear number, after traversing all the reference current values, if the gear number of the reference current passing the verification is found to be smaller than the minimum gear number, it indicates that the current memory chip has a serious problem and needs to return an error message to the test machine. And if the number of the gears of the reference current passing the verification is greater than or equal to the minimum gear number, the current memory chip is indicated to pass the data verification, and the optimal reference current value is determined according to the maximum reference current value and the minimum reference current value. It can be understood that the optimal reference current value obtained by the test is related to the maximum reference current value and the minimum reference current value of the current memory chip, so that the optimal reference current value is suitable for the current memory chip, is obtained under the influence of factors such as a production process and the like, is the reference current value which is matched with the current memory chip and is most suitable for the read operation, and ensures the accuracy of the memory chip in the read operation.

In step S300, the reference current value is traversed to perform a read operation on the memory chips, and the read operation verification is performed on the memory chips, referring to fig. 2, specifically including but not limited to the following steps S310 and S320:

step S310, traversing from the reference current value of the lowest first gear;

and step S320, taking the currently selected reference current value as the current reference current value in each traversal, executing read operation on the memory chip by using the current reference current value, and performing data verification on the read data.

Since the reference current value is linearly changed, in order to determine the maximum reference current value and the minimum reference current value, step S310 is performed according to the reference current value going from low to high, and the reference current value of the current gear is used as the current reference current value each time the read operation and the read operation check are performed on the reference current value of the current gear; and when the reading operation and the reading operation verification corresponding to the current reference current value are completed, increasing the first-gear reference current value, and taking the reference current value after the first gear is increased as the current reference current value until the maximum first gear of the reference current value is reached.

It is understood that, in step S300, the number of gear positions of the reference current value capable of being verified, the maximum reference current value capable of being verified, and the minimum reference current value capable of being verified are recorded, and referring to fig. 3, the following steps S330, S340, and S350 are specifically included, but not limited to:

step S330, when the reading operation corresponding to the current reference current value passes the verification, adding one to the gear number;

step S340, if the read operation check corresponding to the current reference current value is the read operation check which is passed for the first time in the traversal process, recording the current reference current value as a minimum reference current value and a maximum reference current value;

in step S350, if the current reference current value is greater than the maximum reference current value, the current reference current value is recorded as the maximum reference current value.

According to the traversing mode of the step S310 and the step S320, reading operation and reading operation verification are carried out once when the reference current value of the first gear is selected, the verification result of the reference current value of the current gear is obtained and recorded at the same time, and if the verification result is passed, the number of the gears is increased by one; in the process of traversing the reference current value, the verification result is passed for the first time, the current reference current value is set as a minimum reference current value and a maximum reference current value at the same time, and the maximum reference current value is updated in the verification process of the subsequent gears because the reference current value of the subsequent gears is higher than the reference current value adopted in the first verification; if the subsequent gears cannot pass the verification, the fact that only the first-gear reference current passes the test is indicated, and the minimum reference current value and the maximum reference current value are equal; and if the reference current value of the subsequent gear passes the verification, updating the maximum reference current value once every time the verification passes until the current reference current value reaches the highest first gear.

Referring to fig. 4, after the minimum reference current value and the maximum reference current value are obtained, the optimal reference current value may be determined in such a manner that the optimal reference current value applied to the memory chip is determined according to the maximum reference current value and the minimum reference current value in step S400, including, but not limited to, the following steps S410, S420, and S430:

step S410, determining a median gear between the maximum reference current value and the minimum reference current value according to the gear of the reference current value;

step S420, shifting the median gear according to a preset shifting rule;

in step S430, the obtained reference current value is shifted as an optimal reference current value.

Determining a median gear according to the minimum reference current value and the maximum reference current value, wherein the median gear can be the average of the minimum reference current value and the maximum reference current value, and can also be a gear at a middle position selected according to gear distribution; after the median gear is selected, adjusting the gears according to a preset offset rule, for example, when 20-gear reference current values from small to large are respectively 1mA, 2mA, 3mA, 4mA, … … and 20mA, when the minimum reference current value and the maximum reference current value are respectively 9mA and 14mA, and the median gear adopts the average of the minimum reference current value and the maximum reference current value, the median gear is 11.5mA, and in order to match with the initial set gear, the median gear is offset by 0.5mA and is rounded, and 11mA or 12mA is taken; or, when the minimum reference current value and the maximum reference current value are respectively 5 gears as follows: 10mA, 11mA, 12mA, 13mA and 14mA, then the 12mA in the middle can be used as the median gear, and the optimal reference current gear can be obtained by shifting by 1 mA. It is understood that the offset value may be any value including 0, and engineers may select a reasonable offset value according to the test condition, so that the shifted median value is closer to the actual optimal reference current value of the memory chip.

Referring to fig. 5, it can be understood that after the step S400 obtains the optimal reference current value, the method further includes:

step S500, receiving a reference current value curing instruction sent by a testing machine;

and S600, solidifying the optimal reference current value to a parameter configuration area of the memory chip according to the reference current value solidification instruction.

After determining the optimal reference current value of the memory chip, curing the optimal reference current value; when the current memory chip is determined to pass the test, the test machine receives the information that the memory chip passes the test, the test machine sends a reference current value curing instruction to the memory chip, after the memory chip receives the reference current value curing instruction, the calculated optimal reference current value is written into a parameter configuration area of the memory chip, and after that, the memory chip reads the optimal reference current value to set the memory chip at each power-on stage.

By the reference current determining method, different optimal reference currents can be determined for different memory chips, performance difference caused by fluctuation of a memory chip production process is made up, and reliability of the chips is improved. On the other hand, the determination of the optimal reference current is calculated in the memory chip, and the optimal reference current does not need to be calculated by the tester and then sent to the memory chip for solidification, so that the workload of the tester is reduced, and the reference current determination method is also suitable for testers with different performances.

The following describes an embodiment of the present invention with a practical example:

in the CP testing stage, the memory chip receives a test reference current instruction sent by the tester, where the format of the test reference current instruction is instruction code + check data selection code + minimum shift number, and the minimum shift number is used to provide a standard for judging whether the memory chip can pass the read operation check.

Referring to fig. 6, after receiving a test reference current instruction, the preprocessed memory chip generates a plurality of different reference current values through an internal circuit, the generated reference current values linearly change according to a magnitude relationship, and for each gear reference current value, a read operation and data verification are performed, that is, data is read according to the reference current value of the current gear, the read data is compared with verification data, and whether the reference current value of the current gear is suitable for the read operation is determined; if the current gear passes the verification, the reference current value of the current gear is not qualified, if the current gear passes the verification, the reference current value of the current gear is qualified, at the moment, the number of the gears is increased by one, if the reference current value of the current gear corresponds to the first-time verification, the minimum reference current value and the maximum reference current value are set as the reference current value of the current gear, and if the reference current value of the current gear corresponds to the second-time verification, the maximum reference current value is updated.

It will be appreciated that each time a first gear reference current value is tested, the next test is performed by incrementing the first gear until the reference current value reaches the highest first gear. When all the reference current values are tested, the gear number, the minimum reference current value and the maximum reference current value corresponding to the current memory chip can be obtained; and when the number of the gears is greater than or equal to the minimum number of the gears, considering the memory chip as the memory chip passes the specification, determining the optimal current value by adding an offset according to the median gear between the minimum reference current value and the maximum reference current value, and returning error information if the number of the gears is less than the minimum number of the gears.

After the optimal reference current value is determined, the memory chip returns a test result to the testing machine, and the testing machine returns a curing instruction to the memory chip after receiving the test result. And writing the optimal reference current value into a parameter configuration area of the memory chip after the memory chip receives the curing instruction.

The optimal reference current value is determined and solidified through the method, the setting can be performed on different memory chips, and compared with the traditional mode of setting the reference current in batches, the method and the device make up for the influence caused by the difference of production processes and improve the reliability of the memory chips under the reading operation.

The embodiment of the invention also provides a reference current determining device, which comprises at least one processor and a memory which is in communication connection with the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the aforementioned reference current determination method.

Referring to fig. 7, it is exemplified that the control processor 1001 and the memory 1002 in the device 1000 may be connected by a bus. The memory 1002, which is a non-transitory computer-readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer-executable programs. Further, the memory 1002 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk memory, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1002 may optionally include memory located remotely from the control processor 1001, which may be connected to the device 1000 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Those skilled in the art will appreciate that the arrangement of devices shown in fig. 7 is not intended to be limiting of the apparatus 1000 and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.

Also provided is a computer-readable storage medium storing computer-executable instructions, which are executed by one or more control processors, for example, by one control processor 1001 in fig. 7, and which may cause the one or more control processors to execute the reference current determination method in the above-described method embodiment, for example, to execute the above-described method steps S100 to S400 in fig. 1, method steps S310 to S320 in fig. 2, method steps S330 to S350 in fig. 3, method steps S410 to S430 in fig. 4, and method steps S500 to S600 in fig. 5.

The above-described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may also be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.