1. A method for improving flash memory programming efficiency is characterized by comprising the following steps:

receiving a programming instruction and data information needing to be programmed, and caching the data information needing to be programmed;

reading the programming data in the cache;

switching a voltage applied to an address line in a flash to a low voltage, and performing address switching in the flash according to the program data;

verifying the programming data, and recording an address to be programmed in the flash according to a verification result;

judging whether the data information needing to be programmed is read completely,

if yes, skipping to reading the programming data in the cache;

and if not, executing programming operation on the address needing to be programmed in the flash.

2. The method of claim 1, wherein the data information to be programmed comprises an address to be programmed and data to be programmed.

3. The method according to claim 1, wherein the data information to be programmed is buffered by the following steps: and respectively caching the data information needing to be programmed in at least one data latch in the flash according to the data width.

4. The method of claim 1, wherein the address line is a bit line of a flash memory where an address is located.

5. The method according to claim 1, wherein verifying the programming data and recording an address to be programmed in the flash memory according to a verification result comprises the following steps: reading data of an address corresponding to the programming data in the flash; and comparing the data of the address corresponding to the inside of the flash with the programming data, and obtaining and recording the address needing programming in the flash according to the comparison.

6. The method according to claim 3, wherein skipping to reading the program data in the buffer memory comprises the following steps: if yes, add 1 to the address in the data latch and go to read the programmed data in the buffer.

7. An apparatus for improving flash memory programming efficiency, comprising:

the receiving module is used for receiving a programming instruction and data information needing to be programmed and caching the data information needing to be programmed;

the reading module is used for reading the programming data in the cache;

the address switching module switches the voltage applied to an address line in the flash into low voltage and performs address switching in the flash according to the programming data;

the data verification module is used for verifying the programming data and recording an address needing programming in the flash according to a verification result;

the judging module is used for judging whether the data information needing to be programmed is read completely;

the skip module skips to read the programming data in the cache;

and the programming module is used for executing programming operation on the address which needs to be programmed in the flash.

8. The apparatus of claim 7, further comprising an address accumulator for accumulating addresses of the data latches, wherein after verifying the last latched data, the address accumulator adds 1 to the address of the data latch and reads the next latched data.

9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 6.

10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 6 by calling the computer program stored in the memory.

Background

As shown in FIG. 1, for the Nor flash programming process, a programming command and data are received, then the data are verified and the address required to be programmed is recorded, and then programming is performed.

In the prior art, in order to ensure normal operation of a device, when different addresses are switched, the voltage of an address line needs to be switched from high voltage to low voltage, after the address is switched, the voltage of the address line is increased again, then data verification is performed, when the address needing programming is verified, the address is programmed, and after the programming is completed, the voltage of the address line is switched to low voltage to perform address switching. Or if the address needing programming cannot be verified, the voltage of the address line is switched to be low voltage for address switching, and the operation is continuously circulated until the programming operation of all data is completed, and the cyclic charge-discharge process caused by the voltage boosting and the voltage reduction of the address line directly influences the programming efficiency.

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

The invention aims to provide a method, a device, a storage medium and a terminal for improving the programming efficiency of a flash memory, and aims to solve the problem that the programming efficiency is directly influenced by the continuous cyclic charge and discharge process in the existing programming process.

The technical scheme of the invention is as follows: the technical scheme provides a method for improving the programming efficiency of a flash memory, which specifically comprises the following processes:

receiving a programming instruction and data information needing to be programmed, and caching the data information needing to be programmed;

reading the programming data in the cache;

switching a voltage applied to an address line in a flash to a low voltage, and performing address switching in the flash according to the program data;

verifying the programming data, and recording an address to be programmed in the flash according to a verification result;

judging whether the data information needing to be programmed is read completely,

if yes, skipping to reading the programming data in the cache;

and if not, executing programming operation on the address needing to be programmed in the flash.

In the technical scheme, the voltage applied to an address line is switched to low voltage, then verification of all data needing to be programmed is traversed, an address needing to be programmed in the flash is found after the verification is finished, and then programming operation is executed on the address needing to be programmed in the flash; the addresses which do not need to be programmed in the flash do not need to be subjected to voltage rising and falling switching, so that the programming efficiency is improved.

Further, the data information to be programmed includes an address to be programmed and data to be programmed.

Further, the data information to be programmed is cached, and the specific process is as follows: and respectively caching the data information needing to be programmed in at least one data latch in the flash according to the data width.

Further, the address line is a bit line where an address in the flash is located.

Further, verifying the programming data, and recording an address to be programmed in the flash according to a verification result, specifically comprising the following processes: reading data of an address corresponding to the programming data in the flash; and comparing the data of the address corresponding to the inside of the flash with the programming data, and obtaining and recording the address needing programming in the flash according to the comparison.

Further, if yes, jumping to reading the programming data in the cache specifically includes the following steps: if yes, add 1 to the address in the data latch and go to read the programmed data in the buffer.

This technical scheme still provides a device for improving flash memory programming efficiency, includes:

the receiving module is used for receiving a programming instruction and data information needing to be programmed and caching the data information needing to be programmed;

the reading module is used for reading the programming data in the cache;

the address switching module switches the voltage applied to an address line in the flash into low voltage and performs address switching in the flash according to the programming data;

the data verification module is used for verifying the programming data and recording an address needing programming in the flash according to a verification result;

the judging module is used for judging whether the data information needing to be programmed is read completely;

the skip module skips to read the programming data in the cache;

and the programming module is used for executing programming operation on the address which needs to be programmed in the flash.

The data latch further comprises an address accumulator for accumulating the address of the data latch, and after the verification of the last latched data is completed, the address accumulator adds 1 to the address of the data latch and then reads the next latched data.

The present invention also provides a storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute any one of the methods described above.

The technical solution also provides a terminal, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used for executing any one of the methods by calling the computer program stored in the memory.

According to the method, the voltage applied to the address line is switched to low voltage, then verification of all data needing to be programmed is traversed, the address needing to be programmed in the flash is found after the verification is finished, then the voltage applied to the address line is switched to high voltage, and programming operation is carried out on the address needing to be programmed in the flash; although the programming operation is carried out on different addresses needing programming in the flash, the switching among the different addresses is also needed, and a cyclic charge and discharge process caused by the boosting and the voltage reduction of an address line still exists, the voltage rising and falling switching is not needed for the addresses needing no programming in the flash, so that the programming efficiency is improved, and when the quantity of data needing programming is large enough, the improvement effect of the programming efficiency is very obvious.

Drawings

FIG. 1 is a diagram illustrating a programming process of a Nor flash in the prior art.

FIG. 2 is a flow chart of steps of a method for improving flash memory programming efficiency according to the present invention.

FIG. 3 is a schematic diagram of an apparatus for improving flash programming efficiency according to the present invention.

Fig. 4 is a schematic diagram of a terminal in the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 2, a method for improving flash memory programming efficiency specifically includes the following steps:

s1: receiving a programming instruction and data information needing to be programmed, and caching the data information needing to be programmed.

Wherein the data information needing to be programmed comprises an address needing to be programmed and programmed data.

And the data information needing to be programmed is respectively cached in at least one data latch in the flash according to the data width.

S2: and reading the programming data in the buffer.

After the verification of the last latched data is completed each time, the address accumulation of the data latch is enabled, the next latched data is read, and a new round of verification is started.

S3: and switching a voltage applied to an address line in the flash to a low voltage, and performing address switching in the flash according to the program data.

The address line is a bit line where the address in the flash is located.

S4: verifying the programming data, and recording the address to be programmed in the flash according to the verification result.

Wherein, the S4 specifically includes the following processes:

s 41: reading data of an address corresponding to the programming data in the flash;

s 42: and comparing the data of the address corresponding to the inside of the flash with the programming data, and obtaining and recording the address needing programming in the flash according to the comparison.

If the data of the address corresponding to the programming data in the flash is 0, the address corresponding to the flash does not need to be programmed. If the data of the address corresponding to the programming data in the flash is 1 and the data information needing to be programmed is 0, the address corresponding to the flash in the flash needs to be programmed; if the data information to be programmed is 1, the corresponding address in the flash does not need to be programmed.

S5: and judging whether the data information needing to be programmed is read completely, if so, jumping to S6, and otherwise, jumping to S2.

After the last latched data is verified, if the cached programming data is not verified, the latched data of the next address is continuously verified until all the latched data are verified

S6: and executing a programming operation on the address needing to be programmed in the flash.

In the prior art, the voltage of an address line is switched from high voltage to low voltage, after the address is switched, the voltage of the address line is switched from low voltage to high voltage, then data verification is performed, whether programming operation is performed or not is determined according to a verification result, and after the programming operation is completed, the voltage of the address line is switched to low voltage to perform the address switching (namely, the address boosting and voltage dropping process can be performed regardless of whether the address in a flash needs to be programmed or not). In the technical scheme, firstly, the voltage applied to the address line is switched to low voltage, then verification of all data needing to be programmed is traversed, the address needing to be programmed in the flash is found after the verification is finished, then the voltage applied to the address line is switched to high voltage, and programming operation is carried out on the address needing to be programmed in the flash; although the programming operation is carried out on different addresses needing programming in the flash, the switching among the different addresses is also needed, and a cyclic charge and discharge process caused by the boosting and the voltage reduction of an address line still exists, the voltage rising and falling switching is not needed for the addresses needing no programming in the flash, so that the programming efficiency is improved, and when the quantity of data needing programming is large enough, the improvement effect of the programming efficiency is very obvious.

As shown in fig. 3, an apparatus for improving flash memory programming efficiency includes:

the receiving module 101 is used for receiving a programming instruction and data information needing to be programmed and caching the data information needing to be programmed;

the reading module 102 is used for reading the programming data in the cache;

an address switching module 103 for switching a voltage applied to an address line in the flash to a low voltage and performing address switching in the flash according to the program data;

the data verification module 104 is used for verifying the programming data and recording an address which needs to be programmed in the flash according to a verification result;

the judging module 105 judges whether the data information needing to be programmed is read completely;

the jump module 106 jumps to reading the programming data in the cache;

and the programming module 107 is used for executing programming operation on the address needing to be programmed in the flash.

In some embodiments, the apparatus for improving programming efficiency of a flash memory further includes an address accumulator 108 for accumulating addresses of the data latches, and after verifying the last latched data, the address accumulator 108 increments the address of the data latch by 1 and reads the next latched data.

Referring to fig. 4, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.

In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: receiving a programming instruction and data information needing to be programmed, and caching the data information needing to be programmed; reading the programming data in the cache; switching a voltage applied to an address line in a flash to a low voltage, and performing address switching in the flash according to the program data; verifying the programming data, and recording an address to be programmed in the flash according to a verification result; judging whether the data information needing to be programmed is read completely, if so, skipping to reading the programming data in the cache; and if not, executing programming operation on the address needing to be programmed in the flash.

Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.

An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: receiving a programming instruction and data information needing to be programmed, and caching the data information needing to be programmed; reading the programming data in the cache; switching a voltage applied to an address line in a flash to a low voltage, and performing address switching in the flash according to the program data; verifying the programming data, and recording an address to be programmed in the flash according to a verification result; judging whether the data information needing to be programmed is read completely, if so, skipping to reading the programming data in the cache; and if not, executing programming operation on the address needing to be programmed in the flash. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.