1. A display panel, comprising: the display panel comprises a data line, a panel bump module and a driving integrated circuit;

the panel bump module comprises a first row of bumps and a second row of bumps, the first row of bumps comprise pins with the same number as the output ends of the driving integrated circuit, and the second row of bumps comprise pins connected with the data lines in a one-to-one correspondence manner;

when the pins of the first row of bumps are correspondingly bound and connected with the output ends of the driving integrated circuit one by one, the pins of the second row of bumps are configured as data transmission lines of the first row of bumps, and the data transmission lines are used for transmitting driving signals provided by the driving integrated circuit to correspondingly connected data lines;

and when the pins of the second row of bumps are bound and connected with the output end of the driving integrated circuit, the pins of the second row of bumps are used for transmitting the driving signals provided by the driving integrated circuit to the correspondingly connected data lines.

2. The display panel according to claim 1, wherein the number of pins of the second row of bumps is N times the number of pins of the first row of bumps, and N is an integer greater than one.

3. The display panel of claim 1, wherein the panel bump module further comprises: a switching element;

one end of the switch element is connected with the pins of the first row of bumps, and the other end of the switch element is connected with the pins of the second row of bumps.

4. The display panel according to claim 3, wherein the number of the switching elements is the same as the number of pins of the first row of bumps.

5. The display panel according to claim 3, wherein the number of the switching elements is the same as the number of the pins of the second row of bumps.

6. The display panel according to any one of claims 3 to 5, wherein the switching element is a diode, an anode of the diode is connected to the pin of the first row of bumps, and a cathode of the diode is connected to the pin of the second row of bumps.

7. The display panel according to any one of claims 3 to 5, wherein the switching element is a thin film transistor, a first pole of the thin film transistor is connected to the lead of the first row of bumps, and a second pole of the thin film transistor is connected to the lead of the second row of bumps.

8. The display panel of claim 1, wherein the second row of bumps has a larger number of pins than the first row of bumps.

9. A method for manufacturing a display panel according to any one of claims 1 to 8, comprising;

when the panel salient points are led out, two rows of salient points are arranged to form a panel salient point module, the panel salient point module comprises a first row of salient points and a second row of salient points, the first row of salient points comprise pins with the same number as the output ends of the driving integrated circuit, and the second row of salient points comprise pins which are correspondingly connected with the data lines one by one;

when the pins of the first row of bumps are in one-to-one corresponding binding connection with the output ends of the driving integrated circuit, gluing the second row of bumps to configure the pins of the second row of bumps into data transmission lines of the first row of bumps, wherein the data transmission lines are used for transmitting driving signals provided by the driving integrated circuit to correspondingly connected data lines;

and when the pins of the second row of salient points are bound and connected with the output end of the drive integrated circuit, gluing the first row of salient points.

10. A display device, comprising: a display panel as claimed in any one of claims 1 to 8.

Background

Currently, a data driving chip in a display outputs a pixel voltage to a pixel unit through a data line. Because the number of data lines in the display is large, correspondingly, the number of pins needed by the data driving chip is large, so that the number of data transmission lines for transmitting data signals to each data line is large, and the display is not beneficial to realizing a narrow frame of the display.

In order to implement a Full-screen, by reducing the number of data transmission lines, a multiplexing (Mux) signal input Circuit is provided between a data driving chip and a data line in the related art, so that the data driving chip can connect two or more sub-pixel units through a Mux, in the case of an existing display panel design, a case where one Driver Integrated Circuit (DIC) output Channel (Source Channel) drives a plurality of data lines sources on a panel, such as a case of Muxs1:2 or other Mux1: n, where n is an integer greater than 2, occurs, for example, in the current Full High Definition (FHD) display drive, Mux1:2 drive is commonly used, i.e., one Mux Circuit corresponds to two data lines, the number of sources output by the DIC is 1/2 of the number of panel sources, if the display drive uses Mux1:1 or other Mux1: n, the display panel needs to be redesigned, increasing the design cost.

Disclosure of Invention

In view of the above, in order to solve the technical problems or some of the technical problems, embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device.

In a first aspect, an embodiment of the present application provides a display panel, including: the display panel comprises a data line, a panel bump module and a driving integrated circuit;

the panel bump module comprises a first row of bumps and a second row of bumps, the first row of bumps comprise pins with the same number as the output ends of the driving integrated circuit, and the second row of bumps comprise pins connected with the data lines in a one-to-one correspondence manner;

when the pins of the first row of bumps are correspondingly bound and connected with the output ends of the driving integrated circuit one by one, the pins of the second row of bumps are configured as data transmission lines of the first row of bumps, and the data transmission lines are used for transmitting driving signals provided by the driving integrated circuit to correspondingly connected data lines;

and when the pins of the second row of bumps are bound and connected with the output end of the driving integrated circuit, the pins of the second row of bumps are used for transmitting the driving signals provided by the driving integrated circuit to the correspondingly connected data lines.

In a possible implementation manner, the number of pins of the second row of bumps is N times of the number of pins of the first row of bumps, and N is an integer greater than one.

In one possible embodiment, the panel bump module further includes: a switching element; one end of the switch element is connected with the pins of the first row of bumps, and the other end of the switch element is connected with the pins of the second row of bumps.

In a possible embodiment, the number of the switching elements is the same as the number of the pins of the first row of bumps.

In a possible embodiment, the number of the switching elements is the same as the number of the pins of the second row of bumps.

In a possible embodiment, the switching element is a diode, an anode of the diode is connected to the pin of the first row of bumps, and a cathode of the diode is connected to the pin of the second row of bumps.

In a possible implementation manner, the switching element is a thin film transistor, a first pole of the thin film transistor is connected to the pins of the first row of bumps, and a second pole of the thin film transistor is connected to the pins of the second row of bumps.

In a possible implementation, the number of pins of the second row of bumps is greater than the number of pins of the first row of bumps.

In a second aspect, an embodiment of the present application provides a method for manufacturing a display panel, where the display panel is the display panel according to the first aspect, the method includes;

when the panel salient points are led out, two rows of salient points are arranged to form a panel salient point module, the panel salient point module comprises a first row of salient points and a second row of salient points, the first row of salient points comprise pins with the same number as the output ends of the driving integrated circuit, and the second row of salient points comprise pins which are correspondingly connected with the data lines one by one;

when the pins of the first row of bumps are in one-to-one corresponding binding connection with the output ends of the driving integrated circuit, gluing the second row of bumps to configure the pins of the second row of bumps into data transmission lines of the first row of bumps, wherein the data transmission lines are used for transmitting driving signals provided by the driving integrated circuit to correspondingly connected data lines;

and when the pins of the second row of salient points are bound and connected with the output end of the drive integrated circuit, gluing the first row of salient points.

In a third aspect, an embodiment of the present application provides a display device, including: a display panel as described in the first aspect above.

According to the display panel, the manufacturing method and the display device, when pins of the first row of bumps are correspondingly bound and connected with output ends of the driving integrated circuit one by one, the pins of the second row of bumps are configured into data transmission lines of the first row of bumps, so that driving signals provided by the driving integrated circuit are transmitted to the correspondingly connected data lines; and when the pins of the second row of salient points are bound and connected with the output end of the drive integrated circuit, the drive signals provided by the drive integrated circuit are transmitted to the correspondingly connected data lines through the pins of the second row of salient points, so that the display panel can be suitable for different DIC application scenes, the compatibility of the display panel is improved, the cost of newly opening a Mask plate (Mask) is saved, and the cost is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a panel bump module according to an alternative example of the present application;

fig. 3 is a schematic structural diagram of another panel bump module according to an alternative example of the present application;

fig. 4 is a schematic step diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

For the purpose of facilitating understanding of the embodiments of the present application, the following description will be made in terms of specific embodiments with reference to the accompanying drawings, which are not intended to limit the embodiments of the present application.

Fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of the present application, where the display panel includes: a data line 110, a panel Bump (Bump) module 120, and a driving integrated circuit 130.

The panel Bump module 120 includes a first row of Bump bumps 1 and a second row of Bump bumps 2, the first row of Bump1 includes the same number of pins as the number of output terminals of the driving ic 130, and the second row of Bump bumps 2 includes pins connected to the data lines 110 in a one-to-one correspondence.

For example, when the number of the output terminals of the driving integrated circuit 130 is m1 and the number of the data lines 110 is m2, the first row of Bump bumps 1 is provided with m1 pins, so that the Mux1:1 driving is realized by subsequently binding the driving integrated circuit 130 with the first row of Bump bumps Bump 1; the Bump2 in the second row is provided with m2 pins, so that the Mux1: N driving is realized by binding the driving integrated circuit 130 with the Bump2 in the second row. M1 and m2 are integers greater than zero; n may be an integer greater than 1, for example, N may be 2, 3, or the like.

Specifically, when the pins of the first row of Bump bumps Bump1 are correspondingly bonded to the output terminals of the driving integrated circuit 130, the pins of the second row of Bump bumps Bump2 are configured as data transmission lines of the first row of Bump bumps Bump1, and the data transmission lines are used for transmitting the driving signals provided by the driving integrated circuit 130 to the correspondingly connected data lines 110. For example, when the first row of Bump bumps 1 is used, the DIC is bound with the first row of Bump bumps 1, in combination with the above example, each pin of the first row of Bump bumps 1 is bound and connected with the output terminal of the driving integrated circuit 130 in a one-to-one correspondence manner, for example, the 1 st pin of the first row of Bump1 is bound and connected with the 1 st output terminal of the driving integrated circuit 130 in a corresponding manner, the 2 nd pin of the first row of Bump1 is bound and connected with the 2 nd output terminal of the driving integrated circuit 130 in a corresponding manner, the 3 rd pin of the first row of Bump1 is bound and connected with the 3 rd output terminal of the driving integrated circuit 130 in a corresponding manner … …, and so on, the m1 th pin of the first row of Bump1 is bound and connected with the m1 th output terminal of the driving integrated circuit 130 in a corresponding manner; and, the pins of the second row of bumps Bump2 may be configured as data transmission lines of the first row of bumps Bump1, so as to transmit the driving signals provided by the driving integrated circuit 130 to the correspondingly connected data lines 110 through the pins of the second row of bumps Bump2, that is, the pins Pad of the second row of bumps Bump2 may be used as wires on the Source lines of the first row of bumps Bump1 and are directly connected to the Source lines of the panel, so as to implement the use of the Mux1: 1.

When the pins of the second Bump bank 2 are connected to the output terminals of the driving ic 130, the pins of the second Bump bank 2 are used to transmit the driving signal provided by the driving ic 130 to the corresponding connected data lines 110. For example, when the second row of bumps Bump2 is used, the DIC is bound to the second row of bumps Bump2, each pin of the second row of bumps Bump2 is bound to the output terminal of the driving ic 130, for example, the 1 st and 2 nd pins of the second row of bumps Bump2 are bound to the 1 st output terminal of the driving ic 130, the 3 rd and 4 th pins of the second row of bumps Bump2 are bound to the 2 nd output terminal of the driving ic 130, the 5 th and 6 th pins of the second row of bumps Bump2 are bound to the 3 rd output terminal of the driving ic 130, and so on, the (2 m1-1) and 2 m1 th pins of the second row of bumps Bump2 are bound to the m1 th output terminal of the driving ic 130, so that the driving signal provided by the driving ic 130 can be transmitted to the data line 110 connected to the corresponding Bump through the pins of the second row of bumps 2, the use of Mux1:2 is achieved.

As can be seen, the display panel provided in the example of the present application includes: the data line 110, the panel Bump module 120 and the driving integrated circuit 130, wherein the panel Bump module 120 includes a first row of Bump bumps 1 and a second row of Bump bumps 2, when pins of the first row of Bump bumps 1 are in one-to-one corresponding binding connection with output terminals of the driving integrated circuit 130, the pins of the second row of Bump bumps 2 are configured as data transmission lines of the first row of Bump bumps bum 1, so that driving signals provided by the driving integrated circuit 130 are transmitted to the correspondingly connected data line 110 through the data transmission lines (i.e., the pins of the second row of Bump2), and the use of Mux1:1 is realized; when the pins of the second row of Bump bumps, namely the Bump2, are bound and connected with the output end of the driving integrated circuit 130, the driving signal provided by the driving integrated circuit 130 is transmitted to the correspondingly connected data line 110 through the pins of the second row of Bump bumps, namely the Bump2, so that the use of Mux1: N is realized, the display panel can be suitable for different DIC application scenes, the compatibility of the display panel is improved, the cost of developing a Mask is saved, and the cost is reduced.

In actual processing, one DIC Source Channel may drive one or more data line sources on the panel. In case of multiple data lines Source on one DIC Source Channel driver panel, the number of data lines may be larger than the number of outputs of the driver ic, e.g. in connection with the above example, the number of outputs m1 of the driver ic is smaller than the number of data lines m2, i.e. m1< m 2. Therefore, in an alternative embodiment of the present application, the number of pins of the second row of bumps Bump2 may be greater than the number of pins of the first row. Further, the number of pins of the second row of bumps Bump2 is N times the number of pins of the first row of bumps Bump1, where N is an integer greater than one. When the DIC is bound with the second row of Bump bumps 2, every N pins of the second row of Bump bumps Bump2 can be used as a group and bound and connected with the same output end of the DIC, that is, one output end of the DIC can be connected with N pins of the second row of Bump2, so that one DIC Source Channel can drive N data lines sources on the panel, and the use of Mux1: N is realized.

On the basis of the above embodiments, optionally, the panel bump module 120 in the embodiment of the present application further includes: a switching element K; one end of the switch element K is connected to a pin of the first row Bump1, and the other end of the switch element K is connected to a pin of the second row Bump 2. When the pins of the first row of Bump bumps Bump1 are correspondingly and fixedly connected with the output terminals of the driving integrated circuit 130, that is, when the first row of Bump bumps Bump1 is used, the switching element K is in a conducting state, so that the driving signal received by the pins of the first row of Bump1 can be transmitted to the pins of the second row of Bump2 through the conducting switching element K, so that the driving signal can be transmitted to the correspondingly connected data lines 110 through the pins of the second row of Bump2, and Mux1:1 driving is realized. When the pins of the second row of Bump bumps Bump2 are bound and connected with the output terminals of the driving integrated circuit 130, that is, when the second row of Bump bumps Bump2 is used, the switching element K is in an off state, so that the driving signal received by the pins of the second row of Bump2 is not transmitted to the pins of the first row of Bump1 through the switching element K, but is transmitted to the data lines 110 correspondingly connected to the pins of the second row of Bump2, so that one DIC Source Channel can drive N data lines 110 sources on the panel, and Mux1: N driving is realized.

In an alternative embodiment, each pin of the first row Bump1 may be connected to a pin of the second row Bump2 through a switch element K, that is, the number of the switch elements K in the embodiment of the present application may be the same as the number of the pins of the first row Bump 1. For example, each pin of the first row of Bump1 may be connected to two pins of the second row of Bump2 through a switch element K, one end of each switch element K is connected to 1 pin of the first row of Bump1, and the other end is connected to two pins of the second row of Bump 2. Of course, each pin of the first row Bump1 may also be connected to a plurality of pins of the second row Bump2 through a switch element K, for example, 3 or 4 pins of the second row Bump2 may be connected through the switch element K, and the embodiment of the present application is not limited in particular.

In another alternative embodiment, each pin of the second row of bumps Bump2 may be connected to a pin of the first row of bumps Bump1 through a switch element K, that is, the number of the switch elements K is the same as that of the pins of the second row of bumps Bump 2. For example, in the case where every two pins of the second row Bump2 are connected to 1 pin of the first row Bump1 as a group, as shown in fig. 2, each pin of the first row Bump1 may be connected to two pins of the second row Bump2 through a switching element K connected in one-to-one correspondence with the pin of the second row Bump 2. One end of the switching element K may be connected to 1 pin of the first row of bumps Bump1, and the other end of the switching element K may be connected to 1 pin of the second row of bumps Bump 2.

In a specific implementation, the switching element K may be a diode, a triode, an Oxide Thin Film Transistor (OTFT), or the like, which is not particularly limited in the embodiments of the present application.

In an alternative embodiment, the switching element K is a diode, an anode of the diode is connected to the pin of the first row Bump1, and a cathode of the diode is connected to the pin of the second row Bump 2.

As an alternative example of the present application, as shown in fig. 3, a pin of the first row of bumps Bump1 is connected to an anode of a diode, and a pin of the second row of bumps Bump2 is connected to a cathode of the diode.

When the first row of Bump bumps 1 is used, the DIC is bound to the first row of Bump bumps 1, that is, the output end of the driver ic 130 is connected to the pins of the first row of Bump bumps 1 in a one-to-one correspondence; the second row of bumps Bump2 is subjected to gluing, that is, the pins of the second row of bumps Bump2 are subjected to gluing, so that the pins of the second row of bumps Bump2 are sealed in a gluing mode, and the pins of the second row of bumps Bump2 are insulated. In the process that the DIC Source module provides a driving voltage for the Channel Source Channel, that is, when the driving integrated circuit 130 outputs a driving voltage signal, the driving voltage signal may be used as a driving signal, and transmitted to the pin of the first row of Bump1 bound to the output terminal of the driving integrated circuit 130 through the Channel Source Channel, so that the pin of the first row of Bump1 may be transmitted to the anode of the diode, and the diode is turned on, so that the pin Pad of the second row of Bump2 is used as a lead on the first row of Bump1 Source line, and the driving signal is directly connected to the Source line of the panel, thereby implementing the use of Mux1: 1.

When the second row of Bump bumps 2 is used, the DIC and the second row of Bump bumps Bump2 are bound, that is, one output Source of the driver ic 130 is bound and connected with two pins of the second row of Bump bumps Bump 2; the first row of bumps Bump1 is subjected to gluing treatment, namely, the pins of the first row of bumps Bump1 are subjected to gluing treatment, so that the pins of the first row of bumps Bump1 are sealed in a gluing manner, and insulation treatment is realized. When the DIC Source module provides a driving voltage, that is, when the driving integrated circuit 130 outputs a driving voltage signal, the driving voltage signal may be transmitted as a driving signal to a pin of the second row of Bump2 bound to an output terminal of the driving integrated circuit 130 through a Channel Source Channel, and then transmitted to a cathode of the diode, and since the diode is in a reverse cut-off state, the first row of Bump1 is not turned on, thereby implementing Mux1:2 driving.

In another alternative implementation, the switching element K in the embodiment of the present application is a Thin Film Transistor (TFT), a first pole of the TFT is connected to a pin of the first row of bumps Bump1, and a second pole of the TFT is connected to a pin of the second row of bumps Bump 2. Alternatively, the gate of the thin film transistor may be connected to the driving control terminal, so that the thin film transistor is turned on when the output terminal of the driving integrated circuit 130 is connected to the pin bonding of the first row of bumps Bump1 and is turned off when the output terminal of the driving integrated circuit 130 is connected to the pin bonding of the second row of bumps Bump2 under the control of the driving control terminal. The driving control end is configured to output a driving control signal, for example, when the output end of the driving integrated circuit 130 is bound and connected with the pins of the first row of bumps Bump1, an effective driving control signal is output to the gate of the thin film transistor, so that the thin film transistor is turned on according to the effective driving control signal, and further, the driving signal received by the pins of the first row of bumps Bump1 can be transmitted to the pins of the second Bump through the turned-on thin film transistor, so as to be transmitted to the correspondingly connected data line 110 through the pins of the second Bump, thereby implementing Mux1:1 driving; when the output end of the driving integrated circuit 130 is bound and connected with the pins of the second row of bumps Bump2, an invalid driving control signal is output to the gate of the thin film transistor, so that the thin film transistor is disconnected according to the invalid driving control signal, and thus the driving signal received by the pins of the second row of bumps Bump2 is not transmitted to the pins of the first row of bumps Bump1 through the disconnected thin film transistor, and Mux1: N driving is realized.

Of course, the gates of the thin film transistors in the embodiment of the present application may also adopt other connection manners, for example, the gate of each thin film transistor may be connected to the first pole or the second pole of the same thin film transistor, which is not limited in this embodiment.

In practical implementation, the first pole and the second pole of the transistor in this embodiment may be the source or the drain of the transistor, and their functions may be interchanged according to the type of the transistor and the input signal, and are not specifically distinguished herein.

As an example of the present application, when the switching element K is an N-type thin film transistor, and a gate and a first pole of the thin film transistor may be connected to a pin of the first row of Bump1, and a second pole of the thin film transistor is connected to a pin of the second row of Bump2, the thin film transistor may be turned on when the pin of the first row of Bump1 receives a driving signal output by the driving integrated circuit 130, and turned off when the pin of the second row of Bump2 is bound and connected to an output end of the driving integrated circuit 130, that is, the thin film transistor may not be turned on when the pin of the second row of Bump2 receives the driving signal output by the driving integrated circuit, and further the driving signal may not be transmitted to the pin of the first row of Bump1 through the thin film transistor, so that the display panel may be compatible with different DIC application scenarios, improve compatibility of the display panel, and save cost of new development Mask.

Of course, the switching element K may also be a P-type thin film transistor, which is not particularly limited in the embodiments of the present application. For example, when the switching element K is a P-type thin film transistor, and a first pole of the thin film transistor may be connected to a pin of the first row of Bump1, and a gate and a second pole of the thin film transistor are connected to a pin of the second row of Bump2, if the pin of the first row of Bump1 is bound to an output terminal of the driving integrated circuit 130, the thin film transistor is turned on when the pin of the first row of Bump1 receives a driving signal output by the driving integrated circuit 130; if the pins of the second row of Bump bumps 2 are bound and connected with the output end of the driving integrated circuit 130, the thin film transistor is disconnected, that is, the thin film transistor receives a driving signal output by the driving integration at the pins of the second row of Bump bumps Bump2 and is not turned on, and further the driving signal is not transmitted to the pins of the first row of Bump bumps Bump1 through the thin film transistor, so that the display panel can be compatible with different DIC application scenes, the compatibility of the display panel is improved, and the cost of newly developing a Mask is saved.

Further, an embodiment of the present application further provides a method for manufacturing a display panel, which is used for manufacturing the display device of the display panel according to any one of the above embodiments. As shown in fig. 4, a method for manufacturing a display panel provided in the embodiment of the present application may specifically include:

s401, when the panel salient points are led out, two rows of salient points are arranged to form a panel salient point module, and the panel salient point module comprises a first row of salient points and a second row of salient points;

s402, when the pins of the first row of bumps are in one-to-one corresponding binding connection with the output end of the drive integrated circuit, gluing the second row of bumps to configure the pins of the second row of bumps into data transmission lines of the first row of bumps, wherein the data transmission lines are used for transmitting drive signals provided by the drive integrated circuit to correspondingly connected data lines;

and S403, when the pins of the second row of bumps are bound and connected with the output end of the drive integrated circuit, gluing the first row of bumps.

The first row of salient points comprise pins with the same number as the output ends of the driving integrated circuit, and the second row of salient points comprise pins connected with the data lines in a one-to-one correspondence mode.

Specifically, when the panel Bump is led out, two rows of bumps can be designed on one panel and respectively correspond to Source Mux1:1 and Mux1: N (N is more than or equal to 2) use scenes. For example, the BP panel may be divided into two rows of bumps, which are respectively an upper row of bumps and a lower row of two layers of bumps, and may be labeled as a first row of Bump bumps 1 and a second row of Bump bumps 2, wherein the first row of Bump1 corresponds to the DIC case of Mux1:1, and the second row of Bump2 may correspond to the DIC case of Mux1: N.

In a specific implementation, the Bump1 in the first row of the two rows of bumps may be set to be Mux1:1Bump, and the Bump2 in the second row may be designed to be Mux1: N Bump.

For example, for the case of Mux1:2, pins of the first row of Bump bumps 1 and output terminals of the driver ic are bound and connected in a one-to-one correspondence manner, that is, 1 pin of the first row of Bump1 may be bound and connected in a correspondence manner with a 1 output terminal of the driver ic, so as to set the first row of Bump1 to be Mux1:1 Bump; and every 2 pins of the second row of Bump2 can be bound and connected with 1 output end of the driving integrated circuit, that is, the 1 output end of the driving integrated circuit can be connected with 2 pins of the second row of Bump2, so that the second row of Bump2 is designed to be Mux1: N Bump.

For another example, for the case of Mux1: M (M is greater than or equal to 3), pins of the first row Bump1 and output terminals of the driver ic may be bound and connected in a one-to-one correspondence manner, so as to set the first row Bump1 to be Mux1:1 Bump; and every M pins of the second row of Bump bumps, namely Bump2, can be bound and connected with 1 output terminal of the driving integrated circuit, so that the second row of Bump bumps, namely Bump2, is designed into Mux1: M bumps.

Therefore, in the embodiment of the application, when the panel Bump is led out, two rows of Bump (namely, the first row Bump1 and the second row Bump2 included in the panel Bump module 120) are arranged on one display panel and respectively correspond to Source Mux1:1 and Mux1: N (N is greater than or equal to 2) using scene bumps, so that the display panel can use both Mux1:1 and Mux1: N (N is greater than or equal to 2) DIC, the compatibility of the display panel is improved, and the design cost is reduced.

Further, an embodiment of the present invention further provides a display device, including: the display panel provided by the embodiment of the invention. As shown in fig. 5, the display device 500 includes: a display panel 510, wherein the display panel 510 may be the display panel described in the above embodiments. In a specific implementation, the display device may be a display, a mobile phone, a television, a notebook computer, electronic paper, a digital photo frame, a navigator, an all-in-one machine, and the like, which is not particularly limited in this application.

In summary, according to the display device in the embodiment of the application, two rows of bumps are arranged on one display panel by using the display panel in the embodiment, and the two rows of bumps respectively correspond to Source Mux1:1 and Mux1: N (N is greater than or equal to 2) using scene bumps, so that the display panel can use Mux1:1 and Mux1: NDIC, compatibility is improved, and design cost is reduced.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The above-mentioned embodiments, objects, technical solutions and advantages of the present application are described in further detail, it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present application, and are not intended to limit the scope of the present application, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present application should be included in the scope of the present application.