1. A synchronous system based on ATE chip test comprises a main control board, N service boards and a back board, wherein N is a positive integer; the service board communicates with the main control board through the back board; the main control board comprises a main control CPU and a main control FPGA, and is characterized in that the service board comprises a service board FPGA which comprises an FPGA chip test execution module; and the main program of the main control CPU sends the chip test program to the main control FPGA, and the main control FPGA sends the chip test program to the service FPGA chip test execution module.

2. The ATE chip test-based synchronization system of claim 1, wherein the master FPGA comprises an FPGA synchronization control module, the FPGA synchronization control module comprising a synchronization register and a synchronization controller; the synchronization register selects the input of the synchronization controller.

3. The ATE chip test-based synchronization system of claim 2, wherein the synchronization controller and the service board correspond to each other.

4. The ATE chip test-based synchronization system of claim 2, wherein the synchronization register is N bits, each bit controlling a service board.

5. The ATE chip test-based synchronization system of claim 2, wherein the synchronization controller comprises a NOT gate and an AND gate; the signal of the synchronous register is OR-ed with the chip test result of the service board through a NOT gate; and the obtained or obtained result is compared with the chip test results of other service boards.

6. The ATE chip test-based synchronization system of claim 2, wherein the master FPGA further comprises an FPGA communication management module, the FPGA communication management module being in communication with the backplane.

7. A method for synchronization based on ATE chip testing, comprising the synchronization system for ATE chip testing according to any one of claims 1-6,

the testing is started, the main control CPU sends a chip testing program to the main control FPGA, the main control FPGA sends the chip testing program to the service board, and the FPGA chip testing execution module on the service board synchronously starts testing;

testing operation, wherein the service board FPGA chip testing execution module performs operation of a testing program;

determining a chip test result, judging the chip test result by the FPGA chip test execution module of the service board, and setting a test result signal to be high if the chip test result is successful, or setting a test result signal to be low if the chip test result is not successful;

and the test results are synchronous, and the FPGA chip test execution module synchronizes the test results to the synchronous control module of the FPGA of the main control board through the back board.

8. The method of claim 7, further comprising analyzing the test results, wherein the master control board FPGA synchronizes the chip test results of the service boards and determines the chip test results of the plurality of service boards.

9. The method of claim 8, wherein the analysis of the test results is performed by taking or obtaining the result signals according to bits from the test result signals received by the FPGA of the main control board and a preset synchronous register, and determining whether the result signals are all at high level, and if so, the testing of the chip of the service board is successful; otherwise, the service board chip fails to test, and the test result is fed back to the corresponding service board FPGA.

10. The method for synchronizing ATE chip testing according to claim 7, wherein the chip testing program is a testing program with FPGA chip testing instructions; if the chip test result is successful, the service board FPGA continues to execute a subsequent chip test program; and if the chip test result fails, the service board FPGA feeds back the chip test result to the main program of the main control CPU.

Background

For ATE (Automatic Test Equipment): a large number of hardware components are integrated, a TMU component can replace an oscilloscope, and a PMU component can replace a multimeter and the like; compatible with a high-level language, and can realize automatic control through programming; any desired stimulus can be easily transmitted.

The chip testing efficiency is one of the important indexes of the ATE equipment, and in the chip testing process, if each test needs to collect and analyze the test program execution result in each service board, a large amount of time needs to be consumed, and the chip testing efficiency is greatly influenced.

For example, the patent name, a test method of MCU/SOC chip based on ATE; patent application No.: CN 201410708882.7; the application date is: 2014-11-28; the patent describes a testing method of MCU/SOC chip based on ATE, which uses ATE as basic platform and realizes reliable communication between ATE and other devices through self-defined communication protocol. After the test is started, the ATE sends an instruction 1 and an excitation 1 to the device to be tested through a protocol, automatically records test data 1, sends an instruction 2 and an excitation 2 to the device to be tested, and automatically records the test data 2 until all project tests are completed.

In the prior art, each test needs to acquire and analyze the execution result of the test program in each service board, so that a large amount of time needs to be consumed, and the test efficiency of the chip is greatly influenced.

Disclosure of Invention

Aiming at the defects that in the prior art, each test of an ATE chip needs to acquire and analyze the execution result of a test program in each service board, a large amount of time is consumed, and the test efficiency of the chip is influenced, the invention provides a synchronization method and a synchronization system based on the ATE chip test.

In order to solve the technical problem, the invention is solved by the following technical scheme:

a synchronous system based on ATE chip test comprises a main control board, N service boards and a back board, wherein N is a positive integer; the service board communicates with the main control board through the back board; the main control board comprises a main control CPU and a main control FPGA, the service board comprises a service board FPGA, the service board FPGA comprises an FPGA chip test execution module, a main program of the main control CPU sends a chip test program to the main control FPGA, and the main control FPGA sends the chip test program to the FPGA chip test execution module. The FPGA chip test execution module is arranged on the FPGA of the service board, and the chip test result judgment action is synchronously realized in the service board, so that the test efficiency of ATE chip test is improved, and the test cost is reduced.

Preferably, the main control FPGA comprises an FPGA synchronous control module, and the FPGA synchronous control module comprises a synchronous register and a synchronous controller; the synchronization register selects the input of the synchronization controller, i.e. the service board combination that needs to be synchronized.

The synchronous registers are arranged in the main control FPGA, so that the mutual synchronization of the test results of the plurality of service boards can be well realized, and the mutual synchronization of the test results of the plurality of service boards can be realized only by arranging the relevant synchronous registers before the test program runs.

Preferably, the synchronization controller and the service board correspond to each other. The synchronous controllers correspond to the service boards one by one, and the synchronism of the chip in the testing process can be well guaranteed.

Preferably, the synchronous register is N bits, and each 1bit controls one service board.

Preferably, the synchronous controller comprises a not gate and an and gate; the signal of the synchronous register is OR-ed with the chip test result of the service board through a NOT gate; and the OR result and the chip test result of the service board are obtained. The design of the synchronous controller can ensure the selectivity of testing the service boards when the service boards are tested, namely the service boards which are combined randomly are tested.

Preferably, the FPGA communication management module is in communication with the backplane.

A synchronization method based on ATE chip test comprises a synchronization system of the ATE chip test, the synchronization method is,

the testing is started, the main control CPU sends a chip testing program to the main control FPGA, the main control FPGA sends the chip testing program to the service board, and the FPGA chip testing execution module on the service board synchronously starts the chip testing;

testing and running, wherein an FPGA chip testing execution module of the service board FPGA runs a chip testing program;

determining a chip test result, judging the chip test result by an FPGA chip test execution module of the service board FPGA, and if the chip test result is successful, setting a chip test result signal to be high, otherwise, setting a chip test result signal to be low;

and the test results are synchronous, and the FPGA chip test execution module synchronizes the chip test results to the synchronous control module of the FPGA of the main control board.

Preferably, the method further comprises test result analysis, the main control board FPGA synchronizes the chip test results of the service boards, and determines the chip test results of the service boards.

Preferably, the test result analysis is performed, the test result signal received by the main control board FPGA and a preset synchronous register bit-wise fetch or obtain a result signal, whether the result signal is all high level or not is performed, and if the result signal is all high level, the service board chip is successfully tested; otherwise, the service board chip fails to test, and the test result is fed back to the corresponding service board FPGA.

Preferably, the test program is a test program with FPGA test instructions; if the chip test result is successful, the service board FPGA continues to execute a subsequent test program; and if the chip test result fails, the service board FPGA feeds back the chip test result to the main program of the main control CPU.

Due to the adoption of the technical scheme, the invention has the remarkable technical effects that:

by arranging the FPGA chip test execution module on the service board, the test result judgment action is synchronously realized in the service board, so that the chip test efficiency is improved, and the test cost is reduced.

The synchronous registers are arranged in the main control FPGA, so that the mutual synchronization of the test results of the plurality of service boards can be well realized, and the mutual synchronization of the test results of the plurality of service boards can be realized only by arranging the relevant synchronous registers before the test program runs. After each service card executes the chip test program, the test result is directly synchronized to the FPGA of the main control board in a physical connection mode, the main control board returns the synchronized chip test result to the FPGA of each service board in the physical connection mode, and the test program on the service boards acquires the test condition of the service boards in the whole test system according to the synchronized result, so that subsequent corresponding test actions are executed according to the test result.

The synchronization method of the invention can effectively save the time of the main control CPU for collecting the test data, and can more quickly finish the mutual synchronization of the test results between the service boards, the chip test time is short, and the chip test efficiency is high.

Drawings

FIG. 1 is a system diagram of the present invention.

Fig. 2 is a system diagram of the present invention.

Fig. 3 is a circuit diagram of the synchronous controller of the present invention.

FIG. 4 is a test flow diagram of the present invention.

FIG. 5 is a flow chart of testing of an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Example 1

A synchronous system based on ATE chip test comprises a main control board, N service boards and a back board, wherein N is a positive integer; the service board communicates with the main control board through the back board; the main control board comprises a main control CPU and a main control FPGA, the service board comprises a service board FPGA, and the service board FPGA comprises an FPGA chip test execution module; the main program of the main control CPU sends a chip test program to the main control FPGA, the main control FPGA sends the test program to the FPGA chip test execution module, and the main control FPGA sends the test program to the FPGA chip test execution module.

By arranging the FPGA chip test execution module on the FPGA of the service board, the test result judgment action is synchronously realized in the service board, so that the chip test efficiency is improved, and the test cost is reduced.

The main control board FPGA comprises an FPGA communication management module, and the FPGA communication management module is communicated with the back board. The back board connects the main control board and each service board together for communication through a high-speed interface; the backboard is connected with the main control board through the communication backboard connector. The main control board and each service board are provided with a physical connection line.

The main control FPGA comprises an FPGA synchronous control module, and the FPGA synchronous control module comprises a synchronous register and a synchronous controller; the synchronization register selects the input of the synchronization controller, i.e. the service board combination that needs to be synchronized.

The synchronous registers are arranged in the main control FPGA, so that the mutual synchronization of the test results of the plurality of service boards can be well realized, and the mutual synchronization of the test results of the plurality of service boards can be realized only by arranging the relevant synchronous registers before the test program runs.

The synchronous controller and the service board correspond to each other. The synchronous controllers correspond to the service boards one by one, and the synchronism of the chip in the testing process can be well guaranteed.

The synchronous controller comprises a NOT gate and an AND gate; the signal of the synchronous register is OR-ed with the chip test result of the service board through a NOT gate; and the OR result and the chip test result of the service board are obtained. The design of the synchronization controller can ensure the selectivity of the test service board.

According to the circuit diagram of the synchronous controller shown in fig. 3, the synchronous register has N bits, and 1 service board is controlled by every 1 bit. The 0 th bit register controls the corresponding service board 1, and the N-1 th bit register controls the corresponding service board N; each Bit represents that the service board is enabled synchronously with other service boards and is set to be high-effective. Here N is set to 16.

Example 2

A synchronization method based on ATE chip test, including a synchronization system for ATE chip test, as can be seen from fig. 4, the synchronization method is,

the testing is started, the main control CPU sends a chip testing program to the main control FPGA, the main control FPGA sends the chip testing program to the service board, and the FPGA chip testing execution module on the service board synchronously starts the chip testing;

testing and running, wherein an FPGA chip testing execution module of the service board FPGA runs a chip testing program;

determining a chip test result, judging the chip test result by an FPGA chip test execution module of the service board FPGA, and if the chip test result is successful, setting a chip test result signal to be high, otherwise, setting a chip test result signal to be low;

and the test results are synchronous, and the FPGA chip test execution module synchronizes the chip test results to the synchronous control module of the FPGA of the main control board.

Example 3

On the basis of the above embodiment, the embodiment further includes test result analysis, where the main control board FPGA synchronizes chip test results of the service boards, and determines chip test results of a plurality of service boards.

Analyzing the test result, namely taking or obtaining the result signal according to the bit by the test result signal received by the FPGA of the main control board and a preset synchronous register, judging whether the result signal is all high level, and if the result signal is all high level, successfully testing the service board chip; otherwise, the service board chip fails to test, and the test result is fed back to the corresponding service board FPGA.

The test program is a test program with FPGA chip test instructions; if the chip test result is successful, the service board FPGA continues to execute the subsequent test program; and if the chip test result fails, the service board FPGA feeds the test result back to the main program of the main control CPU.

Example 4

As can be seen from fig. 5, when testing a service board chip in the prior art, a main program of a main control CPU issues a test program to start testing, and after the service board receives the test, all service boards run the test program; judging that the query test of the master control CPU is finished, and acquiring test results of all service boards by the master control CPU when the query test of the master control CPU is finished; the master control CPU analyzes the test result; otherwise, the test program is re-run.