1. A high-accuracy FPGA online debugging method is characterized by comprising the following steps:

when debugging a user circuit, determining that a global circuit is composed of the user circuit and a monitoring circuit, wherein the monitoring circuit is connected with the user circuit;

generating a configuration code stream corresponding to the global circuit based on programmable logic resources inside the FPGA, wherein the configuration code stream comprises a first part which is generated based on first type resources and corresponds to the user circuit and a second part which is generated based on second type resources and corresponds to the monitoring circuit; the first type of resource and the second type of resource respectively represent programmable logic resources of different parts in the FPGA, the first type of resource is a programmable logic resource which is used for realizing the user circuit when the user circuit is not debugged in the FPGA, and the hardware structures of the programmable logic resources with the same resource type in the first type of resource and the second type of resource are the same;

and loading the configuration code stream onto the FPGA, wherein the FPGA forms a user circuit by utilizing a first class of resource based on a first part in the configuration code stream and forms a monitoring circuit by utilizing a second class of resource based on a second part in the configuration code stream, and the monitoring circuit samples a signal to be observed of the user circuit in the operation process of the user circuit and transmits the signal to the outside of the FPGA by utilizing a boundary scan chain built in the FPGA for monitoring and debugging.

2. The method according to claim 1, wherein the monitoring circuit includes a trigger module, a sampling module, a sample storage module, and a sample output module, the trigger module is configured to obtain a trigger signal and send a sampling enable signal to the sampling module when it is detected that the trigger signal satisfies a preset trigger condition, the sampling module samples a signal to be observed of the user circuit according to the sampling enable signal and stores the signal in the sample storage module according to a sampling clock until a sampling process is completed, and after the sampling process is completed, the sample output module transmits data stored in the sample storage module to the outside of the FPGA by using the boundary scan chain.

3. The method according to claim 2, wherein during the operation of the user circuit, the trigger module triggers the sampling module to perform sampling in each sampling process a plurality of times according to the acquired trigger signal.

4. The method according to claim 3, wherein the trigger module triggers the sampling module to sample multiple times according to the received trigger signal, and the preset trigger conditions used at least twice are different.

5. The method of claim 3, wherein the sampling module samples the signal to be observed of the user circuit using different sampling parameters in at least two different sampling processes, wherein the sampling parameters comprise a sampling length and/or a sampling number.

6. The method according to claim 2, characterized in that the global clock tree of the FPGA serves as the sampling clock used by the sampling module and/or the sampling enable signal sent by the trigger module.

7. The method according to claim 2, wherein the trigger signal acquired by the trigger module is from the user circuit or is external to the FPGA.

8. The method according to any one of claims 1 to 7, wherein at least one basic logic unit exists in the FPGA, a part of logic components included in the basic logic unit belong to the second type of resources, and the other part of logic components belong to the first type of resources.

9. The method of claim 8, wherein a portion of the logic components in the basic logic unit are randomly selected to be reserved as the second type of resource, or wherein a portion of the logic components in the basic logic unit are selected to be reserved as the second type of resource at intervals.

10. The method according to any of claims 1-7, wherein all programmable logic resources in a predetermined area of the FPGA belong to the second class of resources and programmable logic resources in the remaining area belong to the first class of resources.

11. The method according to claim 10, wherein the predetermined area is an area included in a basic module, or an area included in each row structure or column structure in the FPGA, or an area included in a clock domain, or an area located at a predetermined position and having a predetermined area range.

12. The method according to claim 10, wherein the FPGA comprises a plurality of said predefined areas located at different positions, each predefined area comprises one or more basic modules, each basic module contained in each predefined area belongs to one or more resource types, there are at least two predefined areas having different area ranges, and/or there are at least two predefined areas comprising basic modules of different resource types.

13. The method of claim 12, wherein two predefined regions containing different types of resources have different region extents.

14. The method of claim 12, wherein each of the predetermined regions is randomly distributed within the FPGA or spaced within the FPGA.

15. The method of claim 10, wherein the FPGA is a multi-die FPGA, the multi-die FPGA includes a plurality of FPGA dies having a connection relationship therein, and the predetermined regions are all located on the same FPGA die.

16. The method according to claim 15, wherein the programmable logic resources contained in the predetermined area are less than the programmable logic resources contained in the FPGA die on which the second type of resources is located, and a part of the programmable logic resources included in the FPGA die on which the second type of resources is located belong to the first type of resources, and the first type of resources of the same FPGA die and the second type of resources are shared to form the predetermined circuit portion in the user circuit.

Background

When a user circuit is implemented on an FPGA and normally operates on the FPGA, in order to determine that an operation process of the user circuit on the FPGA is correct and conforms to a design concept, it is generally required to observe behaviors or waveforms of certain specific signals inside the user circuit. In order to realize the function, the current practice is to add a monitoring circuit on the FPGA, and when the user circuit normally operates on the FPGA, the monitoring circuit is used to sample a signal to be observed of the user circuit and output the signal to the FPGA to perform online observation and monitoring, so as to realize corresponding debugging.

But the existing method is difficult to debug, mainly because the addition of the monitoring circuit can affect the user circuit behavior of the original user circuit: when the user circuit is implemented on the FPGA alone, the user circuit adopts the layout and wiring environment a, so that the user circuit has a corresponding user circuit behavior a, and the user circuit behavior may include a plurality of meanings such as a timing of some signals or a timing relationship before some signals. After the monitoring circuit is added, the monitoring circuit also occupies programmable logic resources inside the FPGA, and a new circuit obtained by combining the user circuit and the monitoring circuit needs to be subjected to overall layout and wiring on the FPGA, so that under the influence of the monitoring circuit, the layout and wiring environment of the user circuit changes compared with the situation that the monitoring circuit is not arranged, namely, the layout and wiring environment is changed into a layout and wiring environment B, and the user circuit has a corresponding user circuit behavior B. Therefore, according to the conventional method, after the monitoring circuit is added, the behavior of the user circuit actually changes due to the change of the layout and wiring environment, so that the observed signal to be observed is different from the actual signal when the monitoring circuit is not added, the observation and monitoring result is inaccurate, and the debugging accuracy depends on the accuracy of the observation and monitoring result, thereby causing higher debugging difficulty and low debugging accuracy.

Disclosure of Invention

The invention provides a high-accuracy FPGA online debugging method aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

a high-accuracy FPGA online debugging method comprises the following steps:

when debugging the user circuit, determining that the global circuit consists of the user circuit and a monitoring circuit, wherein the monitoring circuit is connected with the user circuit;

generating a configuration code stream corresponding to the global circuit based on programmable logic resources in the FPGA, wherein the configuration code stream comprises a first part which is generated based on first type resources and corresponds to a user circuit and a second part which is generated based on second type resources and corresponds to a monitoring circuit; the first type of resource and the second type of resource respectively represent programmable logic resources of different parts in the FPGA, the first type of resource is the programmable logic resource which is used for realizing a user circuit when the user circuit is not debugged in the FPGA, and the hardware structures of the programmable logic resources with the same resource type in the first type of resource and the second type of resource are the same;

and loading the configuration code stream onto the FPGA, wherein the FPGA forms a user circuit by utilizing a first class of resource based on a first part in the configuration code stream and forms a monitoring circuit by utilizing a second class of resource based on a second part in the configuration code stream, and the monitoring circuit samples a signal to be observed of the user circuit in the operation process of the user circuit and transmits the signal to the outside of the FPGA by utilizing a boundary scan chain built in the FPGA for monitoring and debugging.

The monitoring circuit comprises a trigger module, a sampling module, a sample storage module and a sample output module, wherein the trigger module is used for acquiring a trigger signal and sending a sampling enabling signal to the sampling module when the trigger signal is detected to meet a preset trigger condition, the sampling module samples a signal to be observed of the user circuit according to the sampling enabling signal and stores the signal in the sample storage module according to a sampling clock until the sampling process is finished, and the sample output module transmits data stored in the sample storage module to the outside of the FPGA by using a boundary scan chain after the sampling process is finished.

The further technical scheme is that in the operation process of the user circuit, the trigger module triggers the sampling module to sample in each sampling process for multiple times according to the acquired trigger signal.

The further technical scheme is that when the trigger module triggers the sampling module to sample for multiple times according to the received trigger signal, preset trigger conditions used at least twice are different.

The further technical scheme is that the sampling module samples the signal to be observed of the user circuit by using different sampling parameters in at least two different sampling processes, wherein the sampling parameters comprise sampling length and/or sampling times.

The further technical scheme is that a global clock tree of the FPGA is used as a sampling clock used by a sampling module and/or a sampling enabling signal sent by a trigger module.

The further technical scheme is that the trigger signal acquired by the trigger module comes from a user circuit or comes from the outside of the FPGA.

The technical scheme is that a part of logic components contained in at least one basic logic unit in the FPGA belong to the second type of resources, and the other part of logic components belong to the first type of resources.

The further technical scheme is that a part of logic parts are randomly selected in the basic logic unit to be reserved as the second type of resources, or a part of logic parts are selected at intervals in the basic logic unit to be reserved as the second type of resources.

The further technical scheme is that all programmable logic resources in a preset area of the FPGA belong to the second type of resources, and the programmable logic resources in the other areas belong to the first type of resources.

The further technical scheme is that the predetermined area is an area contained in a basic module, or the predetermined area is an area contained in each row structure or column structure in the FPGA, or the predetermined area is an area contained in a clock domain, or the predetermined area is located at a predetermined position and has a predetermined area range.

The FPGA comprises a plurality of preset areas which are positioned at different positions, each preset area comprises one or more basic modules, the basic modules contained in each preset area belong to one or more resource types, at least two preset areas have different area ranges, and/or at least two preset areas comprise basic modules of different resource types.

The further technical scheme is that two preset areas with different resource types have different area ranges.

The further technical scheme is that each preset area is randomly distributed in the FPGA or distributed in the FPGA at intervals.

The FPGA is a multi-die FPGA, the multi-die FPGA comprises a plurality of FPGA dies with connection relations, and the predetermined regions are all located on the same FPGA die.

The further technical scheme is that the programmable logic resources contained in the predetermined area are less than the programmable logic resources contained in the FPGA bare chip where the second type of resources are located, part of the programmable logic resources in the FPGA bare chip where the second type of resources are located belong to the first type of resources, and the first type of resources of the same FPGA bare chip are shared with the second type of resources to form a predetermined circuit part in the user circuit.

The beneficial technical effects of the invention are as follows:

the application discloses a high-accuracy FPGA online debugging method, programmable logic resources inside an FPGA are divided in advance, first-class resources used for realizing a user circuit when the user circuit is debugged are used, and meanwhile, programmable logic resources used for realizing the user circuit are not debugged on the user circuit, so that before and after the monitoring circuit is added, the layout and wiring environment of the user circuit is basically not influenced, the behavior of the user circuit is basically kept consistent before and after the monitoring circuit is added, therefore, signals obtained by the monitoring circuit through monitoring the user circuit are more accurate, and the debugging is also more accurate.

Drawings

Fig. 1 is a schematic diagram of an implementation flow of a global circuit on an FPGA when a monitoring circuit is used to perform online debugging on a user circuit.

Fig. 2 is a schematic diagram of an implementation flow of different global circuits on an FPGA in two different scenarios, i.e., online debugging and offline debugging of a user circuit.

Fig. 3 is a schematic diagram of the arrangement of programmable logic resources inside the FPGA.

Fig. 4 is a schematic diagram of a monitoring circuit.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses a high-accuracy FPGA online debugging method, please refer to a flow chart shown in FIG. 1, and the method comprises the following steps:

step S1, when debugging the user circuit, determining that the global circuit is composed of the user circuit and the monitoring circuit, and the monitoring circuit is connected to the user circuit.

The global circuit in the application is a whole circuit structure which needs to be realized by using programmable logic resources on the FPGA and operates on the FPGA, the global circuit at least comprises a user circuit, and the user circuit is a circuit structure which is used for realizing a user design function in the global circuit. When debugging the user circuit, the global circuit includes, in addition to the user circuit, a monitoring circuit connected to the user circuit, and the monitoring circuit is a circuit structure in the global circuit for implementing a signal monitoring function for the user circuit, and in this case, the global circuit is composed of the user circuit and the monitoring circuit.

Meanwhile, the process of the method is compatible with the scenes that the user circuit is not debugged and runs on the FPGA independently, but the user circuit is not debugged, and the meanings of the global circuit and the configuration code stream are different from those in the debugging process.

And step S2, generating a configuration code stream corresponding to the global circuit based on the programmable logic resource in the FPGA.

The programmable logic resource inside the FPGA comprises a plurality of basic modules and interconnection resources (INT) distributed around each basic module, each basic module is a programmable logic resource of a resource type, the resource type of the programmable logic resource mainly comprises a CLB (basic logic unit), a BRAM (Branch), an IOB (input/output interface), a DSP (digital signal processor), a PC (personal computer) and the like, and each resource type comprises a plurality of basic modules. For example, in fig. 3, the programmable logic resource inside the FPGA includes 15 basic modules belonging to three different resource types, among which there are 12 CLBs, 2 DSPs, and 1 BRAM. Each basic logic unit CLB includes several logic parts therein, and the logic parts included therein mainly include LUTs (look-up tables) and REGs (registers). The basic modules are arranged according to a certain structure, such as the existing conventional Column-Based FPGA architecture, wherein each Column is a basic module with the same resource type, for example, a CLB Column is full of one chip Column from top to bottom in a CLB arrangement, and a BRAM Column is full of one chip Column from top to bottom in a BRAM arrangement.

The method divides programmable logic resources in the FPGA into two types in advance, the first type of resources and the second type of resources respectively represent programmable logic resources of different parts, a user circuit and a monitoring circuit have respective exclusive programmable logic resources, the user circuit and the monitoring circuit are respectively realized by the respective corresponding type of resources, the resource type and the number of basic modules contained in each type of resources are determined according to the pre-estimated scale of the corresponding circuit, generally, the scale of the user circuit is larger than that of the monitoring circuit, and therefore, the resource scale of the programmable logic resources contained in the first type of resources corresponding to the user circuit is larger than that of the second type of resources corresponding to the monitoring circuit. And the hardware structures of the programmable logic resources with the same resource type in the first type of resources and the second type of resources are the same, for example, the hardware structures of the CLBs in the first type of resources and the CLBs in the second type of resources are the same, that is, the hardware structures of the programmable logic resources inside the FPGA are not modified, but the programmable logic resources are only divided.

The configuration code stream corresponding to the global circuit can be generated based on the divided first-class resources and second-class resources, when the user circuit is debugged, the global circuit is composed of the user circuit and the monitoring circuit, and the configuration code stream comprises a first part which is generated based on the first-class resources and corresponds to the user circuit and a second part which is generated based on the second-class resources and corresponds to the monitoring circuit. When the user circuit is not debugged, the global circuit is only formed by the user circuit, at the moment, the configuration code stream is generated based on the first type of resources in the FPGA and corresponds to the user circuit, so the first type of resources for realizing the user circuit when the user circuit is debugged are used, and meanwhile, the programmable logic resources for realizing the user circuit when the user circuit is not debugged are also used.

Which programmable logic resources in the FPGA belong to the first class of resources and which belong to the second class of resources are pre-divided, optionally, the following different division modes are provided in the present application:

in the first mode, the first type of resources and the second type of resources share the basic module at the same position, and the mode mainly aims at the basic module with the resource type of the basic logic unit CLB, namely, a part of logic components contained in at least one basic logic unit in the FPGA belong to the second type of resources, and the other part of logic components belong to the first type of resources. When dividing the logic components in one basic logic unit, the logic components can be divided according to any one of the following conditions: (1) and randomly selecting a part of logic parts in the basic logic unit to be reserved as second-class resources and the rest logic parts as first-class resources. (2) And selecting a part of logic parts in the basic logic unit at intervals to be reserved as the second type of resources, and taking the rest logic parts as the first type of resources.

Because the CLB internally includes two types of logic components, namely LUT and REG, when a part of logic components included in a basic logic unit is reserved as the second type of resources, the following situations are included:

(a) only a part of the LUTs or the entire LUT is reserved as the second type of resources, all REGs and possibly unselected LUTs as the first type of resources.

(b) Only a part of REGs or all REGs are reserved as the second type of resource, all LUTs and possibly non-selected REGs as the first type of resource.

(c) And simultaneously selecting a part of LUTs and a part of REGs as the second type of resources and the rest of the LUTs and REGs which are not selected as the first type of resources. This is the most common way, e.g. a CLB includes 8 LUTs and 16 REGs inside, then 2 LUTs and 4 REGs can be divided to belong to the second class of resources, and the remaining 6 LUTs and 12 REGs belong to the first class of resources.

When part of the LUT and part of the REG are selected as the second type of resource, the LUT and the REG can both adopt random selection reservation, or both adopt interval selection reservation, or one adopts random selection reservation and the other adopts interval selection reservation. When the LUT and the REG adopt interval selection reservation, the intervals adopted by the LUT and the REG are the same or different, for example, when the LUT is selected in interval, one reservation is selected from every 1 LUT as a second type of resource; when the REGs are selected at intervals, one reserved resource is selected from every 2 LUTs as the second type resource.

And secondly, classifying the classes of the programmable logic resources according to the positions of the programmable logic resources, wherein all the programmable logic resources in the preset area of the FPGA belong to the second class of resources, and the programmable logic resources in the other areas except the preset area belong to the first class of resources. Unlike the first approach, in this approach, each class of resources has exclusive ownership of a basic unit at a location, i.e., when a CLB is partitioned into resources of the second class, all LUTs and REGs within the CLB belong to the resources of the second class. The preset area has a plurality of different meanings, respectively corresponds to different division modes, and is classified as follows:

in the first category, a predetermined area includes only one basic module: (1) the predefined area is the area encompassed by one basic module, in which case only one basic module belonging to one resource type is included in the predefined area. For example, a region in which a CLB is located is divided into the second type of resources as a predetermined region, or a region in which a BRAM is located is divided into the second type of resources as a predetermined region.

In the second category, a predetermined area includes at least two basic modules, which may include the following cases:

(2) the predetermined area is an area included in each row structure or column structure within the FPGA, and in this case, the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types. It is more common to use each Column structure in the FPGA as a predetermined area, and in the Column-Based FPGA architecture, the resource types of the basic modules in the same Column structure are the same, so Based on this, the predetermined area includes a plurality of basic modules belonging to the same resource type.

(3) The predetermined area is an area included in one clock domain, in which case the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types.

(4) The predetermined area is located at a predetermined position and has a predetermined area range, in which case the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types. That is, the predetermined area is divided by self-defining according to needs, and the predetermined position can be selected from any suitable position according to needs, such as the lower left corner of the whole slice, the center of the whole slice, the upper right corner of the whole slice, the highest line/lowest line of the clock domain, and the like. The predetermined area range may also be configured with a suitable size as required, for example, the predetermined area range is configured to include 8 × 6 CLBs.

In practice, all programmable logic resources in a predetermined area may be reserved for the second type of resources. Or, all programmable logic resources in a plurality of predetermined areas are reserved for the second type of resource, and a plurality of predetermined areas at different positions are included in the FPGA, wherein the position of the BRAM is usually close to the corresponding CLB in the same type of resource or close to the boundary of the clock domain. In general, the first type of resource and the second type of resource each include basic modules of a plurality of resource types, and in the above case (1), one predetermined area includes only one basic module of one resource type, so that especially when the area range of a single predetermined area is as in the above case (1), a plurality of predetermined areas are generally included in the FPGA, and similarly, when the area range of a single predetermined area is as in the above cases (2), (3) and (4), a plurality of predetermined areas are also generally included in the FPGA.

When a plurality of predetermined areas are included in the FPGA, the plurality of predetermined areas are located at different positions, each predetermined area contains one or more basic modules, the basic modules contained in each predetermined area belong to one or more resource types, each predetermined area contains basic modules of the same resource type, or at least two predetermined areas exist that contain basic modules of different resource types, such as only a CLB in one predetermined area and only a BRAM in another predetermined area.

Each of the predetermined regions includes the same region range as any one of the above (1) to (4), or at least two predetermined regions having different region ranges exist, where two predetermined regions having the same resource type have different region ranges, for example, one predetermined region includes only one CLB in units of CLBs, and another predetermined region includes 8 × 6 CLBs in units of customized predetermined region ranges. Alternatively, two predefined zones with different resource types have different zone ranges, which is more common practice, for example, one predefined zone includes 8 × 6 CLBs in the unit of customized predefined zone range, and the other predefined zone includes 1 BRAM in the unit of BRAM Column.

The plurality of predetermined regions in the FPGA are randomly distributed in the FPGA or are distributed in the FPGA at intervals, when the plurality of predetermined regions are distributed in a partitioned manner, all the predetermined regions may be sequentially distributed at intervals, or more commonly, the predetermined regions containing the same resource type and having the same region range form a group, the predetermined regions in each group are distributed at intervals, and the intervals adopted by different groups are the same or different. For example, 10 predetermined regions in units of CLBs form a group, and the interval between every two predetermined regions is 128 CLBs; the method comprises the following steps that 8 preset regions with CLB columns as units form a group, and the interval between every two preset regions is 64 CLB columns; the method comprises the following steps that 5 preset areas with clock domains as units form a group, and the interval between every two preset areas is 12 clock domains; the 3 preset regions with the BRAM Column as the unit form a group, and the interval between every two preset regions is 2 BRAM columns. It can be seen that the predetermined areas containing different types of resources and/or different coverage areas may be spaced at the same or different intervals in a spaced distribution.

The FPGA in the application can be a single-die FPGA or a multi-die FPGA, and the multi-die FPGA comprises a plurality of FPGA dies with a connection relation. Whether a single-die FPGA or a multi-die FPGA is adopted, the first type of resources and the second type of resources can be divided for the programmable logic resources on the FPGA by adopting any one of the methods provided by the first mode or the second mode. For a single-die FPGA, the first type of resources and the second type of resources obtained by division are located on the same die. For the multi-die FPGA, each class of resources obtained by division respectively comprises programmable logic resources on one or more dies, namely the predetermined area is only positioned on one FPGA die or at least two FPGA dies respectively comprise the predetermined area, and the dies covered by the two classes of resources are the same or different. In this embodiment, in the second mode, for the multi-die FPGA, when all the programmable logic resources in the predetermined area of the multi-die FPGA are divided into the second type of resources, the predetermined area is located on the same FPGA die in the multi-die FPGA, that is, the programmable logic resources on one FPGA die are specially reserved for the second type of resources, and the programmable logic resources on other FPGA dies are all divided into the first type of resources. It should be noted that, if the programmable logic resource of one FPGA bare chip cannot meet the resource requirement of the required second type of resource, the programmable logic resources on the plurality of FPGAs may also be reserved for the second type of resource, but in an actual situation, because the circuit scale of the monitoring circuit is not too large, the resource requirement of the second type of resource is usually not too large, and the programmable logic resource on one FPGA bare chip can meet the requirement.

In the above embodiments, the programmable logic resources included in the predetermined area may be the same as the programmable logic resources included in the FPGA die, that is, all the programmable logic resources on the FPGA die are all divided into the second type of resources. Or, the programmable logic resources included in the predetermined area are less than the programmable logic resources included in the FPGA die, that is, only part of the programmable logic resources on the FPGA die are divided into the second type of resources, and the rest of the programmable logic resources on the FPGA die can be divided into the first type of resources, so that part of the first type of resources and all the second type of resources share the same FPGA die. For example, a multi-die FPGA includes 4 FPGA dies having a connection relationship, which are respectively denoted as a die 1, a die 2, a die 3, and a die 4, and an exemplary way is that the second type of resource includes all programmable logic resources on the die 1, and the first type of resource includes all programmable logic resources on three dies, that is, the die 2, the die 3, and the die 4; another exemplary way is that the second type of resource includes a portion of the programmable logic resources on die 1, and the first type of resource includes the remaining other programmable logic resources on die 1 and all of the programmable logic resources on three die, namely die 2, die 3, and die 4. In this embodiment, the first type of resource sharing the same FPGA die with the second type of resource is used to form a predetermined circuit portion in the user circuit, the predetermined circuit portion is a circuit portion located on a non-critical path in the user circuit configured in advance, and the non-critical path is a path where a timing margin reaches a preset threshold, so that even if the monitoring circuit has some influence on the user circuit, the behavior of the user circuit is not substantially changed.

The skilled person knows that, after the global circuit is input, the configuration code stream corresponding to the global circuit can be generated through steps of synthesis, boxing, layout, wiring, timing analysis and the like, it is noted that the boxing constraint also needs to be satisfied when the programmable logic resources are divided into two types, especially when the first type of resources and the second type of resources share the CLBs at the same position, the CLB boxing constraint needs to be considered to be satisfied, for example, when the monitoring circuit is scattered and respectively added to the CLBs to occupy the logic components belonging to the second type of resources, each CLB is added with at most 2 clock signals, and the REG of the monitoring circuit needs to be connected with one clock signal, the REG in the monitoring circuit can only be added to the CLBs with at least one spare clock signal. And then, normally performing layout and wiring and other processing to generate a configuration code stream, wherein the intermediate steps are not described in detail in the application.

And step S3, loading the configuration code stream to the FPGA to realize a global circuit.

When the user circuit is debugged, corresponding to the situation that the global circuit is composed of the user circuit and the monitoring circuit, the FPGA forms the user circuit by utilizing the first type of resources based on the first part in the configuration code stream and forms the monitoring circuit by utilizing the second type of resources based on the second part in the configuration code stream, the user circuit and the monitoring circuit both run on the FPGA, and meanwhile, the monitoring circuit monitors the running process of the user circuit.

The monitoring circuit samples a signal to be observed of the user circuit in the operation process of the user circuit and transmits the signal to the outside of the FPGA by using a boundary scan chain built in the FPGA for monitoring and debugging, the circuit structure of the monitoring circuit is shown in FIG. 4, the monitoring circuit comprises a trigger module, a sampling module, a Sample storage module and a Sample output module, the trigger module is used for acquiring a trigger signal Trig and sending a sampling enable signal Sample _ EN to the sampling module when detecting that the trigger signal Trig meets a preset trigger condition, and the sampling module samples the signal to be observed of the user circuit according to the sampling enable signal Sample _ EN and a sampling clock CLK and stores the signal in the Sample storage module until the sampling process is finished. The sampling module samples the signal to be observed Sig according to the preconfigured sampling parameters, wherein the sampling parameters comprise sampling length and/or sampling times, so that when the length of the sampled data reaches the preconfigured sampling length and/or the sampled times reaches the preconfigured sampling times, the end of the sampling process is determined, wherein the preconfigured sampling length and/or the sampled times do not exceed the storage capacity of the sample storage module, and storage overflow is avoided. And after the sampling process is finished, the sample output module transmits the data stored in the sample storage module to the outside of the FPGA by utilizing the built-in boundary scan chain of the FPGA according to the first-in first-out sequence. And then the off-chip connector can receive and arrange the data and display waveforms, and then debug, thereby realizing the on-line monitoring and debugging of the signal to be observed.

In the circuit structure, the trigger module is mainly realized by a trigger formed by a register and an LUT, the register is used for storing a preset trigger condition, and the trigger is used for sending a sampling enable signal Sample _ EN when an acquired trigger signal Trig meets the preset trigger condition. The sampling module is mainly realized by a counter formed by a register and an LUT (look up table), the register is used for storing sampling parameters, and the counter realizes the counting of sampling times. The sample storage module is mainly implemented by BRAM. The sample output module is mainly realized by a shift register.

In one embodiment, the global clock tree of the FPGA serves as a sampling clock for the sampling module and/or as a sampling enable signal for the trigger module to send.

In the above process, the trigger signal Trig acquired by the trigger module is also from the user circuit, or from outside the FPGA, and fig. 4 takes the trigger signal Trig from the user circuit as an example. The trigger signal Trig includes a single-path or multi-path signal, and the preset trigger condition that the trigger signal Trig needs to satisfy is configured in a user-defined manner in advance, for example, the acquired trigger signal Trig is "a, b, c", and the preset trigger condition is satisfied when "a, b, c ═ 1, 0, 1" is determined.

In the application, since the transmission speed of the boundary scan chain generally cannot reach the sampling bandwidth (sampling speed x sampling bit width) of the sampling module, and synchronous output is difficult to achieve during sampling, the application stores the sampled data first and then outputs the sampled data. Optionally, the user circuit operation process includes a plurality of sampling processes, and the trigger module triggers the sampling module to sample in each sampling process for a plurality of times according to the acquired trigger signal, so that data sampled in each sampling process can be output after each sampling process is finished, or data sampled in a plurality of sampling processes can be output after a plurality of sampling processes are finished.

When the trigger module triggers the sampling module to sample for multiple times according to the received trigger signal, the preset trigger conditions used each time are the same, or the preset trigger conditions used at least twice are different, for example, according to the above example, in one sampling process, when the trigger signal "a, b, c ═ 1, 0, 1", the sampling is triggered; in another sampling process, the sampling is triggered when the trigger signal "a, b, c ═ 0, 0, 1".

Regardless of whether the preset trigger condition used in multiple triggering is the same or not, in another embodiment, the sampling module samples the signal to be observed of the user circuit by using different sampling parameters in at least two different sampling processes, where the sampling parameters include sampling length and/or sampling times.

Similarly, when the user circuit is not debugged, corresponding to the situation that the global circuit is composed of only the user circuit, the FPGA forms the user circuit by using the first type of resources based on the configuration code stream, and the user circuit operates on the FPGA, as shown in fig. 2.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.