1. An FPGA online debugging method for realizing continuous sampling is characterized by comprising the following steps:

when a user circuit is debugged, a configuration code stream corresponding to a global circuit formed by the user circuit and a monitoring circuit is loaded on an FPGA (field programmable gate array), the FPGA utilizes programmable logic resources to realize the user circuit and the monitoring circuit based on the configuration code stream, and the monitoring circuit is connected with the user circuit;

the monitoring circuit at least comprises a sampling module, a sample storage module and a sample output module, wherein the write port bandwidth and the read port bandwidth of the sample storage module are equal to the output bandwidth of the on-chip interface, the monitoring circuit samples a signal to be observed of the user circuit through the sampling module in the operation process of the user circuit and writes the signal into the sample storage module through the write port, after the sampling module starts to sample a preset delay time of the time of writing data, the sample output module starts to read data from the sample storage module through the read port and transmits the data to the outside of the FPGA for monitoring and debugging by utilizing the on-chip interface, and the data sampled and written by the sampling module in the preset delay time is smaller than the storage capacity of the sample storage module.

2. The method of claim 1,

the on-chip interface of the FPGA is a boundary scan interface used by a boundary scan chain built in the FPGA, and the sample output module is connected with the boundary scan chain; the sampling frequency of the sampling module is less than a predetermined threshold.

3. The method of claim 1,

and the on-chip interface of the FPGA is a high-speed serial interface reserved for the monitoring circuit, and the sample output module is connected to the high-speed serial interface through a parallel-serial conversion module.

4. The method of claim 1,

and the on-chip interface of the FPGA is an IO interface reserved for the monitoring circuit, and the sample output module is connected to the IO interface through a parallel-serial conversion module.

5. The method according to any one of claims 1 to 4, wherein the monitoring circuit further includes a trigger module, the trigger module is configured to obtain a trigger signal, send a sampling enable signal to the sampling module when it is detected that the trigger signal satisfies a preset trigger condition, and send an output enable signal to the sample output module after the predetermined delay time, the sampling module samples a signal to be observed of the user circuit according to the sampling enable signal, and the sample output module reads data from the sample storage module according to the output enable signal.

6. The method according to any of claims 1-4, wherein the sample storage module is implemented as a FIFO internal to the FPGA.

7. The method according to any one of claims 1 to 4,

the sample storage module is implemented by one or more BRAMs internal to the FPGA.

8. The method of claim 7,

when the sample storage module is implemented by multiple BRAMs, the multiple BRAMs are adjacent or spaced apart in layout position within the FPGA chip.

9. The method according to any one of claims 1 to 4,

the sample storage module is realized by adopting distributed storage units in the FPGA, and the layout positions of all the storage units in the distributed storage units are adjacent or spaced.

10. The method according to any one of claims 1 to 4,

the storage capacity of the sample storage module is not less than twice the sampling bit width of the sampling module.

11. The method of claim 1,

the FPGA forms a user circuit by utilizing a first class of resources based on a first part corresponding to the user circuit in the configuration code stream and forms a monitoring circuit by utilizing a second class of resources based on a second part corresponding to the monitoring circuit in the configuration code stream;

the first type of resource and the second type of resource respectively represent programmable logic resources of different parts in the FPGA, the first type of resource is a programmable logic resource used for realizing the user circuit when the user circuit is not debugged in the FPGA, and the hardware structures of the programmable logic resources with the same resource type in the first type of resource and the second type of resource are the same.

Background

When a user circuit is implemented on an FPGA and normally operates on the FPGA, in order to determine that an operation process of the user circuit on the FPGA is correct and conforms to a design concept, it is generally required to observe behaviors or waveforms of certain specific signals inside the user circuit. In order to implement this function, the current practice is to add a monitoring circuit on the FPGA, and when the user circuit normally operates on the FPGA, the monitoring circuit is used to sample a signal to be observed of the user circuit and output the signal to the outside of the FPGA for observation and monitoring, so as to implement corresponding debugging.

The existing monitoring circuit usually stores sampled data, and outputs the stored data to the outside of the FPGA for observation after sampling is finished, and the total number of samples in one sampling process is limited by storage capacity, so that the operation is inconvenient.

Disclosure of Invention

The invention provides an FPGA online debugging method for realizing continuous sampling aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

an FPGA online debugging method for realizing continuous sampling comprises the following steps:

when debugging a user circuit, loading a configuration code stream corresponding to a global circuit consisting of the user circuit and a monitoring circuit to an FPGA (field programmable gate array), wherein the FPGA utilizes programmable logic resources to realize the user circuit and the monitoring circuit based on the configuration code stream, and the monitoring circuit is connected with the user circuit;

the monitoring circuit at least comprises a sampling module, a sample storage module and a sample output module, wherein the write port bandwidth and the read port bandwidth of the sample storage module are equal to the output bandwidth of the on-chip interface, the monitoring circuit samples a signal to be observed of the user circuit through the sampling module in the operation process of the user circuit and writes the signal into the sample storage module through the write port, after the preset delay time of the time when the sampling module starts to sample and write data, the sample output module starts to synchronously read the data from the sample storage module through the read port and transmits the data to the outside of the FPGA through the on-chip interface for monitoring and debugging, and the data sampled and written by the sampling module in the preset delay time is smaller than the storage capacity of the sample storage module.

The further technical scheme is that an on-chip interface of the FPGA is a boundary scan interface used by a boundary scan chain built in the FPGA, and a sample output module is connected with the boundary scan chain; the sampling frequency of the sampling module is less than the predetermined threshold.

The further technical scheme is that an on-chip interface of the FPGA is a high-speed serial interface reserved for a monitoring circuit, and the sample output module is connected to the high-speed serial interface through the parallel-serial conversion module.

The further technical scheme is that an on-chip interface of the FPGA is an IO interface reserved for a monitoring circuit, and the sample output module is connected to the IO interface through the parallel-serial conversion module.

The monitoring circuit further comprises a trigger module, wherein the trigger module is used for acquiring a trigger signal, sending a sampling enabling signal to the sampling module when detecting that the trigger signal meets a preset trigger condition, and sending an output enabling signal to the sample output module after a preset delay time, the sampling module samples a signal to be observed of the user circuit according to the sampling enabling signal, and the sample output module reads data from the sample storage module according to the output enabling signal.

The further technical scheme is that the sample storage module is realized by FIFO inside the FPGA.

The further technical scheme is that the sample storage module is realized by one or more BRAMs inside the FPGA.

The further technical scheme is that when the sample storage module is realized by a plurality of BRAMs, the plurality of BRAMs are adjacent or spaced at intervals in the layout position in the FPGA chip.

The further technical scheme is that the sample storage module is realized by adopting distributed storage units in the FPGA, and the layout positions of all the storage units in the distributed storage units are adjacent or spaced.

The further technical scheme is that the storage capacity of the sample storage module is not less than twice of the sampling bit width of the sampling module.

The FPGA forms a user circuit by utilizing a first type of resource based on a first part corresponding to the user circuit in the configuration code stream and forms a monitoring circuit by utilizing a second type of resource based on a second part corresponding to the monitoring circuit in the configuration code stream;

the first type of resource and the second type of resource respectively represent programmable logic resources of different parts in the FPGA, the first type of resource is the programmable logic resource which is used for realizing a user circuit when the user circuit is not debugged in the FPGA, and the hardware structures of the programmable logic resources with the same resource type in the first type of resource and the second type of resource are the same.

The beneficial technical effects of the invention are as follows:

the application discloses an FPGA online debugging method for realizing continuous sampling, which is characterized in that sampling write-in action and reading output action are synchronously performed, so that the total number of sampled samples is not limited by the storage capacity of a sample storage module, the phenomenon of sampling pause or data loss caused by overflow of the sample storage module can be avoided, and the accuracy and the efficiency of sampling and debugging are ensured.

Furthermore, programmable logic resources inside the FPGA can be divided in advance, the first type of resources used for realizing the user circuit when the user circuit is debugged are also programmable logic resources used for realizing the user circuit without debugging the user circuit, so that the layout and wiring environment of the user circuit is basically not affected before and after the monitoring circuit is added, and therefore the behavior of the user circuit is basically kept consistent before and after the monitoring circuit is added, signals obtained by the monitoring circuit through monitoring the user circuit are more accurate, and debugging is also more accurate.

Drawings

Fig. 1 is a schematic diagram of information flow of an implementation process of a global circuit on an FPGA when a monitoring circuit is used to perform online debugging on a user circuit, and a circuit structure diagram of the implemented monitoring circuit.

Fig. 2 is another circuit configuration diagram of the monitoring circuit.

Fig. 3 is a schematic diagram of the arrangement of programmable logic resources inside the FPGA.

Fig. 4 is a schematic information flow diagram of another embodiment of a process of implementing a global circuit on an FPGA when a monitoring circuit is used to perform online debugging on a user circuit.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses an FPGA online debugging method for realizing continuous sampling, please refer to fig. 1, and the method is implemented as follows:

when the user circuit is debugged, the configuration code stream corresponding to the global circuit formed by the user circuit and the monitoring circuit is loaded on the FPGA. The global circuit in the application is a whole circuit structure which needs to be realized by using programmable logic resources on the FPGA and operates on the FPGA, the global circuit at least comprises a user circuit, and the user circuit is a circuit structure which is used for realizing a user design function in the global circuit. When debugging the user circuit, the global circuit includes, in addition to the user circuit, a monitoring circuit connected to the user circuit, and the monitoring circuit is a circuit structure in the global circuit for implementing a signal monitoring function for the user circuit, and in this case, the global circuit is composed of the user circuit and the monitoring circuit.

Those skilled in the art know that after the global circuit is input, the configuration code stream corresponding to the global circuit can be generated through steps of synthesis, boxing, layout, wiring, timing analysis and the like, and the intermediate steps are not described in detail in this application.

The FPGA utilizes programmable logic resources to realize a user circuit and a monitoring circuit based on the configuration code stream, and the monitoring circuit is connected with the user circuit. The monitoring circuit at least comprises a sampling module, a sample storage module and a sample output module. The write port and the read port of the sample storage module can be operated simultaneously, the write port bandwidth and the read port bandwidth of the sample storage module are equal to the output bandwidth of the on-chip interface, the write port bandwidth and the read port bandwidth of the common sample storage module are adjustable, but the on-chip interface has the limitation of the interface standard, so the write port bandwidth and the read port bandwidth of the sample storage module are generally adjusted to be equal to the output bandwidth of the on-chip interface. The bandwidth of the write port is the sampling frequency and the sampling bit width, and the bandwidth of the read port is the reading frequency and the reading bit width. The monitoring circuit samples a signal Sig to be observed of the user circuit through the sampling module in the operation process of the user circuit and writes the signal Sig into the sample storage module through the writing port, and after the sampling module starts to sample the preset delay time of the data writing time, the sample output module starts to synchronously read data from the sample storage module through the reading port and transmits the data out of the FPGA through the on-chip interface for monitoring and debugging. The sample output module is mainly realized by a shift register.

The data sampled and written by the sampling module within the preset delay time is smaller than the storage capacity of the sample storage module, so that the reading can be started before the storage capacity of the sample storage module is full, the writing and the reading are in dynamic balance, and the storage overflow condition is avoided. Particularly, the sample output module and the sampling module can be controlled to start working synchronously.

The storage capacity of the sample storage module is not less than twice of the sampling bit width of the sampling module, and when data with one sampling bit width is written, data with the other sampling bit width is read, so that although the storage capacity of the sample storage module is fixed, the total sample number is not limited by the storage capacity of the sample storage module due to the fact that writing and reading operations are performed synchronously, that is, the sample storage module can not overflow and can work normally no matter how large the total sample number is before the sampling module meets the preset stop condition to stop sampling, and therefore continuous sampling can be achieved.

Although theoretically, the overflow of the sample storage module can be avoided if the output bandwidth is larger than the write port bandwidth, but the idle waiting condition of the output part also needs to be avoided, so that the write port bandwidth and the read port bandwidth are set to be equal to the output bandwidth of the on-chip interface, and the overflow of the memory can be avoided, and the empty of the memory can also be avoided.

The sample storage module has a plurality of different implementations:

(1) in one embodiment, the sample storage module is implemented as a FIFO inside the FPGA.

(2) In another embodiment, the sample storage module is implemented by one or more BRAMs internal to the FPGA. Optionally, when the sample storage module is implemented by multiple BRAMs, the multiple BRAMs are adjacent or spaced apart in layout position within the FPGA chip.

(3) In another embodiment, the sample storage module is implemented by using distributed storage units inside the FPGA, and layout positions of the storage units in the distributed storage units are adjacent or spaced apart.

No matter how the sample storage module is realized, the on-chip interface of the FPGA has the following different implementation modes, and the different implementation modes respectively have advantages and disadvantages:

(1) in one embodiment, the on-chip interface of the FPGA is a boundary scan interface used by a boundary scan chain built in the FPGA, and the sample output module is connected with the boundary scan chain, as shown in fig. 1. The method can multiplex the existing interface without occupying additional interface resources, but the read frequency of the boundary scan chain is low, generally 50MHz to 100MHz, and the boundary scan interface is a serial interface, that is, the read bit width is 1 bit, that is, the output bandwidth of the on-chip interface is low in this case, and the sampling frequency that can be reached by the sampling module may cause the write port bandwidth to exceed the output bandwidth, so in this case, the sampling frequency of the sampling module needs to be limited, that is, the sampling frequency of the sampling module is controlled to be less than the predetermined threshold.

If the sampling frequency of the sampling module is not controlled, the write port bandwidth is larger than the output bandwidth, and the sample storage module still overflows, at this time, the sampling module needs to be controlled to suspend writing, and the writing is continued when the sample storage module has enough space, wherein the suspending writing can be suspending sampling or discarding and not writing after sampling.

(2) In another embodiment, the on-chip interface of the FPGA is an IO interface reserved for the monitoring circuit, and the sample output module is connected to the IO interface through a parallel-to-serial conversion module, and a common IO interface, such as LVDS, requires a special IO interface to be reserved for the monitoring circuit, and occupies additional interface resources compared to a method using a boundary scan chain. Moreover, the IO interface of the FPGA is usually a serial interface, that is, the read bit width is 1 bit, so an additional serial-parallel conversion module needs to be provided, the sample output module is connected to the IO interface through the parallel-serial conversion module, and at this time, the structure of the monitoring circuit refers to fig. 2. However, this approach has the advantages that the readout frequency is higher than that of the boundary scan chain, for example, LVDS usually has about 1200MHz, so the output bandwidth is higher, and the output bandwidth can be increased by implementing parallel output of a plurality of on-chip interfaces through a plurality of IO interfaces. Therefore, the sampling frequency of the sampling module is not required to be limited, and the overflow of the sample storage module can not happen basically.

(3) In another embodiment, the on-chip interface of the FPGA is a high-speed serial interface reserved for the monitoring circuit, the common high-speed serial interface includes SERDES and GTP, the high-speed serial interface of the FPGA is a serial interface, that is, the read bit width is 1 bit, therefore, an additional serial-to-parallel conversion module needs to be provided, the sample output module is connected to the high-speed serial interface through the parallel-to-serial conversion module, the circuit structure is similar to the case of using an IO interface to implement the on-chip interface, please refer to fig. 2. The FPGA has more common IO interfaces and fewer high-speed serial interfaces, and the method needs to occupy precious and scarce high-speed serial interfaces. However, the high-speed serial interface has a higher reading frequency than a common IO interface, usually 3125MHz to 12000MHz, so the sampling frequency of the sampling module is not limited, and the overflow of the sample storage module is not substantially caused.

Optionally, the monitoring circuit further includes a trigger module, as shown in fig. 1 and 2, the trigger module is configured to obtain a trigger signal Trig, send a sampling enable signal Sample _ EN to the sampling module when it is detected that the trigger signal Trig meets a preset trigger condition, and send an Output enable signal Output _ EN to the Sample Output module after a predetermined delay time. The sampling module samples a signal to be observed of the user circuit according to the sampling enable signal Sample _ EN, and the Sample Output module reads data Output from the Sample storage module according to the Output enable signal Output _ EN according to a first-in first-out sequence, so that synchronous read-write operation is realized, and continuous sampling is realized. And then the off-chip connector can receive and arrange the data and display waveforms, and then debug, thereby realizing the on-line monitoring and debugging of the signal to be observed.

In the circuit structure, the trigger module is mainly realized by a trigger formed by a register and an LUT, the register is used for storing a preset trigger condition, and the trigger is used for sending a sampling enable signal Sample _ EN and an Output enable signal Output _ EN when an acquired trigger signal Trig meets the preset trigger condition.

In the above process, the trigger signal Trig acquired by the trigger module is also from the user circuit or from outside the FPGA, and fig. 1 and 2 take the example that the trigger signal Trig is from the user circuit. The trigger signal Trig includes a single-path or multi-path signal, and the preset trigger condition that the trigger signal Trig needs to satisfy is configured in a user-defined manner in advance, for example, the acquired trigger signal Trig is "a, b, c", and the preset trigger condition is satisfied when "a, b, c ═ 1, 0, 1" is determined.

When the trigger module triggers the sampling module to sample for multiple times according to the received trigger signal, the preset trigger conditions used each time are the same, or the preset trigger conditions used at least twice are different, for example, according to the above example, in one sampling process, when the trigger signal "a, b, c ═ 1, 0, 1", the sampling is triggered; in another sampling process, the sampling is triggered when the trigger signal "a, b, c ═ 0, 0, 1".

Regardless of whether the preset trigger condition used in the multiple triggering is the same, in another embodiment, the sampling has different preset stop conditions and/or sampling parameters in at least two different sampling processes, and the sampling parameters include the sampling length and/or the number of sampling times and/or the total number of samples sampled.

In an embodiment of the present application, besides the implementation of the global circuit in the FPGA according to a conventional method, the implementation can be realized by the following method:

in the method provided in this embodiment, the programmable logic resources inside the FPGA are divided into two types in advance, the first type of resources and the second type of resources respectively represent programmable logic resources of different portions inside the FPGA, the user circuit and the monitoring circuit have respective dedicated one type of programmable logic resources, and the user circuit and the monitoring circuit are implemented by respective corresponding one type of resources. Therefore, the first type of resources are programmable logic resources used for realizing the user circuit when the user circuit is not debugged in the FPGA, and are also programmable logic resources used for realizing the user circuit when the user circuit is debugged in the FPGA, and the second type of resources are programmable logic resources used for realizing the monitoring circuit when the user circuit is debugged in the FPGA. The resource type and the number of the basic modules contained in each type of resource are determined according to the estimated scale of the corresponding circuit, generally, the scale of the user circuit is larger than that of the monitoring circuit, and therefore, the resource scale of the programmable logic resource contained in the first type of resource corresponding to the user circuit is larger than that of the second type of resource corresponding to the monitoring circuit. The hardware structures of the programmable logic resources having the same resource type in the first type of resource and the second type of resource are the same, for example, the hardware structures of the CLBs in the first type of resource and the CLBs in the second type of resource are the same, that is, the hardware structures of the programmable logic resources inside the FPGA are not modified, but the programmable logic resources are only divided.

The programmable logic resource inside the FPGA comprises a plurality of basic modules and interconnection resources (INT) distributed around each basic module, each basic module is a programmable logic resource of a resource type, the resource type of the programmable logic resource mainly comprises a CLB (basic logic unit), a BRAM (Branch), an IOB (input/output interface), a DSP (digital signal processor), a PC (personal computer) and the like, and each resource type comprises a plurality of basic modules. For example, in fig. 3, the programmable logic resource inside the FPGA includes 15 basic modules belonging to three different resource types, among which there are 12 CLBs, 2 DSPs, and 1 BRAM. Each basic logic unit CLB includes several logic parts therein, and the logic parts included therein mainly include LUTs (look-up tables) and REGs (registers). The basic modules are arranged according to a certain structure, such as the existing conventional Column-Based FPGA architecture, wherein each Column is a basic module with the same resource type, for example, a CLB Column is full of one chip Column from top to bottom in a CLB arrangement, and a BRAM Column is full of one chip Column from top to bottom in a BRAM arrangement.

The configuration code stream corresponding to the global circuit can be generated based on the divided first-class resources and second-class resources, when the user circuit is debugged, the global circuit is composed of the user circuit and the monitoring circuit, and the configuration code stream comprises a first part which is generated based on the first-class resources and corresponds to the user circuit and a second part which is generated based on the second-class resources and corresponds to the monitoring circuit. When the user circuit is not debugged, the global circuit is only formed by the user circuit, at the moment, the configuration code stream is generated based on the first type of resources in the FPGA and corresponds to the user circuit, so the first type of resources for realizing the user circuit when the user circuit is debugged are used, and meanwhile, the programmable logic resources for realizing the user circuit when the user circuit is not debugged are also used.

Which programmable logic resources in the FPGA belong to the first class of resources and which belong to the second class of resources are pre-divided, optionally, the present embodiment provides several different dividing manners as follows:

in the first mode, the first type of resources and the second type of resources share the basic module at the same position, and the mode mainly aims at the basic module with the resource type of the basic logic unit CLB, namely, a part of logic components contained in at least one basic logic unit in the FPGA belong to the second type of resources, and the other part of logic components belong to the first type of resources. When dividing the logic components in one basic logic unit, the logic components can be divided according to any one of the following conditions: (1) and randomly selecting a part of logic parts in the basic logic unit to be reserved as second-class resources and the rest logic parts as first-class resources. (2) And selecting a part of logic parts in the basic logic unit at intervals to be reserved as the second type of resources, and taking the rest logic parts as the first type of resources.

Because the CLB internally includes two types of logic components, namely LUT and REG, when a part of logic components included in a basic logic unit is reserved as the second type of resources, the following situations are included:

(a) only a part of the LUTs or the entire LUT is reserved as the second type of resources, all REGs and possibly unselected LUTs as the first type of resources.

(b) Only a part of REGs or all REGs are reserved as the second type of resource, all LUTs and possibly non-selected REGs as the first type of resource.

(c) And simultaneously selecting a part of LUTs and a part of REGs as the second type of resources and the rest of the LUTs and REGs which are not selected as the first type of resources. This is the most common way, e.g. a CLB includes 8 LUTs and 16 REGs inside, then 2 LUTs and 4 REGs can be divided to belong to the second class of resources, and the remaining 6 LUTs and 12 REGs belong to the first class of resources.

When part of the LUT and part of the REG are selected as the second type of resource, the LUT and the REG can both adopt random selection reservation, or both adopt interval selection reservation, or one adopts random selection reservation and the other adopts interval selection reservation. When the LUT and the REG adopt interval selection reservation, the intervals adopted by the LUT and the REG are the same or different, for example, when the LUT is selected in interval, one reservation is selected from every 1 LUT as a second type of resource; when the REGs are selected at intervals, one reserved resource is selected from every 2 LUTs as the second type resource.

And secondly, classifying the classes of the programmable logic resources according to the positions of the programmable logic resources, wherein all the programmable logic resources in the preset area of the FPGA belong to the second class of resources, and the programmable logic resources in the other areas except the preset area belong to the first class of resources. Unlike the first approach, in this approach, each class of resources has exclusive ownership of a basic unit at a location, i.e., when a CLB is partitioned into resources of the second class, all LUTs and REGs within the CLB belong to the resources of the second class. The preset area has a plurality of different meanings, respectively corresponds to different division modes, and is classified as follows:

in the first category, a predetermined area includes only one basic module: (1) the predefined area is the area encompassed by one basic module, in which case only one basic module belonging to one resource type is included in the predefined area. For example, a region in which a CLB is located is divided into the second type of resources as a predetermined region, or a region in which a BRAM is located is divided into the second type of resources as a predetermined region.

In the second category, a predetermined area includes at least two basic modules, which may include the following cases:

(2) the predetermined area is an area included in each row structure or column structure within the FPGA, and in this case, the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types. It is more common to use each Column structure in the FPGA as a predetermined area, and in the Column-Based FPGA architecture, the resource types of the basic modules in the same Column structure are the same, so Based on this, the predetermined area includes a plurality of basic modules belonging to the same resource type.

(3) The predetermined area is an area included in one clock domain, in which case the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types.

(4) The predetermined area is located at a predetermined position and has a predetermined area range, in which case the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types. That is, the predetermined area is divided by self-defining according to needs, and the predetermined position can be selected from any suitable position according to needs, such as the lower left corner of the whole slice, the center of the whole slice, the upper right corner of the whole slice, the highest line/lowest line of the clock domain, and the like. The predetermined area range may also be configured with a suitable size as required, for example, the predetermined area range is configured to include 8 × 6 CLBs.

In practice, all programmable logic resources in a predetermined area may be reserved for the second type of resources. Or, all programmable logic resources in a plurality of predetermined areas are reserved for the second type of resource, and a plurality of predetermined areas at different positions are included in the FPGA, wherein the position of the BRAM is usually close to the corresponding CLB in the same type of resource or close to the boundary of the clock domain. In general, the first type of resource and the second type of resource each include basic modules of a plurality of resource types, and in the above case (1), one predetermined area includes only one basic module of one resource type, so that especially when the area range of a single predetermined area is as in the above case (1), a plurality of predetermined areas are generally included in the FPGA, and similarly, when the area range of a single predetermined area is as in the above cases (2), (3) and (4), a plurality of predetermined areas are also generally included in the FPGA.

When a plurality of predetermined areas are included in the FPGA, the plurality of predetermined areas are located at different positions, each predetermined area contains one or more basic modules, the basic modules contained in each predetermined area belong to one or more resource types, each predetermined area contains basic modules of the same resource type, or at least two predetermined areas exist that contain basic modules of different resource types, such as only a CLB in one predetermined area and only a BRAM in another predetermined area.

Each of the predetermined regions includes the same region range as any one of the above (1) to (4), or at least two predetermined regions having different region ranges exist, where two predetermined regions having the same resource type have different region ranges, for example, one predetermined region includes only one CLB in units of CLBs, and another predetermined region includes 8 × 6 CLBs in units of customized predetermined region ranges. Alternatively, two predefined zones with different resource types have different zone ranges, which is more common practice, for example, one predefined zone includes 8 × 6 CLBs in the unit of customized predefined zone range, and the other predefined zone includes 1 BRAM in the unit of BRAM Column.

The plurality of predetermined regions in the FPGA are randomly distributed in the FPGA or are distributed in the FPGA at intervals, when the plurality of predetermined regions are distributed in a partitioned manner, all the predetermined regions may be sequentially distributed at intervals, or more commonly, the predetermined regions containing the same resource type and having the same region range form a group, the predetermined regions in each group are distributed at intervals, and the intervals adopted by different groups are the same or different. For example, 10 predetermined regions in units of CLBs form a group, and the interval between every two predetermined regions is 128 CLBs; the method comprises the following steps that 8 preset regions with CLB columns as units form a group, and the interval between every two preset regions is 64 CLB columns; the method comprises the following steps that 5 preset areas with clock domains as units form a group, and the interval between every two preset areas is 12 clock domains; the 3 preset regions with the BRAM Column as the unit form a group, and the interval between every two preset regions is 2 BRAM columns. It can be seen that the predetermined areas containing different types of resources and/or different coverage areas may be spaced at the same or different intervals in a spaced distribution.

The FPGA in the application can be a single-die FPGA or a multi-die FPGA, and the multi-die FPGA comprises a plurality of FPGA dies with a connection relation. Whether a single-die FPGA or a multi-die FPGA is adopted, the first type of resources and the second type of resources can be divided for the programmable logic resources on the FPGA by adopting any one of the methods provided by the first mode or the second mode. For a single-die FPGA, the first type of resources and the second type of resources obtained by division are located on the same die. For the multi-die FPGA, each class of resources obtained by division respectively comprises programmable logic resources on one or more dies, namely the predetermined area is only positioned on one FPGA die or at least two FPGA dies respectively comprise the predetermined area, and the dies covered by the two classes of resources are the same or different. In this embodiment, in the second mode, for the multi-die FPGA, when all the programmable logic resources in the predetermined area of the multi-die FPGA are divided into the second type of resources, the predetermined area is located on the same FPGA die in the multi-die FPGA, that is, the programmable logic resources on one FPGA die are specially reserved for the second type of resources, and the programmable logic resources on other FPGA dies are all divided into the first type of resources. It should be noted that, if the programmable logic resource of one FPGA bare chip cannot meet the resource requirement of the required second type of resource, the programmable logic resources on the plurality of FPGAs may also be reserved for the second type of resource, but in an actual situation, because the circuit scale of the monitoring circuit is not too large, the resource requirement of the second type of resource is usually not too large, and the programmable logic resource on one FPGA bare chip can meet the requirement.

In the above embodiments, the programmable logic resources included in the predetermined area may be the same as the programmable logic resources included in the FPGA die, that is, all the programmable logic resources on the FPGA die are all divided into the second type of resources. Or, the programmable logic resources included in the predetermined area are less than the programmable logic resources included in the FPGA die, that is, only part of the programmable logic resources on the FPGA die are divided into the second type of resources, and the rest of the programmable logic resources on the FPGA die can be divided into the first type of resources, so that part of the first type of resources and all the second type of resources share the same FPGA die. For example, a multi-die FPGA includes 4 FPGA dies having a connection relationship, which are respectively denoted as a die 1, a die 2, a die 3, and a die 4, and an exemplary way is that the second type of resource includes all programmable logic resources on the die 1, and the first type of resource includes all programmable logic resources on three dies, that is, the die 2, the die 3, and the die 4; another exemplary way is that the second type of resource includes a portion of the programmable logic resources on die 1, and the first type of resource includes the remaining other programmable logic resources on die 1 and all of the programmable logic resources on three die, namely die 2, die 3, and die 4. In this embodiment, the first type of resource sharing the same FPGA die with the second type of resource is used to form a predetermined circuit portion in the user circuit, the predetermined circuit portion is a circuit portion located on a non-critical path in the user circuit configured in advance, and the non-critical path is a path where a timing margin reaches a preset threshold, so that even if the monitoring circuit has some influence on the user circuit, the behavior of the user circuit is not substantially changed.

It should be noted that, when the programmable logic resources are divided into two types, the packing constraint needs to be satisfied, especially when the first type of resources and the second type of resources share the CLBs at the same position, the CLB packing constraint needs to be considered to be satisfied, for example, when the monitoring circuit is scattered and respectively added to the CLBs to occupy the logic components belonging to the second type of resources, each CLB is added with at most 2 clock signals, and the REG of the monitoring circuit needs to be connected with one clock signal, so that the REG in the monitoring circuit can only be added to the CLBs with at least one spare clock signal. Then, the configuration code stream can be generated by normally performing the processes of layout and wiring and the like.

Then, when the FPGA implements the user circuit and the monitoring circuit using the programmable logic resource based on the configuration code stream, referring to fig. 4, the user circuit is formed using the first type of resource based on the first portion corresponding to the user circuit in the configuration code stream, and the monitoring circuit is formed using the second type of resource based on the second portion corresponding to the monitoring circuit in the configuration code stream, so that the user circuit and the monitoring circuit are independent from each other.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.