1. An FPGA online debugging method with dynamically variable sampling frequency is characterized by comprising the following steps:

when a user circuit is debugged, a configuration code stream corresponding to a global circuit formed by the user circuit and a monitoring circuit is loaded on an FPGA (field programmable gate array), the FPGA utilizes programmable logic resources to realize the user circuit and the monitoring circuit based on the configuration code stream, and the monitoring circuit is connected with the user circuit;

the monitoring circuit comprises a clock adjusting module, a sampling module, a sample storage module and a sample output module, wherein in the running process of the user circuit, the clock adjusting module provides a sampling clock corresponding to and matched with the running state of a signal to be observed of the user circuit in the current period to the sampling module, the signal to be observed is in the running process of the user circuit, at least two different running states exist, the sampling clock corresponding to different running states is different in frequency, the sampling module samples and stores the signal to be observed according to the sampling clock provided by the clock adjusting module, and after sampling is completed, the sample output module utilizes a boundary scan chain of the built-in FPGA to transmit the signal to the outside of the FPGA for monitoring and debugging.

2. The method of claim 1,

the higher the change frequency of the signal to be observed in the current time period is, the higher the frequency of the corresponding sampling clock is, and the operating state of the signal to be observed is determined according to the signal characteristics of the signal to be observed and/or the signal characteristics of a predetermined related signal of the signal to be observed.

3. The method according to claim 1 or 2,

the clock adjusting module comprises a phase-locked loop circuit, a multiplexer and a selection register, wherein the input end of the phase-locked loop circuit acquires a reference clock, and each output end of the phase-locked loop circuit respectively outputs sampling clocks with different frequencies, each output end of the phase-locked loop circuit is respectively connected with the input end of the multiplexer, the selection register gates one path of the multiplexer according to a clock selection signal, and the sampling clock of one input end of the multiplexer is provided for the sampling module.

4. The method of claim 3,

and the clock selection signal of the selection register is input from the FPGA on line, or the selection register selects one group from a plurality of groups of clock selection signals stored in advance according to a preset strategy.

5. The method of claim 4,

and the clock selection signal of the selection register is transmitted to the selection register through a boundary scan chain built in the FPGA, or the clock selection signal of the selection register is transmitted to the selection register through a dynamically configurable port DRP of the FPGA.

6. The method of claim 3,

and each input end of the multiplexer is connected with each output end of the phase-locked loop circuit and is also connected with an off-chip clock input from the outside of the FPGA, and the sampling clock provided by the multiplexer to the sampling module is one of a plurality of sampling clocks with different frequencies generated by the off-chip clock and the reference clock.

7. The method of claim 6,

the off-chip clock is a test clock signal used by a boundary scan port of the boundary scan chain.

8. The method of claim 6,

the reference clock is a clock signal generated by the user circuit, and the off-chip clock is also connected to the user circuit and used for generating the reference clock.

9. The method of claim 6,

the user circuit is internally provided with a clock tree, an original clock source and the off-chip clock are respectively connected with two input ends of an alternative selector, and the output end of the alternative selector drives a logic circuit for generating the signal to be observed through the clock tree.

10. The method of claim 9, wherein during operation of the subscriber circuit:

and controlling the alternative selector to gate a logic circuit driven by the off-chip clock and used for generating the signal to be observed, controlling the multiplexer to gate and provide the off-chip clock to the sampling module, and adjusting the off-chip clock to a preset frequency to realize debugging of the user circuit.

11. The method of claim 1,

the FPGA forms a user circuit by utilizing a first class of resources based on a first part corresponding to the user circuit in the configuration code stream and forms a monitoring circuit by utilizing a second class of resources based on a second part corresponding to the monitoring circuit in the configuration code stream;

the first type of resource and the second type of resource respectively represent programmable logic resources of different parts in the FPGA, the first type of resource is a programmable logic resource used for realizing the user circuit when the user circuit is not debugged in the FPGA, and the hardware structures of the programmable logic resources with the same resource type in the first type of resource and the second type of resource are the same.

Background

When a user circuit is implemented on an FPGA and normally operates on the FPGA, in order to determine that an operation process of the user circuit on the FPGA is correct and conforms to a design concept, it is generally required to observe behaviors or waveforms of certain specific signals inside the user circuit. In order to implement this function, the current practice is to add a debugging circuit on the FPGA, and when the user circuit normally operates on the FPGA, the debugging circuit is used to sample a signal to be observed of the user circuit and output the signal to the FPGA to perform real-time observation and monitoring, thereby implementing corresponding debugging.

In practical implementation, a signal to be observed is generally sampled and then stored according to a sampling clock, and the stored data is output to the outside of the FPGA for observation after the sampling is finished. In many debugging scenes, some time periods of a signal to be observed are debugging critical time periods, some time periods of the signal to be observed are debugging non-critical time periods, the signal of the signal to be observed in the non-critical time periods hardly changes, but the signal to be observed still needs to be sampled in the non-critical time periods according to debugging requirements, at the moment, a plurality of continuously sampled data are the same, and the significance of the repeatedly sampled data is not great. And because the monitoring circuit needs to store and output the sampled data, the total number of samples in the sampling process is limited by the storage capacity, and the total number of samples is also limited under the condition of limited storage capacity, wherein if more meaningless data for repeated sampling exists, the debugging efficiency is low.

Disclosure of Invention

The invention provides an FPGA online debugging method with dynamically variable sampling frequency aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

an FPGA online debugging method with dynamically variable sampling frequency comprises the following steps:

when debugging a user circuit, loading a configuration code stream corresponding to a global circuit consisting of the user circuit and a monitoring circuit to an FPGA (field programmable gate array), wherein the FPGA utilizes programmable logic resources to realize the user circuit and the monitoring circuit based on the configuration code stream, and the monitoring circuit is connected with the user circuit;

the monitoring circuit comprises a clock adjusting module, a sampling module, a sample storage module and a sample output module, wherein in the operation process of the user circuit, the clock adjusting module provides a sampling clock which corresponds to and is matched with the operation state of a signal to be observed of the user circuit in the current time period for the sampling module, the frequency of the sampling clock which corresponds to at least two different operation states and different operation states of the signal to be observed in the operation process of the user circuit is different, the sampling module samples the signal to be observed according to the sampling clock provided by the clock adjusting module and stores the signal in the sample storage module, and after the sampling is completed, the sample output module utilizes a boundary scan chain of the built-in FPGA to transmit the signal to the outside of the FPGA for monitoring and debugging.

The further technical scheme is that the higher the change frequency of the signal to be observed in the current time period is, the higher the frequency of the corresponding sampling clock is, and the running state of the signal to be observed is determined according to the signal characteristics of the signal to be observed and/or the signal characteristics of the preset associated signal of the signal to be observed.

The clock adjusting module comprises a phase-locked loop circuit, a multiplexer and a selection register, wherein the input end of the phase-locked loop circuit acquires a reference clock, and the output ends of the phase-locked loop circuit respectively output sampling clocks with different frequencies, the output ends of the phase-locked loop circuit are respectively connected with the input end of the multiplexer, the selection register gates one path of the multiplexer according to a clock selection signal, and the sampling clock of one input end of the multiplexer is provided for the sampling module.

The further technical scheme is that clock selection signals of the selection register are input through an FPGA external line, or the selection register selects one group from a plurality of groups of clock selection signals stored in advance according to a preset strategy.

The further technical scheme is that a clock selection signal of the selection register is transmitted to the selection register through a boundary scan chain built in the FPGA, or the clock selection signal of the selection register is transmitted to the selection register through a dynamically configurable port DRP of the FPGA.

The further technical scheme is that each input end of the multiplexer is connected with each output end of the phase-locked loop circuit and is also connected with an off-chip clock input from the outside of the FPGA, and the sampling clock provided by the multiplexer to the sampling module is one of a plurality of sampling clocks with different frequencies generated by the off-chip clock and the reference clock.

The further technical scheme is that the off-chip clock is a test clock signal used by a boundary scan port of the boundary scan chain.

The reference clock is a clock signal generated by the user circuit, and the off-chip clock is also connected to the user circuit and used for generating the reference clock.

The further technical scheme is that a clock tree is arranged in the user circuit, an original clock source and an off-chip clock are respectively connected with two input ends of the alternative selector, and an output end of the alternative selector drives a logic circuit for generating a signal to be observed through the clock tree.

The further technical scheme is that in the operation process of the user circuit:

and controlling the alternative selector to gate a logic circuit driven by an off-chip clock and used for generating a signal to be observed, controlling the multiplexer to gate to supply the off-chip clock to the sampling module, and adjusting the off-chip clock to a preset frequency to realize debugging of the user circuit.

The FPGA forms a user circuit by utilizing a first type of resource based on a first part corresponding to the user circuit in the configuration code stream and forms a monitoring circuit by utilizing a second type of resource based on a second part corresponding to the monitoring circuit in the configuration code stream;

the first type of resource and the second type of resource respectively represent programmable logic resources of different parts in the FPGA, the first type of resource is the programmable logic resource which is used for realizing a user circuit when the user circuit is not debugged in the FPGA, and the hardware structures of the programmable logic resources with the same resource type in the first type of resource and the second type of resource are the same.

The application discloses an FPGA online debugging method with dynamically variable sampling frequency, which utilizes a clock adjusting module in a monitoring circuit to adjust a sampling clock of a sampling module, so that the sampling module samples a signal to be observed by adopting the corresponding sampling clock in different time periods to adapt to the running state of the signal to be observed, thereby reducing invalid data with unchanged sampling repetition on the premise of ensuring that the signal change is monitored, and improving the monitoring and debugging efficiency.

The clock adjusting module can also provide an off-chip clock for the sampling module to use, and the running speed can be controlled by controlling the frequency of the off-chip clock, so that special debugging requirements such as single-step running can be met.

Drawings

Fig. 1 is a schematic diagram of a connection structure of a subscriber circuit and a monitoring circuit in the present application.

Fig. 2 is a waveform diagram illustrating the variation of the sampling clock according to the operation state of the signal to be observed.

FIG. 3 is a schematic diagram of the connection of the subscriber circuit and the monitoring circuit in one embodiment.

Fig. 4 is a schematic diagram of the connection of the subscriber circuit and the monitoring circuit in another embodiment.

Fig. 5 is a schematic diagram of the connection of the subscriber circuit and the monitoring circuit in another embodiment.

FIG. 6 is a schematic diagram of the arrangement of programmable logic resources within the FPGA.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses an FPGA online debugging method with dynamically variable sampling frequency, which comprises the following implementation processes:

when the user circuit is debugged, the configuration code stream corresponding to the global circuit formed by the user circuit and the monitoring circuit is loaded on the FPGA. The global circuit in the application is a whole circuit structure which needs to be realized by using programmable logic resources on the FPGA and operates on the FPGA, the global circuit at least comprises a user circuit, and the user circuit is a circuit structure which is used for realizing a user design function in the global circuit. When debugging the user circuit, the global circuit includes, in addition to the user circuit, a monitoring circuit connected to the user circuit, and the monitoring circuit is a circuit structure in the global circuit for implementing a signal monitoring function for the user circuit, and in this case, the global circuit is composed of the user circuit and the monitoring circuit. Those skilled in the art know that after the global circuit is input, the configuration code stream corresponding to the global circuit can be generated through steps of synthesis, boxing, layout, wiring, timing analysis and the like, and the intermediate steps are not described in detail in this application.

The FPGA utilizes programmable logic resources to realize a user circuit and a monitoring circuit based on the configuration code stream, and the monitoring circuit is connected with the user circuit. Referring to fig. 1, the monitoring circuit includes a clock adjusting module, a sampling module, a sample storage module, and a sample output module. In the operation process of the user circuit, the clock adjusting module provides a sampling clock which corresponds to and is matched with the operation state of the signal Sig to be observed of the user circuit in the current time period for the sampling module. At least two different operation states exist in the operation process of the user circuit of the signal Sig to be observed, and the frequencies of sampling clocks corresponding to the different operation states are different. For example, in fig. 1, the signal Sig to be observed has three different operating states during the operation of the user circuit, so that the clock adjusting module provides three sampling clocks CLK1, CLK2 and CLK3 with different frequencies to the sampling module, and the frequency of each sampling clock is correspondingly matched with one state of the signal Sig to be observed.

And the sampling module samples the signal to be observed according to the sampling clock provided by the clock adjusting module and stores the signal in the sample storage module. And after sampling is finished, the sample output module is transmitted to the outside of the FPGA by utilizing a boundary scan chain built in the FPGA to carry out monitoring and debugging. The sample output module outputs the stored data according to a first-in first-out sequence, the sample output module is mainly realized by a shift register, the sampling is completed when the data to be sampled is configured to reach the total number of samples, and the total number of samples does not exceed the storage capacity of the sample storage module.

In the application, in the operation process of the user circuit, the change frequencies of the signal to be observed in different time periods are different, the signal to be observed continuously operates for a period of time in each operation state, and the different operation states represent the different change frequencies of the signal to be observed in different continuous time periods. The signal to be observed has at least two different operation states in the whole time sequence, the operation states corresponding to two adjacent continuous time periods are different, and a plurality of same operation states which are discontinuous in time can exist. As shown in fig. 2, the signal to be observed exists in two states, i.e., the operating state 1 and the operating state 2, which may be generated in a staggered manner, for example, the operating state 1 appears first, and the operating state 2 is switched to the operating state 1 after a period of time.

The higher the change frequency of the signal to be observed represented by the running state is, the higher the frequency of the corresponding sampling clock is, that is, the faster the signal to be observed changes in a continuous period of time is, the higher the frequency of the sampling clock is used for sampling so as to accurately monitor the change of the signal to be observed. And the lower the change frequency of the signal to be observed represented by the running state is, the lower the sampling clock is used for sampling, so that the quantity of sampled repeated invalid data can be reduced on the premise of accurately monitoring the change of the signal to be observed.

The different operating states of the signals to be observed are determined on the basis of the signal characteristics of certain signals. In an alternative embodiment, the operating state of the signal to be observed is determined according to the signal characteristic of the signal to be observed, i.e. by the signal to be observed itself, and it is determined that the frequency of change of the subsequent time interval will become higher when the signal to be observed meets a first predetermined condition, and it is determined that the frequency of change of the subsequent time interval will become lower when, for example, a second predetermined condition is met. For example, in fig. 2, for a signal Sig to be observed at an interconnection interface between two modules, an operation state may be determined by detecting whether a signal to be observed appears, and when it is determined that a signal to be observed appears, it is switched from a characterized operation state 1 with a low change frequency to a characterized operation state 2 with a high change frequency, and then the corresponding sampling clock is switched from the sampling clock CLK1 corresponding to the operation state 1 to the sampling clock CLK2 corresponding to the operation state 1 with a higher frequency.

In another alternative embodiment, the operating state of the signal to be observed is determined according to the signal characteristics of a predetermined associated signal of the signal to be observed, i.e. by other signals associated with the signal to be observed, in particular similar to the above. For example, when an enable signal of a certain signal Sig to be observed occurs, the signal to be observed has a series of signal changes, and it may be determined that the operation state 1 with a low change frequency of the representation is switched to the operation state 2 with a high change frequency of the representation when the enable signal of the signal to be observed is detected.

It should be noted that the different change frequencies represented by the different operating states are only relative to each other, and not an absolute value of the change frequencies, such as in the above example, it can only be shown that the change frequency represented by the operating state 2 is higher than the change frequency represented by the operating state 1, and it cannot be generally determined what the change frequency is in two consecutive periods.

IN one embodiment, as shown IN fig. 3, the clock adjusting module includes a phase-locked loop circuit PLL having an input terminal acquiring the reference clock CLK _ IN and respective output terminals outputting sampling clocks CLK1, CLK2, and CLK3 of different frequencies, a multiplexer MUX, and a selection register. And each output end of the phase-locked loop circuit PLL is respectively connected with the input ends of the multiplexers MUX, and the number of the input ends of the multiplexers MUX is not less than that of the output ends of the phase-locked loop circuit PLL. The selection register controls the multiplexer MUX according to the clock selection signal SEL and gates one path of the multiplexer MUX, and therefore the sampling clock of one input end of the multiplexer MUX is supplied to the sampling module. In fig. 3, for example, the multiplexer MUX is a four-out-one multiplexer, the selection register inputs a two-bit control signal to the MUXF4, and selects CLK1 from among CLK1, CLK2, and CLK3, which are input, and supplies the selected signal to the sampling block.

IN another embodiment, as shown IN fig. 4, on the basis of fig. 3, each input terminal of the multiplexer MUX is connected to an off-chip clock CLK _ OUT inputted from outside of the FPGA IN addition to each output terminal of the phase-locked loop circuit PLL, and the sampling clock provided by the multiplexer MUX to the sampling module is one of a plurality of sampling clocks of different frequencies generated by the off-chip clock CLK _ OUT and the reference clock CLK _ IN. Optionally, the off-chip clock CLK _ OUT is any externally input clock signal, or a test clock signal used by a boundary scan port of a boundary scan chain.

IN the embodiment shown IN fig. 4, when the reference clock CLK _ IN is the clock signal generated by the user circuit, the off-chip clock CLK _ OUT is also connected to the user circuit and used to generate the reference clock CLK _ IN, i.e., the off-chip clock CLK _ OUT can be input back into the user circuit to become one of the sources of the reference clock CLK _ IN. Specifically, the user circuit has a built-IN clock tree, the original clock source CLK0 and the off-chip clock CLK _ OUT are respectively connected to two input terminals of the alternative selector MUXF2, and the output terminal of the alternative selector MUXF2 outputs the reference clock CLK _ IN through the clock tree, as shown IN fig. 5.

In addition, as shown in fig. 5, the output terminal of the one-of-two selector MUXF2 is also connected to and drives the logic circuit for generating the signal to be observed, so that the off-chip clock CLK _ OUT can also drive the logic circuit for generating the signal to be observed through the clock tree. In this embodiment, since both the logic circuit generating the signal to be observed and the monitoring circuit can select the off-chip clock CLK _ OUT, the operation speed can be controlled by controlling the frequency of the off-chip clock CLK _ OUT to meet specific debugging requirements, one typical debugging requirement is Single Step (Single Step), specifically, the alternative selector MUXF2 is controlled to gate a path driving the logic circuit generating the signal to be observed by the off-chip clock CLK _ OUT, the multiplexer MUX is controlled to gate the off-chip clock CLK _ OUT to the sampling module, and the off-chip clock CLK _ OUT is adjusted to a predetermined frequency to realize debugging of the user circuit.

In any of the configurations of fig. 3-5, the selection register has two following ways to control the multiplexer MUX:

in an alternative implementation, the clock select signal SEL for selecting the register is input off-line from the FPGA, as shown in fig. 4 and 4 for example. Optionally, the clock selection signal SEL of the selection register is transmitted to the selection register via a boundary scan chain built in the FPGA, or the clock selection signal SEL of the selection register is transmitted to the selection register via a dynamically configurable port DRP of the FPGA.

In this embodiment, another alternative implementation is that the selection register selects one set from several sets of clock selection signals stored in advance according to a predetermined strategy. A common predetermined strategy, such as polling, uses each of the previously stored clock selection signals sequentially, and the timing for switching the clock selection signals can be set by another controller.

In an embodiment of the present application, besides the implementation of the global circuit in the FPGA according to a conventional method, the implementation can be realized by the following method:

in the method provided in this embodiment, the programmable logic resources inside the FPGA are divided into two types in advance, the first type of resources and the second type of resources respectively represent programmable logic resources of different portions inside the FPGA, the user circuit and the monitoring circuit have respective dedicated one type of programmable logic resources, and the user circuit and the monitoring circuit are implemented by respective corresponding one type of resources. Therefore, the first type of resources are programmable logic resources used for realizing the user circuit when the user circuit is not debugged in the FPGA, and are also programmable logic resources used for realizing the user circuit when the user circuit is debugged in the FPGA, and the second type of resources are programmable logic resources used for realizing the monitoring circuit when the user circuit is debugged in the FPGA. The resource type and the number of the basic modules contained in each type of resource are determined according to the estimated scale of the corresponding circuit, generally, the scale of the user circuit is larger than that of the monitoring circuit, and therefore, the resource scale of the programmable logic resource contained in the first type of resource corresponding to the user circuit is larger than that of the second type of resource corresponding to the monitoring circuit. The hardware structures of the programmable logic resources having the same resource type in the first type of resource and the second type of resource are the same, for example, the hardware structures of the CLBs in the first type of resource and the CLBs in the second type of resource are the same, that is, the hardware structures of the programmable logic resources inside the FPGA are not modified, but the programmable logic resources are only divided.

The programmable logic resource inside the FPGA comprises a plurality of basic modules and interconnection resources (INT) distributed around each basic module, each basic module is a programmable logic resource of a resource type, the resource type of the programmable logic resource mainly comprises a CLB (basic logic unit), a BRAM (Branch), an IOB (input/output interface), a DSP (digital signal processor), a PC (personal computer) and the like, and each resource type comprises a plurality of basic modules. For example, in fig. 6, the programmable logic resource inside the FPGA includes 15 basic modules belonging to three different resource types, among which there are 12 CLBs, 2 DSPs, and 1 BRAM. Each basic logic unit CLB includes several logic parts therein, and the logic parts included therein mainly include LUTs (look-up tables) and REGs (registers). The basic modules are arranged according to a certain structure, such as the existing conventional Column-Based FPGA architecture, wherein each Column is a basic module with the same resource type, for example, a CLB Column is full of one chip Column from top to bottom in a CLB arrangement, and a BRAM Column is full of one chip Column from top to bottom in a BRAM arrangement.

The configuration code stream corresponding to the global circuit can be generated based on the divided first-class resources and second-class resources, when the user circuit is debugged, the global circuit is composed of the user circuit and the monitoring circuit, and the configuration code stream comprises a first part which is generated based on the first-class resources and corresponds to the user circuit and a second part which is generated based on the second-class resources and corresponds to the monitoring circuit. When the user circuit is not debugged, the global circuit is only formed by the user circuit, at the moment, the configuration code stream is generated based on the first type of resources in the FPGA and corresponds to the user circuit, so the first type of resources for realizing the user circuit when the user circuit is debugged are used, and meanwhile, the programmable logic resources for realizing the user circuit when the user circuit is not debugged are also used.

Which programmable logic resources in the FPGA belong to the first class of resources and which belong to the second class of resources are pre-divided, optionally, the present embodiment provides several different dividing manners as follows:

in the first mode, the first type of resources and the second type of resources share the basic module at the same position, and the mode mainly aims at the basic module with the resource type of the basic logic unit CLB, namely, a part of logic components contained in at least one basic logic unit in the FPGA belong to the second type of resources, and the other part of logic components belong to the first type of resources. When dividing the logic components in one basic logic unit, the logic components can be divided according to any one of the following conditions: (1) and randomly selecting a part of logic parts in the basic logic unit to be reserved as second-class resources and the rest logic parts as first-class resources. (2) And selecting a part of logic parts in the basic logic unit at intervals to be reserved as the second type of resources, and taking the rest logic parts as the first type of resources.

Because the CLB internally includes two types of logic components, namely LUT and REG, when a part of logic components included in a basic logic unit is reserved as the second type of resources, the following situations are included:

(a) only a part of the LUTs or the entire LUT is reserved as the second type of resources, all REGs and possibly unselected LUTs as the first type of resources.

(b) Only a part of REGs or all REGs are reserved as the second type of resource, all LUTs and possibly non-selected REGs as the first type of resource.

(c) And simultaneously selecting a part of LUTs and a part of REGs as the second type of resources and the rest of the LUTs and REGs which are not selected as the first type of resources. This is the most common way, e.g. a CLB includes 8 LUTs and 16 REGs inside, then 2 LUTs and 4 REGs can be divided to belong to the second class of resources, and the remaining 6 LUTs and 12 REGs belong to the first class of resources.

When part of the LUT and part of the REG are selected as the second type of resource, the LUT and the REG can both adopt random selection reservation, or both adopt interval selection reservation, or one adopts random selection reservation and the other adopts interval selection reservation. When the LUT and the REG adopt interval selection reservation, the intervals adopted by the LUT and the REG are the same or different, for example, when the LUT is selected in interval, one reservation is selected from every 1 LUT as a second type of resource; when the REGs are selected at intervals, one reserved resource is selected from every 2 LUTs as the second type resource.

And secondly, classifying the classes of the programmable logic resources according to the positions of the programmable logic resources, wherein all the programmable logic resources in the preset area of the FPGA belong to the second class of resources, and the programmable logic resources in the other areas except the preset area belong to the first class of resources. Unlike the first approach, in this approach, each class of resources has exclusive ownership of a basic unit at a location, i.e., when a CLB is partitioned into resources of the second class, all LUTs and REGs within the CLB belong to the resources of the second class. The preset area has a plurality of different meanings, respectively corresponds to different division modes, and is classified as follows:

in the first category, a predetermined area includes only one basic module: (1) the predefined area is the area encompassed by one basic module, in which case only one basic module belonging to one resource type is included in the predefined area. For example, a region in which a CLB is located is divided into the second type of resources as a predetermined region, or a region in which a BRAM is located is divided into the second type of resources as a predetermined region.

In the second category, a predetermined area includes at least two basic modules, which may include the following cases:

(2) the predetermined area is an area included in each row structure or column structure within the FPGA, and in this case, the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types. It is more common to use each Column structure in the FPGA as a predetermined area, and in the Column-Based FPGA architecture, the resource types of the basic modules in the same Column structure are the same, so Based on this, the predetermined area includes a plurality of basic modules belonging to the same resource type.

(3) The predetermined area is an area included in one clock domain, in which case the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types.

(4) The predetermined area is located at a predetermined position and has a predetermined area range, in which case the predetermined area includes a plurality of basic modules belonging to the same resource type or includes a plurality of basic modules belonging to at least two different resource types. That is, the predetermined area is divided by self-defining according to needs, and the predetermined position can be selected from any suitable position according to needs, such as the lower left corner of the whole slice, the center of the whole slice, the upper right corner of the whole slice, the highest line/lowest line of the clock domain, and the like. The predetermined area range may also be configured with a suitable size as required, for example, the predetermined area range is configured to include 8 × 6 CLBs.

In practice, all programmable logic resources in a predetermined area may be reserved for the second type of resources. Or, all programmable logic resources in a plurality of predetermined areas are reserved for the second type of resource, and a plurality of predetermined areas at different positions are included in the FPGA, wherein the position of the BRAM is usually close to the corresponding CLB in the same type of resource or close to the boundary of the clock domain. In general, the first type of resource and the second type of resource each include basic modules of a plurality of resource types, and in the above case (1), one predetermined area includes only one basic module of one resource type, so that especially when the area range of a single predetermined area is as in the above case (1), a plurality of predetermined areas are generally included in the FPGA, and similarly, when the area range of a single predetermined area is as in the above cases (2), (3) and (4), a plurality of predetermined areas are also generally included in the FPGA.

When a plurality of predetermined areas are included in the FPGA, the plurality of predetermined areas are located at different positions, each predetermined area contains one or more basic modules, the basic modules contained in each predetermined area belong to one or more resource types, each predetermined area contains basic modules of the same resource type, or at least two predetermined areas exist that contain basic modules of different resource types, such as only a CLB in one predetermined area and only a BRAM in another predetermined area.

Each of the predetermined regions includes the same region range as any one of the above (1) to (4), or at least two predetermined regions having different region ranges exist, where two predetermined regions having the same resource type have different region ranges, for example, one predetermined region includes only one CLB in units of CLBs, and another predetermined region includes 8 × 6 CLBs in units of customized predetermined region ranges. Alternatively, two predefined zones with different resource types have different zone ranges, which is more common practice, for example, one predefined zone includes 8 × 6 CLBs in the unit of customized predefined zone range, and the other predefined zone includes 1 BRAM in the unit of BRAM Column.

The plurality of predetermined regions in the FPGA are randomly distributed in the FPGA or are distributed in the FPGA at intervals, when the plurality of predetermined regions are distributed in a partitioned manner, all the predetermined regions may be sequentially distributed at intervals, or more commonly, the predetermined regions containing the same resource type and having the same region range form a group, the predetermined regions in each group are distributed at intervals, and the intervals adopted by different groups are the same or different. For example, 10 predetermined regions in units of CLBs form a group, and the interval between every two predetermined regions is 128 CLBs; the method comprises the following steps that 8 preset regions with CLB columns as units form a group, and the interval between every two preset regions is 64 CLB columns; the method comprises the following steps that 5 preset areas with clock domains as units form a group, and the interval between every two preset areas is 12 clock domains; the 3 preset regions with the BRAM Column as the unit form a group, and the interval between every two preset regions is 2 BRAM columns. It can be seen that the predetermined areas containing different types of resources and/or different coverage areas may be spaced at the same or different intervals in a spaced distribution.

The FPGA in the application can be a single-die FPGA or a multi-die FPGA, and the multi-die FPGA comprises a plurality of FPGA dies with a connection relation. Whether a single-die FPGA or a multi-die FPGA is adopted, the first type of resources and the second type of resources can be divided for the programmable logic resources on the FPGA by adopting any one of the methods provided by the first mode or the second mode. For a single-die FPGA, the first type of resources and the second type of resources obtained by division are located on the same die. For the multi-die FPGA, each class of resources obtained by division respectively comprises programmable logic resources on one or more dies, namely the predetermined area is only positioned on one FPGA die or at least two FPGA dies respectively comprise the predetermined area, and the dies covered by the two classes of resources are the same or different. In this embodiment, in the second mode, for the multi-die FPGA, when all the programmable logic resources in the predetermined area of the multi-die FPGA are divided into the second type of resources, the predetermined area is located on the same FPGA die in the multi-die FPGA, that is, the programmable logic resources on one FPGA die are specially reserved for the second type of resources, and the programmable logic resources on other FPGA dies are all divided into the first type of resources. It should be noted that, if the programmable logic resource of one FPGA bare chip cannot meet the resource requirement of the required second type of resource, the programmable logic resources on the plurality of FPGAs may also be reserved for the second type of resource, but in an actual situation, because the circuit scale of the monitoring circuit is not too large, the resource requirement of the second type of resource is usually not too large, and the programmable logic resource on one FPGA bare chip can meet the requirement.

In the above embodiments, the programmable logic resources included in the predetermined area may be the same as the programmable logic resources included in the FPGA die, that is, all the programmable logic resources on the FPGA die are all divided into the second type of resources. Or, the programmable logic resources included in the predetermined area are less than the programmable logic resources included in the FPGA die, that is, only part of the programmable logic resources on the FPGA die are divided into the second type of resources, and the rest of the programmable logic resources on the FPGA die can be divided into the first type of resources, so that part of the first type of resources and all the second type of resources share the same FPGA die. For example, a multi-die FPGA includes 4 FPGA dies having a connection relationship, which are respectively denoted as a die 1, a die 2, a die 3, and a die 4, and an exemplary way is that the second type of resource includes all programmable logic resources on the die 1, and the first type of resource includes all programmable logic resources on three dies, that is, the die 2, the die 3, and the die 4; another exemplary way is that the second type of resource includes a portion of the programmable logic resources on die 1, and the first type of resource includes the remaining other programmable logic resources on die 1 and all of the programmable logic resources on three die, namely die 2, die 3, and die 4. In this embodiment, the first type of resource sharing the same FPGA die with the second type of resource is used to form a predetermined circuit portion in the user circuit, the predetermined circuit portion is a circuit portion located on a non-critical path in the user circuit configured in advance, and the non-critical path is a path where a timing margin reaches a preset threshold, so that even if the monitoring circuit has some influence on the user circuit, the behavior of the user circuit is not substantially changed.

It should be noted that, when the programmable logic resources are divided into two types, the packing constraint needs to be satisfied, especially when the first type of resources and the second type of resources share the CLBs at the same position, the CLB packing constraint needs to be considered to be satisfied, for example, when the monitoring circuit is scattered and respectively added to the CLBs to occupy the logic components belonging to the second type of resources, each CLB is added with at most 2 clock signals, and the REG of the monitoring circuit needs to be connected with one clock signal, so that the REG in the monitoring circuit can only be added to the CLBs with at least one spare clock signal. Then, the configuration code stream can be generated by normally performing the processes of layout and wiring and the like.

And then when the FPGA utilizes the programmable logic resources to realize the user circuit and the monitoring circuit based on the configuration code stream, the first part corresponding to the user circuit in the configuration code stream forms the user circuit based on the first type of resources, and the second part corresponding to the monitoring circuit in the configuration code stream forms the monitoring circuit based on the second type of resources, so that the user circuit and the monitoring circuit are mutually independent.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.