1. A method for analyzing wafer test data is used for acquiring and analyzing the wafer test data, and is characterized by comprising the following steps:

s1, obtaining wafer test data of a plurality of batches;

s2, wafer test data are distinguished according to the catalog classification information, distinguished wafer test data storage paths are recorded, and catalog classification filing is carried out;

s3, according to the classification information of the target directory, indexing the data path of the corresponding wafer test data from the directory, extracting the wafer test data, and merging the wafer test data into a target data set according to the target parameters;

and S4, carrying out view construction and view analysis on the target data set, and/or carrying out data statistical analysis.

2. The method for analyzing wafer test data as claimed in claim 1, wherein the wafer test data is obtained from FTP data provided by a single or multiple suppliers in step S1, the FTP data includes more than one project data, and the project data includes more than one lot of wafer test data.

3. The method of claim 1, wherein the catalog classification information comprises one or more of item number, program name, supplier name, production lot number, sheet number, and test time.

4. The method for analyzing wafer test data according to claim 1, wherein in step S2, after wafer test data are classified according to the catalog classification information, duplicate wafer test data are deleted.

5. The method for analyzing wafer test data according to claim 1, wherein in step S3, the target parameter is one or more of a product model, a wafer number, a production program name, a good product number, abnormal BIN data, and a test time.

6. The method for analyzing wafer test data as claimed in claim 1, wherein in step S4, when performing the view construction and view analysis on the target data set, the wafer test data in the target data set is constructed into a graph according to the timing or the combination of the timing and the production procedure, and used for analyzing the wafer yield or the lot yield or the abnormal item information.

7. The method as claimed in claim 1, wherein in step S4, when performing statistical data analysis on the target data set, the wafer test data in the data set are merged and sorted according to a single variable for comparison analysis.

8. An analysis platform for wafer test data, used for obtaining and analyzing wafer test data, the platform comprising:

the catalog module is used for acquiring wafer test data of a plurality of batches, distinguishing the wafer test data according to catalog classification information, recording distinguished wafer test data storage paths and carrying out catalog classification filing;

the data integration module is used for extracting wafer test data from a data path for indexing the corresponding wafer test data in the catalog according to the target catalog classification information and merging the wafer test data into a target data set according to target parameters;

and the analysis module comprises a view analysis module capable of carrying out view construction and view analysis based on the target data set and/or an engineering analysis module capable of carrying out data statistical analysis based on the target data set.

9. An electronic device comprising a processor and a memory, the memory storing computer readable instructions which, when executed by the processor, perform the steps of the method of any one of claims 1 to 7.

10. A storage medium on which a computer program is stored, characterized in that the computer program, when being executed by a processor, performs the steps of the method as claimed in any one of the claims 1 to 7.

Background

The testing of integrated circuits includes wafer testing before packaging (Circuit testing) and finished product testing after packaging (Final Test).

Currently, Wafer testing is performed by probing each Die (Die) on a chip (Wafer) with a Probe (Probe) contact (Pad), a start signal is sent out to start testing through an interface, a classification signal is sent back to a detector after testing is completed, failed products outside the range of qualified lines of various parameters preset in a testing program are screened out and rejected, and a testing system can output Wafer testing data of each LOT, including yield of each LOT of a single LOT and BIN information thereof.

However, the existing wafer test system only records the wafer test data, and cannot perform effective integrated analysis on the data after recording, so that an engineer is difficult to perform analysis based on the measured wafer test data to improve the effectiveness of the design end and the manufacturing end, and if the data is directly derived and data sorting is performed through personal experience, the analysis efficiency is severely restricted.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method, a platform, an electronic device, and a storage medium for analyzing wafer test data, which have high analysis efficiency and can automatically extract, integrate, and analyze the wafer test data.

In a first aspect, an embodiment of the present application provides a method for analyzing wafer test data, which is used to acquire and analyze the wafer test data, and the method includes the following steps:

s1, obtaining wafer test data of a plurality of batches;

s2, wafer test data are distinguished according to the catalog classification information, distinguished wafer test data storage paths are recorded, and catalog classification filing is carried out;

s3, according to the classification information of the target directory, indexing the data path of the corresponding wafer test data from the directory, extracting the wafer test data, and merging the wafer test data into a target data set according to the target parameters;

and S4, carrying out view construction and view analysis on the target data set, and/or carrying out data statistical analysis.

According to the analysis method for the wafer test data, the extracted wafer test data can be classified according to the catalog, the wafer test data containing specific target parameters can be extracted quickly for view or engineering analysis, effective information can be provided for a design end and a manufacturing end for failure analysis, and the design and manufacturing yield is improved; the wafer test data containing specific target parameters are retrieved from the directory and integrated into a target data set for analysis, so that the analysis time can be effectively saved; in addition, the wafer test data are filed in a classified mode by utilizing the directory, the process that all the wafer test data need to be traversed again in each analysis is omitted, and the time for acquiring the data in the analysis process can be shortened.

In the method for analyzing wafer test data, in step S1, the wafer test data is obtained from FTP data provided by one or more suppliers, the FTP data includes more than one item data, and the item data includes more than one lot of wafer test data.

The analysis method of the wafer test data comprises the step of analyzing the wafer test data, wherein the catalog classification information comprises one or more of item numbers, program names, supplier names, production lot numbers, sheet numbers and test time.

In the method for analyzing wafer test data, in step S2, after wafer test data are classified according to catalog classification information, duplicate wafer test data are deleted.

In the method for analyzing wafer test data, in step S3, the target parameter is one or more of a product model, a chip number, a production program name, a good product number, abnormal BIN data, and a test time.

In the method for analyzing wafer test data, in step S4, when performing view construction and view analysis on the target data set, the wafer test data in the target data set is constructed into a graph according to a time sequence or a combination of the time sequence and a production procedure, and the graph is used to analyze wafer yield or lot yield or abnormal item information.

In the method for analyzing wafer test data, in step S4, when performing data statistics analysis on the target data set, the wafer test data in the data set are merged and sorted according to a single variable, and are compared and analyzed.

In a second aspect, an embodiment of the present application further provides an analysis platform for wafer test data, configured to acquire and analyze the wafer test data, where the platform includes:

the catalog module is used for acquiring wafer test data of a plurality of batches, distinguishing the wafer test data according to catalog classification information, recording distinguished wafer test data storage paths and carrying out catalog classification filing;

the data integration module is used for extracting wafer test data from a data path for indexing the corresponding wafer test data in the catalog according to the target catalog classification information and merging the wafer test data into a target data set according to target parameters;

and the analysis module comprises a view analysis module capable of carrying out view construction and view analysis based on the target data set and/or an engineering analysis module capable of carrying out data statistical analysis based on the target data set.

According to the analysis platform for the wafer test data, the catalog of the extracted wafer test data is classified through the catalog module, the data integration module is facilitated to quickly extract the wafer test data containing specific target parameters for the analysis module to perform view or engineering analysis, effective information can be provided for a design end and a manufacturing end to perform failure analysis, and the design and manufacturing yield is improved; the data integration module retrieves wafer test data containing specific target parameters from the directory module and integrates the wafer test data into a target data set, and then the target data set is supplied to the analysis module for analysis, so that the analysis time can be effectively saved; in addition, the wafer test data are classified and filed by using the directory module, so that the process of traversing all the wafer test data again in each analysis is avoided, and the time for acquiring the data in the analysis process can be reduced.

In a third aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method provided in the first aspect are executed.

In a fourth aspect, embodiments of the present application provide a storage medium, on which a computer program is stored, where the computer program is executed by a processor to execute the steps in the method provided in the first aspect.

Therefore, the embodiment of the application provides an analysis method, a platform, an electronic device and a storage medium for wafer test data, wherein the analysis method realizes rapid extraction, classification, integration and analysis of the wafer test data, can provide effective information for a design end and a manufacturing end for failure analysis, and improves the design and manufacturing yield; the method for testing the data file path by using the directory index wafer is used as the basis of data integration, so that the data integration and analysis efficiency can be effectively improved, and the calculation and operation loads are reduced.

Drawings

Fig. 1 is a flowchart of a method for analyzing wafer test data according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of an analysis platform for wafer test data according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, fig. 1 is a method for analyzing wafer test data in some embodiments of the present application, for obtaining and analyzing the wafer test data, the method including the following steps:

s1, obtaining wafer test data of a plurality of batches;

specifically, a LOT of wafer test data is wafer test data of a LOT, and a LOT generally includes 24 or 12 wafers; in the analysis process of the wafer test data, each wafer test data may be a wafer test data or an LOT wafer test data, and in this embodiment, is preferably an LOT wafer test data.

The obtained wafer test data can be input from a database or directly obtained from a wafer test system, and correspondingly, the wafer test data comprises the test result of the wafer in the wafer test system, the related production information of the wafer and the like; wherein the test result comprises test time, BIN distribution condition and the like; the related production information includes production information including model number, supplier, item type, lot number, sheet number, test time, production procedure, etc.

The BIN is used for evaluating the standard reaching condition of the corresponding test items of the wafer in the wafer test system.

S2, wafer test data are distinguished according to the catalog classification information, distinguished wafer test data storage paths are recorded, and catalog classification filing is carried out;

after the wafer test data are distinguished and filed to the corresponding catalogues, the wafer test data in the same catalog have the same specific catalog classification information content, and the specific distinguishing method can limit the content of the catalog classification information to distinguish according to the needs.

The catalog is not a folder catalog, but records the storage positions of the wafer test data, namely recording the storage paths of the wafer test data with the same specific catalog classification information content and sorting the wafer test data into a list under the same catalog, and placing the wafer test data with different specific catalog classification information contents under different catalogs, namely different catalogs contain lists of the wafer test data with different specific catalog classification information; the classified wafer test data are not moved in storage positions, and are only marked in a list form in a directory, so that the storage load is reduced, the retrieval and extraction of subsequent data processing are facilitated, and a basis is provided for data analysis.

S3, according to the classification information of the target directory, indexing the data path of the corresponding wafer test data from the directory, extracting the wafer test data, and merging the wafer test data into a target data set according to the target parameters;

the target catalog classification information is specific catalog classification information, and the catalog is classified according to the catalog classification information, so that when wafer test data containing the specific catalog classification information needs to be analyzed, the data under the corresponding catalog can be extracted for analysis and calculation, and the method has the characteristics of accurate data tracking and clear index.

Each target data set formed by merging the wafer test data according to the target parameters can represent a plurality of wafers with the same target parameters, and if the target parameters are qualified, two target data sets respectively representing that the wafer test data are qualified and representing that the wafer test data are unqualified can be merged.

And S4, carrying out view construction and view analysis on the target data set, and/or carrying out data statistical analysis.

In the view analysis process, a plurality of target data sets are arranged into a chart or a graph for view analysis, and the trend of the target parameters according to specific variables can be visually expressed and compared; in the engineering analysis process, a plurality of target data sets are arranged in a list for statistical analysis, and the data integration calculation is facilitated.

According to the analysis method for the wafer test data, the extracted wafer test data can be classified according to the catalog, the wafer test data containing specific target parameters can be extracted quickly for view or engineering analysis, effective information can be provided for a design end and a manufacturing end for failure analysis, and the design and manufacturing yield is improved; the wafer test data containing specific target parameters are retrieved from the directory and integrated into a target data set for analysis, so that the analysis time can be effectively saved; in addition, the wafer test data are filed in a classified mode by utilizing the directory, the process that all the wafer test data need to be traversed again in each analysis is omitted, and the time for acquiring the data in the analysis process can be shortened.

In some preferred embodiments, in step S1, the wafer test data is obtained from FTP data provided by a single or multiple suppliers, the FTP data includes more than one project data, and the project data includes more than one lot of wafer test data; thus, the wafer test data is accompanied by suppliers, project conditions, LOT, and the like.

The analysis method of the embodiment of the application can acquire wafer test data of different suppliers, different projects and different batches, and performs classification and sorting in a catalog classification mode, so that the analysis method of the embodiment of the application can realize dimension data analysis, for example, analysis of wafer yield/BIN distribution conditions of different suppliers in the same project and the same batch, analysis of wafer yield/BIN distribution conditions of different batches in the same project of the same supplier and the like, and further can provide effective information for a design end and a manufacturing end to perform failure analysis, and design and manufacturing yield is improved.

In some preferred embodiments, the catalog classification information includes one or more of an item number, a program name, a supplier name, a production lot number, a sheet number, a test time; specifically, one or more of catalog classification information can be designated for integrated classification during catalog classification, and if the catalog is classified by the item number alone, the wafer test data paths with the same item number are filed in the same catalog; the following example takes wafer test data with item number CP as an example:

designing an entry module by using an updata function (update function) in EXCEL, traversing all FTP data, classifying according to CP types, for example, screening files containing wafer test data with CP2 when wafer test data of CP2 is distinguished, recording file paths of the files with CP2, and recording the files in a list under the same directory, and sorting the files into the following directory list:

the list shows files belonging to the item CP2 in the acquired FTP data, records storage paths of the files, arranges the files in the list under the same directory and finishes data arrangement; the sorting process only records the storage position of the corresponding data file, and does not relate to reading and writing of the data file, so that the storage load can be effectively reduced, and the classification efficiency is improved.

Since the same data may be repeatedly recorded in the actual data acquisition process, and the repeated data may affect the subsequent data analysis effect, in some preferred embodiments, in step S2, after the wafer test data are distinguished according to the catalog classification information, the repeated wafer test data are deleted.

Specifically, after traversing all the FTP data, when screening out the data files conforming to the keyword, if the files have a plurality of files with the same name, determining that the files with the same name are duplicate files, recording the path of the first screened file, and not recording the rest of the duplicate files.

In some preferred embodiments, step S3 includes the following sub-steps:

s31, selecting the information content of the target catalog classification;

s32, obtaining a directory matched with the classification information content of the target directory;

s33, obtaining storage paths of all wafer test data in the catalog;

s34, extracting wafer test data according to the storage path and integrating the wafer test data into a list;

s35, sorting the lists containing the wafer test data according to the target parameters;

and S36, merging the wafer test data items with the same target parameters to form a target data set in a list form.

Specifically, since the catalog classification is classified and filed based on the catalog classification information, the catalog classification information type in the content of the selected catalog classification information in step S31 is consistent with the catalog classification information type used in the catalog classification, such as classification based on the item number CP in the catalog classification, and at this time, step S31 should select a type of item number, such as CP 2.

In some preferred embodiments, in step S3, the target parameter is one or more of a product model, a piece number, a production program name, a good product number, abnormal BIN data, and a test time; taking the following table as an example, the wafer test data in the CP2 project is merged into a data set by taking the test time as the target parameter:

the BIN condition is an important index for verifying the wafer test quality, and comprises an open short circuit test, a static current test, a function test and an N tube current test which are sequentially carried out, when the test is not passed, the test of the next stage is not required, if the corresponding test is not passed, the test is correspondingly classified into BIN2, BIN3, BIN4 and BIN5, and if the corresponding test is passed, the test is classified into BIN 1.

In some preferred embodiments, in step S4, when performing view construction and view analysis on the target data set, the wafer test data in the target data set is constructed into a graph according to the timing or the combination of the timing and the production procedure, and used for analyzing the wafer yield or the lot yield or the abnormal item information; the constructed chart can be a line chart, a bar chart, a curve chart, a pie chart and the like, the occupation ratios of various BINs can be found by utilizing the mean value, and the visual graphical analysis such as the change trend of the product quality seen from the overall yield is realized.

Specifically, the analysis type needs to be selected in combination with the selection of the target parameter in step S3, if the yield of the wafer in the same item on different dates needs to be analyzed, the target parameter should be set as the production date, and the variation trend of the yield is shown by a bar chart, a line chart or a graph; or if the processing quality change of the same program needs to be displayed, the target parameter is set to be a production date with a shorter time interval, for example, the production date is divided by 5 minutes, then a time sequence is taken as an abscissa, the wafer yield of the same program is taken as an ordinate to draw a line graph, yield curves of a plurality of programs can be drawn in the same graph to display the production under different programs, the variation trend of the yield of the generated wafers is realized, the advantages and the disadvantages of different programs are compared, abnormal nodes can be positioned, data support is provided for the failure analysis of abnormal BINs in different projects, effective information can be provided for a design end and a manufacturing end to carry out the failure analysis, and the design and manufacturing yield is improved.

More specifically, when the graph is analyzed, the graph can mark the position of the abnormal data according to the threshold setting, and if the yield curve is lower than a certain threshold, the line segment is marked, that is, the interval where the line segment is located generates more defective products corresponding to the time interval, that is, the time interval corresponding to the defective products and generating more products is indirectly analyzed.

In some preferred embodiments, in step S4, when view construction and view analysis are performed on the target data set, all non-zero graphs are drawn according to preset analysis content, that is, zero graphs are not shown, so as to improve the utilization rate of resource analysis.

In some preferred embodiments, in step S4, when performing data statistics analysis on the target data set, the wafer test data in the data set are merged and sorted according to a single variable, and then are subjected to comparison analysis; specifically, the single variable includes LOT, production program, supplier, etc., so that a certain batch of products can be screened and analyzed to measure various comparison data, such as comparison of wafer test data of the supplier, the same LOT, and different programs, comparison of wafer test data of the same LOT, the same program, and different suppliers, and comparison of wafer test data of the same supplier, the same program, and different LOTs, and specifically, comparison of the wafer test data can be comparison of the first 5 items of wafer yield and abnormal BIN, etc.

Therefore, the analysis method for the wafer test data provided by the embodiment of the application realizes the rapid extraction, classification, integration and analysis of the wafer test data, can provide effective information for a design end and a manufacturing end to perform failure analysis, and improves the design and manufacturing yield.

Referring to fig. 2, fig. 2 is a platform for analyzing wafer test data in some embodiments of the present application, for obtaining and analyzing the wafer test data, the platform including:

the catalog module 201 is used for acquiring wafer test data of a plurality of batches, distinguishing the wafer test data according to catalog classification information, recording storage paths of the distinguished wafer test data, and classifying and archiving the catalogs;

the data integration module 202 is configured to extract wafer test data from a data path indexing the corresponding wafer test data in the directory according to the target directory classification information, and merge the wafer test data into a target data set according to the target parameters;

the analysis module comprises a view analysis module 203 which can perform view construction and view analysis based on the target data set, and/or an engineering analysis module 204 which can perform data statistic analysis based on the target data set.

The analysis platform for wafer test data provided by the embodiment of the application can execute the analysis method to analyze the wafer test data.

According to the analysis platform for the wafer test data provided by the embodiment of the application, the catalog of the extracted wafer test data is classified by the catalog module 201, so that the data integration module 202 can be used for rapidly extracting the wafer test data containing specific target parameters for view or engineering analysis by the analysis module, effective information can be provided for a design end and a manufacturing end for failure analysis, and the design and manufacturing yield is improved; the data integration module 202 retrieves wafer test data containing specific target parameters from the catalog module 201 and integrates the wafer test data into a target data set, and then the target data set is supplied to the analysis module for analysis, so that the analysis time can be effectively saved; in addition, the catalog module 201 is used for classifying and archiving the wafer test data, so that the process of traversing all the wafer test data again in each analysis is avoided, and the time for acquiring the data in the analysis process can be reduced.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure, where the present disclosure provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.

The embodiment of the present application provides a storage medium, and when being executed by a processor, a computer program performs the method in any optional implementation manner of the above embodiment. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In summary, the embodiments of the present application provide an analysis method, a platform, an electronic device, and a storage medium for wafer test data, where the analysis method realizes rapid extraction, classification, integration, and analysis of wafer test data, and can provide effective information for a design end and a manufacturing end to perform failure analysis, thereby improving design and manufacturing yield; the method for testing the data file path by using the directory index wafer is used as the basis of data integration, so that the data integration and analysis efficiency can be effectively improved, and the calculation and operation loads are reduced.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above embodiments are merely examples of the present application and are not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.