The method for analyzing and detecting the open circuit and the short circuit of the PCB design file is characterized by comprising the following steps of:

acquiring a PCB design file and exporting a Gerber file and an IPC file according to the PCB design file, or acquiring the Gerber file and the IPC file;

loading and acquiring pin coordinate data and logic network serial number data in the IPC file, and constructing an IPC network according to the pin coordinate data and the logic network serial number data;

loading the Gerber file and analyzing and calculating a physical network;

projecting the pin coordinates in the IPC file into the physical network;

establishing a mapping relation according to the pin coordinates in the IPC file and the physical network hit by projection, and respectively establishing a first mapping association table and a second mapping association table, wherein the first mapping association table is used for detecting whether the PCB design file has an open circuit, and the second mapping association table is used for detecting whether the PCB design file has a short circuit;

and detecting whether the PCB design file has an open circuit or a short circuit according to the first mapping association table and the second mapping association table, and displaying and storing the PCB design file.

2. The method of claim 1, wherein the first mapping association table is constructed by connecting a KEY and a Value with a logical network number in the IPC network as KEY and a physical network list in the Gerber network as Value.

3. The method according to claim 1, wherein the second mapping association table is constructed by connecting a KEY and a Value with a KEY and a Value as a list of logic network numbers of the IPC network, wherein the KEY and the Value are used as KEY and the list of logic network numbers of the Gerber network.

4. The method of claim 2, wherein traversing a KEY with a Value number greater than one corresponding to each KEY in the first mapping association table determines that the KEY has an open circuit.

5. The method for analyzing and detecting open and short circuits of PCB design files according to claim 3, wherein traversing KEY whose Value number corresponding to each KEY in the second mapping association table is greater than one, and determining that the KEY has a short circuit.

6. The method of claim 1, wherein one Gerber file corresponds to one IPC file when acquiring the Gerber file and the IPC file.

7. The method according to claim 1, wherein an open-short analysis table is established according to the first mapping association table and the second mapping association table and the open-short data, and the open-short analysis table at least includes short circuit quantity statistics and open circuit quantity statistics.

8. The method for analyzing and detecting open circuit and short circuit of PCB design file according to any of claims 1-7, wherein the open circuit analysis table further comprises layer information, the layer information comprises pin coordinate data and logical network number data in the first mapping association table and physical network in the second mapping association table.

The PCB open-short circuit analysis and detection device is characterized by comprising a server and a client, wherein the server runs the open-short circuit analysis and detection method for the PCB design file according to any one of claims 1 to 8, the client is provided with an uploading port, the uploading port is used for a client to upload the PCB design file or the Gerber file and the IPC file to the server, and the server performs open-short circuit analysis on the PCB design file or the Gerber file and the IPC file and transmits the open-short circuit analysis and the IPC file back to the client for display.

An electronic device for analyzing and detecting open and short circuit of PCB, comprising a processor, a memory and a touch screen display, wherein the memory stores the method for analyzing and detecting open and short circuit of PCB design file according to any one of claims 1-8, the processor is used for executing executable commands in the memory, and the touch screen display is used for man-machine interaction.

Background

In the current PCB manufacturing process, the production is usually carried out according to the information provided by the customer, but the information provided by the customer is usually a PCB design file or a Gerber file of the production information. When a file is designed for a PCB, engineering personnel are required to export the Gerber file through PCB design software, then the network condition in the Gerber file is compared roughly manually, and the Gerber file can be found when the obvious network (whether the open circuit and short circuit conditions exist) is inconsistent; when a customer only provides the Gerber file, manual comparison cannot be carried out, if the customer only provides the Gerber file, and the customer only does not have the mother PCB design file as a reference, and does not know whether the submitted Gerber file is modified or damaged in the process before delivery. Therefore, if the error cannot be easily detected directly according to the data provided by the customer, the subsequent PCB production has defects.

Therefore, in order to omit manual comparison operation and greatly improve the identification efficiency, a method for automatically pre-examining open/short circuit defects in the PCB engineering data is required to find the open/short circuit problem in the PCB engineering data.

Disclosure of Invention

The invention aims to provide a method and a device for analyzing and detecting open and short circuit of a PCB design file and electronic equipment aiming at the problems in the prior art.

In order to realize the purpose of the invention, the invention adopts the following technical scheme: the method for analyzing and detecting the open circuit and the short circuit of the PCB design file comprises the following steps:

s100, obtaining a PCB design file and exporting a Gerber file and an IPC file according to the PCB design file, or obtaining the Gerber file and the IPC file;

s200, loading and acquiring pin coordinate data and logic network number data in the IPC file, and constructing an IPC network according to the pin coordinate data and the logic network number data;

s300, loading the Gerber file and analyzing and calculating a physical network;

s400, projecting the pin coordinates in the IPC file to the physical network;

s500, establishing a mapping relation according to the pin coordinates in the IPC file and the physical network hit by projection, and respectively establishing a first mapping association table and a second mapping association table, wherein the first mapping association table is used for detecting whether the PCB design file has an open circuit, and the second mapping association table is used for detecting whether the PCB design file has a short circuit;

s600, detecting whether the PCB design file has an open circuit or a short circuit according to the first mapping association table and the second mapping association table, and displaying and storing the PCB design file.

The working principle and the beneficial effects are as follows: 1. compared with the prior art, the method can ensure that the data acquired from the client can be compared, and can realize the quick search of the positions of short circuit and open circuit by analyzing the IPC file and the Gerber file and establishing a mapping relation, thereby modifying according to the defects, avoiding the occurrence of PCB production errors, having extremely high detection efficiency, greatly shortening the detection time and saving the cost;

2. the method has the advantages that the error and leakage condition existing in manual detection does not exist, the problem of open and short circuit can be detected by 100% through the one-to-one correspondence of the IPC file and the Gerber file, the information required to be provided by a client does not need to be changed, the PCB design file is still provided, or the Gerber file and the IPC file are provided, and the Gerber file and the IPC file can be exported through the PCB design file and are standard files in the field without extra cost.

Further, S501, the logic network number of the IPC network is taken as KEY, the physical network list in the Gerber network is taken as Value, and the KEY and the Value are connected to construct the first mapping association table. The step is equivalent to numbering the logic networks in the IPC network into KEY and corresponding to each value in a physical network list in the Gerber network one by one, so that if two physical networks exist in one KEY, the circuit is equivalent to an open circuit condition, the open circuit position can be quickly found out from the IPC file or the Gerber file through the KEY, the information can be conveniently fed back to a client for modification or a technician for subsequent pertinence modification, manual one-to-one comparison is not needed, and the detection efficiency is greatly improved.

Further, in S502, the corresponding physical network in the Gerber network is taken as KEY, the logical network number list of the IPC network is taken as Value, and the KEY and the Value are connected to construct the second mapping association table. The step is equivalent to numbering the physical networks in the Gerber networks as KEY and corresponding to each value in a logic network list in the IPC network one by one, so that if two logic networks exist in one KEY, the short circuit condition exists in the circuit, the short circuit position can be quickly found out from the IPC file or the Gerber file through the KEY, the short circuit position can be conveniently fed back to a client for modification or the subsequent pertinence of technical personnel for modification, manual one-to-one comparison is not needed, and the detection efficiency is greatly improved.

Further, traversing the KEY with Value quantity greater than one corresponding to each KEY in the first mapping association table, and determining that the KEY has an open circuit. The KEY with the open circuit can be quickly screened out through a common traversal step.

Further, traversing the KEY with Value quantity greater than one corresponding to each KEY in the second mapping association table, and determining that the KEY has a short circuit. The KEY with the short circuit can be quickly screened out through a common traversal step.

Further, when the Gerber file and the IPC file are obtained, one Gerber file corresponds to one IPC file. The Gerber files and the IPC files are in one-to-one correspondence, and orders are also made one by one, so that the situation that one Gerber file corresponds to a plurality of IPC files or one IPC file corresponds to a plurality of Gerber files does not exist, and the situation that whether the Gerber file and the IPC file correspond to each other does not need to be verified, if the Gerber file and the IPC file do not correspond to each other, a plurality of open and short circuits exist in the subsequent steps, and the Gerber file and the IPC file are obviously inconsistent.

Further, S700, an open-short analysis table is established according to the first mapping association table, the second mapping association table, and the open-short data, where the open-short analysis table at least includes short quantity statistics and open quantity statistics. In the step, the results are unified in the open-short circuit analysis table, so that technical personnel can look up the results and perform targeted modification, and customers can look up and modify the results conveniently.

Further, the open-short analysis table further includes layer information, where the layer information includes pin coordinate data and logical network number data in the first mapping association table and a physical network in the second mapping association table. The scheme further facilitates the technical personnel and the client to consult after analysis.

The PCB open-short circuit analysis device comprises a server and a client, wherein the server operates the open-short circuit analysis detection method of the PCB design file, the client is provided with an uploading port, the uploading port is used for a client to upload the PCB design file or the Gerber file and the IPC file to the server, and the server is used for carrying out open-short circuit analysis on the PCB design file or the Gerber file and the IPC file and transmitting the open-short circuit analysis back to the client for display. The device adopting the method also has the effect of greatly improving the detection efficiency without manual comparison one by one.

The PCB open-short circuit analysis electronic equipment comprises a processor, a memory and a touch screen display, wherein the open-short circuit analysis detection method of the PCB design file is stored in the memory, the processor is used for operating an executable command in the memory, and the touch screen display is used for man-machine interaction. The electronic equipment adopting the method also has the advantages that manual comparison is not needed, the detection efficiency is greatly improved, and open-short circuit analysis can be carried out at any time and any place.

Drawings

FIG. 1 is a flow chart of the method of the present invention;

FIG. 2 is a diagram of an IPC file adding interface of the device of the present invention;

FIG. 3 is a schematic diagram of a physical network for the method of the present invention;

FIG. 4 is a mapping relation diagram of an IPC file and a Gerber file in the method of the present invention;

FIG. 5 is a schematic illustration of a first mapping association table and a second mapping association table of the method of the present invention;

FIG. 6 is a schematic diagram of the method of the present invention detecting a short circuit condition;

FIG. 7 is a schematic diagram of the detection of an open circuit condition by the method of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.

Example 1

As shown in fig. 1, the method for analyzing and detecting open/short circuit of PCB design document includes the following steps:

s100, obtaining a PCB design file and exporting a Gerber file and an IPC file or obtaining the Gerber file and the IPC file according to the PCB design file;

in this step, the IPC file is a network aggregate file recording logical relations of the design file, in this embodiment, the IPC-D-356A format, and the IPC-D-356A is a specific format established by the american society of printed circuits, which is a network aggregate file recording logical relations of the design file, a logical network output by the design software in the PCB design file and consistent with the schematic diagram, and a physical network (Gerber file) established by the CAM software for comparison, which can check the Gerber file and the drilling file.

When the Gerber file and the IPC file are obtained, one Gerber file corresponds to one IPC file. The Gerber files and the IPC files are in one-to-one correspondence, and orders are also made one by one, so that the situation that one Gerber file corresponds to a plurality of IPC files or one IPC file corresponds to a plurality of Gerber files does not exist, and the situation that whether the Gerber file and the IPC file correspond to each other does not need to be verified, if the Gerber file and the IPC file do not correspond to each other, a plurality of open and short circuits exist in the subsequent steps, and the Gerber file and the IPC file are obviously inconsistent.

Preferably, in this embodiment, the PCB design file is converted into a Gerber file by a PCB conversion program (Altium Designer software) and an IPC file is generated at the same time.

S200, loading and acquiring pin coordinate data and logic network number data in the IPC file, and constructing the IPC network according to the pin coordinate data and the logic network number data;

in this step, because the IPC file is adopted, the pin coordinate data and the logic network number data in the IPC file can be very conveniently obtained only by loading the IPC file, the pin coordinate data and the logic network number data are read according to the row after loading, the pin coordinate data and the logic network number data are divided into the header information and the network content information, the header information and the network content information are read according to an IPC format protocol, the read result is called key according to the network name, and a hash mapping table is constructed by taking the pin list as a value and is recorded as an IPC _ Map, namely the IPC network.

S300, loading and acquiring a physical network of the Gerber file, and classifying the physical network to construct a Gerber network;

in this step, the Gerber file is loaded to directly read the physical network or the physically connected network, as shown in fig. 3, elements that can be connected together in the graph are classified into the same corresponding physically connected network, specifically, the graph is implemented by a chain conduction algorithm of the existing touch judgment, the physically connected network displays the graph with a color different from that of other parts in the corresponding graph, so as to analogize other corresponding physically connected networks, each physically connected network generates a unique ID during construction, the ID is a key, and the physically connected network list is a value to construct a hash mapping table as GBR _ Map, that is, the Gerber network.

S400, projecting the pin coordinate in the IPC file into a Gerber file;

in this step, the physical network of the projection hit can be corresponding to the pins of the IPC file, so that the pins can be completely in one-to-one correspondence, and the missing is equivalent to the existence of an error in the IPC file or a Gerber file, wherein the pins are from pin coordinate data.

S500, establishing a mapping relation according to pins in the IPC file and a physical network projected and hit in the Gerber file, and respectively establishing a first mapping association table and a second mapping association table, wherein the first mapping association table is used for detecting whether the PCB design file has an open circuit or not, and the second mapping association table is used for detecting whether the PCB design file has a short circuit or not;

s501, taking the logic network number of the IPC network as KEY, taking the physical network list in the Gerber network as Value, and connecting the KEY and the Value to construct a first mapping association table.

S502, taking a corresponding physical network in the Gerber network as KEY, taking a logic network number list of the IPC network as Value, and connecting the KEY and the Value to construct a second mapping association table.

S503, traversing the KEY with the Value number more than one corresponding to each KEY in the first mapping association table, determining that the KEY has an open circuit, and traversing the KEY with the Value number more than one corresponding to each KEY in the second mapping association table, determining that the KEY has a short circuit.

500 step 503, after the pins in the IPC file and the Gerber file are in one-to-one correspondence with the physical network, the two tables obtained can quickly check whether the PCB design file has open short circuit through a common traversal algorithm, so that the PCB design file can be conveniently fed back to a client for modification or a technician for subsequent pertinence modification, manual one-to-one comparison is not needed, and the detection efficiency is greatly improved.

In this embodiment, a second mapping association table of the mapping table is constructed by using Gerber physical network ID as a key and an IPC logical network name list as values, and may be used to analyze a short circuit condition, and when the number of logical networks in any one value list in the second mapping association table exceeds 1, it is indicated that a short circuit occurs. As there are A, B two nets in IPC file, a includes pins a1 and a2, B includes pins B1 and B2, there are pads P1, P2, P3 and P4 in Gerber file, where P1 and P2 are connected to form Net1, P3 and P4 are connected to form Net2, and assuming that the projection of Gerber file to IPC file is: a1 corresponds to P1, a2 corresponds to P3, B1 corresponds to P2, B2 corresponds to P4, the tree diagram corresponding to the network is shown in fig. 4, the lower half diagram in fig. 5 is shown as a second mapping association table, as shown in the figure, Net1 corresponds to a1 and B1, and Net2 corresponds to a2 and B2.

Specifically, referring to fig. 6, taking 23 as an example, two logical networks, i.e., L1 and LED-L, correspond to one DFM-Net24 physical network, and also two bar portions on the left side of the table can be seen, and one L1 appears in the right side portion of the table, which indicates that a short circuit occurs, according to a correct design, L1 should be included in the bar portions on the left side, and if the logical network corresponds to only one physical network, it is in a normal state. .

Correspondingly, the IPC network name is key, the Gerber physical network ID list is used as a value to construct a first mapping association table of the mapping table, the first mapping association table can be used for analyzing the open circuit condition, and when the number of physical networks in any value list in the first mapping association table exceeds 1, the open circuit occurs. Suppose the projection from the IPC file to the GBR file is: a1 corresponds to P1, a2 corresponds to P3, B1 corresponds to P2, B2 corresponds to P4, the tree diagram corresponding to the network is also shown in fig. 4, the upper half diagram in fig. 5 is shown as a first mapping association table, as shown in the figure, a corresponds to P1 and P3, and B corresponds to P2 and P4. Wherein the first mapping association table is IPC _ GBR _ Map in the figure, and the second mapping association table is GBR _ IPC _ Map in the figure.

Specifically, as shown in fig. 7, taking the behavior 13 as an example, the NetF1-1 logical network corresponds to two physical networks, namely DFM-Net2 and DFM-Net5, so that there is an open circuit, and the logical network is in a normal state if it corresponds to only one physical network.

S600, detecting whether the PCB design file has an open circuit or a short circuit according to the first mapping association table and the second mapping association table, and displaying and storing the PCB design file.

S700, establishing an open-short circuit analysis table according to the first mapping association table, the second mapping association table and the open-short circuit data, wherein the open-short circuit analysis table at least comprises short circuit quantity statistics and open circuit quantity statistics.

In this step, that is, in the same manner as the case shown in fig. 6 and fig. 7, the results are unified in an open-short analysis table, which greatly facilitates the technical staff to look up and make targeted modification, and also facilitates the customer to look up and modify.

Preferably, referring to details in fig. 6 and fig. 7, the open-short analysis table further includes layer information, where the layer information includes pin coordinate data and logical network number data in the first mapping association table and a physical network in the second mapping association table. The scheme further facilitates technical personnel and clients to consult after analysis, and the display logic network or the physical network can be switched.

Compared with the prior art, the method and the device can ensure that the data acquired from the client can be compared, and can realize quick finding of the positions of short circuits and open circuits by analyzing the IPC file and the Gerber file and establishing a mapping relation, so that the positions of the short circuits and the open circuits can be modified according to defects, the condition of PCB production errors is avoided, the detection efficiency is high, the detection time is greatly shortened, and the cost is saved.

The method has the advantages that the error and leakage condition existing in manual detection does not exist, the problem of open and short circuit can be detected by 100% through the one-to-one correspondence of the IPC file and the Gerber file, the information required to be provided by a client does not need to be changed, the PCB design file is still provided, or the Gerber file and the IPC file are provided, and the Gerber file and the IPC file can be exported through the PCB design file and are standard files in the field without extra cost.

Example 2

The PCB open-short circuit analysis device comprises a server and a client, wherein the server operates the open-short circuit analysis detection method of the PCB design file, the client is provided with an uploading port, the uploading port is used for a client to upload the PCB design file, the Gerber file and the IPC file to the server, and the server carries out open-short circuit analysis on the PCB design file or the Gerber file and the IPC file and transmits the open-short circuit analysis back to the client for display. The device adopting the method also has the effect of greatly improving the detection efficiency without manual comparison one by one. The operation mode of the upload port can be seen in the schematic diagram of the add interface of the IPC file in fig. 2.

Example 3

The PCB open-short circuit analysis electronic equipment comprises a processor, a memory and a touch screen display, wherein the open-short circuit analysis detection method of the PCB design file is stored in the memory, the processor is used for operating an executable command in the memory, and the touch screen display is used for man-machine interaction. The electronic equipment adopting the method also has the advantages that manual comparison is not needed, the detection efficiency is greatly improved, and open-short circuit analysis can be carried out at any time and any place.

The present invention is not described in detail in the prior art, and therefore, the present invention is not described in detail.

It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.

The computer system of the server for implementing the method of the embodiment of the present invention includes a central processing unit CPU) that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) or a program loaded from a storage section into a Random Access Memory (RAM). In the RAM, various programs and data necessary for system operation are also stored. The CPU, ROM, and RAM are connected to each other via a bus. An input/output (I/O) interface is also connected to the bus.

The following components are connected to the I/O interface: an input section including a keyboard, a mouse, and the like; an output section including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage section including a hard disk and the like; and a communication section including a network interface card such as a LAN card, a modem, or the like. The communication section performs communication processing via a network such as the internet. The drive is also connected to the I/O interface as needed. A removable medium such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive as necessary, so that a computer program read out therefrom is mounted into the storage section as necessary.

In particular, according to the embodiments of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication section, and/or installed from a removable medium. The computer program performs the above-described functions defined in the system of the present invention when executed by a Central Processing Unit (CPU).

It should be noted that the computer readable medium shown in the present invention can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present invention, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present invention, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams or flowchart illustrations, and combinations of blocks in the block diagrams or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The modules described in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described modules may also be disposed in a processor.

Although the use of the term in the present text is used more often, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations that may be imposed by the spirit of the present invention.

The present invention is not limited to the above-mentioned preferred embodiments, and any other products in various forms can be obtained by anyone in the light of the present invention, but any changes in the shape or structure thereof, which have the same or similar technical solutions as those of the present application, fall within the protection scope of the present invention.