1. A method for verifying data protection bits for NOR Flash, the method comprising the steps of:

s1, enumerating all combinations of data protection bits of the state register, and acquiring specific area addresses protected by the data protection bits in each combination;

s2, designing a verification paradigm, and circularly traversing each combination according to the verification paradigm to generate a corresponding test case;

and S3, simulating and traversing each test case to generate a report file, and verifying the data protection bit of the state register in the chip to be tested according to the report file.

2. The method according to claim 1, wherein the condition that the verification of the data protection bit in step S3 is successful is: the area protected by the combination of data protection bits may not perform write and erase operations, and the area unprotected by the combination of data protection bits may perform write and erase operations.

3. The method of claim 1, wherein after the simulation traverses each test case in step S3, the report file is generated based on the simulation result.

4. The method of claim 1, wherein the report file includes first operation information as to whether the area protected by the combination of the data protection bits is not executable for the write and erase operations, and second operation information as to whether the area unprotected by the combination of the data protection bits is executable for the write and erase operations.

5. The method of claim 4, wherein if the report file of the test case matches the result of the first operation information is yes and/or the result of the second operation information is no, a design modification prompt is issued.

6. The method for verifying the data protection bit according to claim 1, wherein the specific area address protected by the data protection bit is obtained through a design specification of NOR Flash and written into a corresponding test case.

7. An apparatus for verifying a data protection bit of a NOR Flash, comprising:

an enumeration module for enumerating all combinations of data protection bits of the status register;

the acquisition module is used for acquiring the specific area address protected by the data protection bit;

the case generation module is used for designing a verification paradigm and circularly traversing each combination according to the verification paradigm to generate a test case;

the simulation verification module is used for simulating and verifying the data protection bit of the state register in the chip to be tested;

the acquisition module acquires specific area addresses protected by data protection bits in each combination enumerated by the enumeration module, the case generation module generates corresponding test cases with the same number as the combinations by combining the combinations enumerated by the enumeration module and the specific area addresses protected by the data protection bits acquired by the acquisition module based on a verification paradigm, and the simulation test module generates a report file by simulating and traversing each test case and verifies the data protection bits of a state register in a chip to be tested based on the report file.

8. The apparatus of claim 7, wherein the emulation verification module comprises:

the simulation module is used for simulating according to the test case and generating a simulation result;

the report module is used for generating a report file according to the simulation result of the simulation module;

and the verification analysis module is used for verifying the report file generated by the analysis report module so as to verify the data protection bit of the state register in the chip to be tested.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-6.

10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-6.

Background

The write protection is a function provided by the NOR Flash, different areas of the NOR Flash can be protected by configuring different combinations of the status registers by a user, if the protected area is not unprotected, the write and erase operations cannot be performed in the area of the NOR Flash, and all write and erase instructions sent to the protected area can be directly ignored by the NOR Flash.

When designing NOR Flash memories with different memory sizes, research and development personnel have different protected areas in the NOR Flash memories with different memory sizes for different data protection bit combinations in the status register.

Therefore, the corresponding data protection bit is verified for NOR Flash with different memory sizes; in the prior art, when verifying data protection bits of NOR flashes with different memory sizes, a test case related to write protection needs to be manually rewritten to verify whether a combination of write protection bits of different status registers protects a corresponding area. Because the combination of the write protection bits of the status register is fixed, only the corresponding protection areas are different, when the write protection bits of the NOR Flash of different memories are verified, if each combination of the write protection bits is written with a test case one by one in each development process to test, only repeated operation of changing the address of the protection area is performed in different test cases, so that the efficiency is low, and the process of manually writing too many test cases is complicated.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method and an apparatus for verifying a data protection bit, an electronic device, and a storage medium, which can be universally used for verifying and obtaining the data protection bits of NOR Flash data of different memory sizes, and the verification process is simple, convenient, and efficient.

In a first aspect, an embodiment of the present application provides a method for verifying a data protection bit, where the method is used to verify the data protection bit of NOR Flash, and the method includes the following steps:

s1, enumerating all combinations of data protection bits of the state register, and acquiring specific area addresses protected by the data protection bits in each combination;

s2, designing a verification paradigm, and circularly traversing each combination according to the verification paradigm to generate a corresponding test case;

and S3, simulating and traversing each test case to obtain a report file, and verifying the data protection bit of the state register in the chip to be tested according to the report file.

According to the verification method of the data protection bit, the specific area address protected by the data protection bit in each combination is obtained through all combinations of the data protection bits of the enumeration state register, a test case which can be used for verification is constructed, then the verification test case is generated according to a paradigm, and a simulation result is checked, so that the data protection bit of the state register can be verified.

In the method for verifying the data protection bit, the condition that the data protection bit in step S3 is successfully verified is as follows: the area protected by the combination of data protection bits may not perform write and erase operations, and the area unprotected by the combination of data protection bits may perform write and erase operations.

In the method for verifying the data protection bit, after each test case is simulated and traversed in step S3, the report file is generated based on the simulation result.

The method for verifying the data protection bits comprises a first operation information about whether the area protected by the combination of the data protection bits can perform the writing and erasing operations and a second operation information about whether the area unprotected by the combination of the data protection bits can perform the writing and erasing operations.

According to the verification method of the data protection bit, if the report file of the test case meets the condition that whether the first operation information result is yes and/or the second operation information result is no, a design modification prompt is issued.

According to the verification method of the data protection bit, the specific area address protected by the data protection bit is obtained through a design specification of NOR Flash and is written into a corresponding test case.

In a second aspect, an embodiment of the present application further provides a verification apparatus for verifying a data protection bit of NOR Flash, including:

an enumeration module for enumerating all combinations of data protection bits of the status register;

the acquisition module is used for protecting the specific area address of the data protection bit;

the case generation module is used for designing a verification paradigm and circularly traversing each combination according to the verification paradigm to generate a test case;

the simulation verification module is used for simulating and verifying the data protection bit of the state register in the chip to be tested;

the acquisition module acquires specific area addresses protected by data protection bits in each combination enumerated by the enumeration module, the case generation module generates corresponding test cases with the same number as the combinations by combining the combinations enumerated by the enumeration module and the specific area addresses protected by the data protection bits acquired by the acquisition module based on a verification paradigm, and the simulation test module generates a report file by simulating and traversing each test case and verifies the data protection bits of a state register in a chip to be tested based on the report file.

The verifying device of the data protection bit, wherein the emulation verifying module comprises:

the simulation module is used for simulating according to the test case and generating a simulation result;

the report module is used for generating a report file according to the simulation result of the simulation module;

and the verification analysis module is used for verifying the report file generated by the analysis report module so as to verify the data protection bit of the state register in the chip to be tested.

According to the verification device for the data protection bits, all combinations of the data protection bits are enumerated through the enumeration module, specific area addresses protected by all combinations are obtained through the obtaining module, the test case which can be used for verification is constructed through the case generating module, then the data protection bits of the state register can be obtained through simulation results of the simulation verification test case which is verified through the simulation verification module paradigm, the verification device can be generally used for verifying NOR Flash data protection bits with different memory sizes, and the verification process is simple, convenient and efficient.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.

In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program runs the steps in the method provided in the first aspect when executed by a processor.

As can be seen from the above, embodiments of the present application provide a method, an apparatus, an electronic device, and a storage medium for verifying data protection bits, where in the verification method, all combinations of data protection bits are enumerated and specific area addresses protected by each combination are obtained, a test case that can be used for verification is generated in a traversal manner according to a verification paradigm, and then the data protection bits of a status register are verified through a report file generated by simulation of the test case, so that the method and the apparatus can be generally used for verification and verification of NOR Flash data protection bits of different memory sizes, and the verification process is simple, convenient, and efficient.

Drawings

Fig. 1 is a flowchart of a method for verifying a data protection bit according to an embodiment of the present disclosure.

Fig. 2 is a detailed logic diagram of a verification method for data protection bits according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of an apparatus for verifying a data protection bit according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

In a first aspect, please refer to fig. 1-2, fig. 1-2 are a method for verifying data protection bits of NOR Flash according to some embodiments of the present application, the method includes the following steps:

s1, enumerating all combinations of data protection bits of the state register, and acquiring specific area addresses protected by the data protection bits in each combination;

the state register is also called as a condition code register and is provided with a plurality of state bits for embodying or storing information, and the data protection bit is formed by the state bits of the state register; since the combination of the data protection bits of the status register is fixed, all combinations of the data protection bits of the status register in the NOR Flash can be enumerated, that is, all fixed combinations of the status register in the NOR Flash can be obtained by an enumeration method.

Specifically, the specific area address protected by the data protection bit in each combination is obtained, so that the specific area address protected by the data protection bit corresponding to the target NOR Flash by the corresponding combination can be ensured.

S2, designing a verification paradigm, and circularly traversing each combination according to the verification paradigm to generate a corresponding test case;

specifically, based on the combination form of the data protection bits in combination with the specific area addresses protected by the corresponding data protection bit combinations, since the combination and the specific addresses protected by the combination are in one-to-one correspondence, a verification paradigm can be designed to traverse the combination to generate the test case.

More specifically, the test case contains combination information for use in the input simulation test and target address information for use in the determination result.

More specifically, the combination information is set based on the combination form of the data protection bits, and the target address information is set based on the specific area address corresponding to the combination protection.

And S3, simulating and traversing each test case to obtain a report file, and verifying the data protection bit of the state register in the chip to be tested according to the report file.

Specifically, the test cases are subjected to simulation test one by one, combination information corresponding to the test cases in a data protection bit combination form is simulated, whether the execution conditions of the writing and erasing algorithms in the target address information are consistent with the expected relationship is checked, and if the execution conditions are consistent, the data protection bit combination in the current combination information and the corresponding address play a protection role.

According to the verification method of the data protection bits, the specific area address of the data protection bits in each combination is obtained through all combinations of the data protection bits of the enumeration state register, a test case which can be used for verification is constructed, then the data protection bits are traversed through a paradigm to generate the verification test case, a report file is obtained through simulation, and the data protection bits of the state register can be verified based on the report file.

More specifically, the paradigm refers to a prevailing course of action in a field, which includes both concepts and methods. In this embodiment, the present invention refers to a verification concept and a specific verification method designed based on a combination of data protection bits and an address, that is, a write protection relationship of a specific area address protected by each combination of data protection bits, that is, a relationship between a use state of the specific area address and a corresponding data protection bit, that is, a relationship between a combination of data protection bits and a corresponding specific area address whether reading or writing can be performed is defined.

Specifically, the paradigm may be preset and written into the verification script.

In some preferred embodiments, the condition that the data protection bit verification in step S3 is successful is: the area protected by the combination of data protection bits may not perform write and erase operations, and the area unprotected by the combination of data protection bits may perform write and erase operations.

Thus, the verification result that satisfies the paradigm is: the area protected by the combination of the data protection bits can not execute writing and erasing operations, and the area unprotected by the combination of the data protection bits can execute the writing and erasing operations; similarly, the verification result that does not satisfy the paradigm is: write and erase operations may be performed on areas protected by the combination of data protection bits and/or may not be performed on areas unprotected by the combination of data protection bits.

Specifically, the test case meeting the verification result of the paradigm shows that the verified data protection bit combination of the NOR Flash plays a role in data protection; therefore, a test case can be quickly generated based on the paradigm verification, whether the data protection bit of the NOR Flash protects the corresponding specific area address can be quickly verified based on the result of the simulation test case, and in addition, the writing and erasing conditions of the protected area and the unprotected area are simultaneously verified, so that the verification accuracy of the data protection bit can be effectively ensured.

In some preferred embodiments, after each test case is simulated and traversed in step S3, a report file is generated based on the simulation result.

Specifically, each report file corresponds to each test case and can be recorded by setting a serial number, for example, if the serial number of a group of test cases is text1, the report file automatically generates a serial number text1_ report, which is beneficial to subsequent verification processing by classification and sorting of simulation results, so that the verification process is more standard and ordered.

More specifically, the report file includes test data that can be used for paradigm validation, and may also include a specific area address that corresponds to a data protection bit combination form, a state, and a data protection bit corresponding to protection.

In some preferred embodiments, the report file includes first operation information as to whether the area protected by the combination of the data protection bits can perform the write and erase operations, and second operation information as to whether the area unprotected by the combination of the data protection bits can perform the write and erase operations.

Specifically, in the verification process, whether the first operation information and the second operation information conform to the corresponding relationship between the data protection bit and the address can be verified through the report file at the same time or at different times.

In this embodiment, it is preferable that the first operation information is verified first, and then the second operation information is verified; if the first operation information is verified to be not in accordance with the relationship between the data protection bit combination and the address (namely, the area protected by the data protection bit can execute writing and erasing operations), the verification of the second operation information is skipped, and the verification speed can be effectively improved.

In some preferred embodiments, if the report file of the test case meets the condition that the result of the first operation information is yes and/or the result of the second operation information is no, it indicates that the data protection bit combination corresponding to the address of the current test case does not play a protection role, and a design modification prompt is issued.

Specifically, if the test case cannot pass the simulation verification, it indicates that there is erroneous data in the test case, and the source of the erroneous data is generally that an error occurs in acquiring the specific area address protected by the data protection bit in each combination, so that a design modification prompt needs to be issued, and a designer modifies the design or re-enters the accurate specific area address.

In some preferred embodiments, the specific area address protected by the data protection bit is obtained through a design specification of NOR Flash and written into a corresponding test case.

Specifically, the design specification of the NOR Flash contains the specific area address protected correspondingly by the data protection bit combination, and when the embodiment of the application is applied to the NOR flashes with different specifications, the acquisition process can be completed only by searching the specific area address protected correspondingly by the corresponding data protection bit combination from the corresponding design specification of the NOR Flash; when the method is used for NOR flashes with different specifications, the specific area address protected correspondingly by the corresponding data protection bit combination is obtained and can be reused, and the verification logic does not need to be redesigned, so that the method has the characteristics of convenience in operation, wide application range and high reusability.

According to the verification method of the data protection bits, all combinations of the data protection bits are enumerated, specific area addresses protected by each combination are obtained, test cases which can be used for verification are generated in a traversing mode according to a verification paradigm, then the data protection bits of the state register are verified through a report file generated by simulation of the test cases, the method can be generally used for verification and obtaining of NOR Flash data protection bits of different memory sizes, and the verification process is simple, convenient and efficient.

In a second aspect, please refer to fig. 3, fig. 3 is a verification apparatus for verifying a data protection bit of a NOR Flash according to some embodiments of the present application, including:

an enumeration module for enumerating all combinations of data protection bits of the status register;

the acquisition module is used for protecting the specific area address of the data protection bit;

the case generation module is used for designing a verification paradigm and circularly traversing each combination according to the verification paradigm to generate a test case;

the simulation verification module is used for simulating and verifying the data protection bit of the state register in the chip to be tested;

the acquisition module acquires specific area addresses protected by data protection bits in each combination enumerated by the enumeration module, the case generation module combines the enumerated combinations of the enumeration module and the specific area addresses protected by the data protection bits acquired by the acquisition module and generates corresponding test cases with the same number as the combinations based on a verification paradigm, and the simulation test module traverses each test case through simulation to generate a report file and verifies the data protection bits of a state register in a chip to be tested based on the report file.

According to the verification device for the data protection bits, all combinations of the data protection bits are enumerated through the enumeration module, specific area addresses protected by all combinations are obtained through the obtaining module, the test case which can be used for verification is constructed through the case generating module, then the data protection bits of the state register can be obtained through simulation results of the simulation verification test case which is verified through the simulation verification module paradigm, the verification device can be generally used for verifying NOR Flash data protection bits with different memory sizes, and the verification process is simple, convenient and efficient.

In some preferred embodiments, the obtaining module is a writer, and the designer can write the address information into the verification device through the obtaining module.

In some preferred embodiments, the simulation verification module comprises:

the simulation module is used for simulating according to the test case and generating a simulation result;

the report module is used for generating a report file according to the simulation result of the simulation module;

and the verification analysis module is used for verifying the report file generated by the analysis report module so as to verify the data protection bit of the state register in the chip to be tested.

Specifically, the simulation module traverses the test case data to perform simulation test, generates a corresponding report file through the report module after the test is completed, and verifies the report file by the verification analysis module, so as to judge whether the data protection bit in the corresponding test case has a protection effect on the protection address.

In a third aspect, referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.

In a fourth aspect, the present application provides a storage medium, and when being executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.