Three-coordinate radar system applied to low-slow small target detection
1. A three-coordinate radar system applied to low-slow small target detection is characterized by comprising an antenna, a coupling feeder network, a channel module and a signal processing module which are sequentially cascaded;
the antenna is divided into N antenna channels;
the channel module comprises a correction unit, a frequency synthesis component and M TR components; wherein:
the TR component comprises N/M radio frequency interfaces which are butted with the antenna channels and is butted with the frequency synthesis component through a power division synthesis network; the power division synthesis network is provided with a receiving and transmitting switch for switching the working state to realize the receiving and transmitting time-sharing work of the TR component;
the frequency synthesizer component is used for generating an intermediate frequency transmitting signal, an intermediate frequency transmitting signal time pulse signal and a local oscillator signal of up-down frequency conversion required by the TR component;
the correction unit is used for respectively correcting the receiving channel and the transmitting channel according to the switching state of the receiving and transmitting switch;
the coupling feeder network is connected with a signal to the TR component in the channel module in a butt joint mode, and simultaneously feeds the signal to the correction unit in the channel module to realize real-time correction of the transmitting and receiving channels of the TR component;
and the signal processing module is used for carrying out digital processing on signals obtained by synthesizing M TR component sub-arrays and then carrying out amplitude-phase weighting to complete DBF processing so as to finally obtain radar target information.
2. The system of claim 1, wherein the calibration unit couples the calibration signal to the TR transmit/receive channels using a radio frequency coupler.
3. The system of claim 1, wherein each antenna channel is composed of a plurality of slot antenna elements.
4. The three-coordinate radar system applied to low-slow small target detection as claimed in claim 1, wherein the number of the antenna channels is 64, and the number of the TR components is 16; each TR component receives 4 paths of antenna channel signals, amplifies, filters, mixes, filters and synthesizes the signals into 1 path of signals by power, thereby realizing the function of subarray synthesis; correspondingly, each TR component receives 1 path of intermediate frequency signals from the frequency synthesis component, then the signals are divided into 4 paths of transmitting channels, and 4 paths of radio frequency signals are output to corresponding antenna channels after the signals are amplified, up-converted, filtered and amplified by the 4 paths of transmitting channels.
5. The three-coordinate radar system applied to low-slow small-target detection of the radar system as claimed in claim 4, wherein the number of the coupled feeder networks is 4 for the correction unit; when the receiving channel of the TR component needs to be corrected, the correction unit transmits a correction signal, the correction signal is coupled to 4 coupling feeder networks through 1-4 power dividers, and each coupling feeder network couples the correction signal to 16 signal channels, so that the correction signal is coupled to 64 TR receiving channels in total.
6. The three-coordinate radar system applied to low-slow small target detection according to claim 1, wherein the signal processing module comprises an ADC unit, an FPGA and a DSP which are sequentially cascaded; the FPGA is used for generating a radar time sequence control signal, a radar wave control signal, receiving data output by the ADC unit, and extracting, filtering and DBF processing baseband data; the DSP performs operations to form a radar target description word.
7. The three-coordinate radar system applied to low-slow small target detection according to claim 6, wherein a wave control circuit is arranged in the FPGA to generate the radar wave control signal; specifically, according to the beam direction, the weighting coefficients of different beam directions are calculated and generated in real time, so that the beam direction is dynamically changed, and the function of receiving multi-beam tracking is realized.
8. The system of claim 6, wherein the DSP is configured to finally obtain the radar target description word by performing pulse reduction, MTD/MTI, decision and CFAR operations on the large echo data.
9. The system of claim 6, wherein the frequency synthesizer module is further configured to generate a reference clock of an ADC sampling clock inside the signal processing module, so as to ensure homology and coherence of the whole system and provide a precondition for DBF processing.
10. The system of claim 1, wherein the radar system is configured to perform mechanical scanning in azimuth direction and electrical scanning in elevation direction, and the reception in elevation direction is configured to perform DBF technology to form multiple beams.
Background
Early radar systems used search radar in conjunction with altimetry radar to measure 3 coordinates (azimuth, elevation and range) of an airborne target. The radar mainly adopts a mechanical rotating antenna, and the elevation angle range of a search airspace is 5-45 degrees. With the continuous change of detection technology, the two-coordinate radar cannot completely meet the requirement.
With the continuous development of transmitter technology and signal processing technology, especially the increasing maturity and miniaturization of various electric scanning technologies or combination of electric and mechanical scanning technologies, the search radar of the low-altitude short-range anti-air system for target indication has been developed from two coordinates to three coordinates. The search airspace range of the three-coordinate radar can be expanded to 60-80 degrees, the detection technology of the ultra-low-altitude target and the hovering helicopter is greatly improved, and a multi-beam scanning mode is adopted in the elevation angle.
Radars adopting Digital Beam Forming (DBF) technology are also generally called phased array radars, and the three-coordinate radar applying the multi-Beam technology has the advantages of high data rate, large antenna gain, long operating distance and good anti-interference performance. But the number of the feed sources and the transceiver devices is large, and at least the amplitude (or phase) balance among the signals is required to be good, otherwise, measurement errors are caused. In order to effectively implement DBF processing, amplitude and phase correction is generally required to be performed on each physical channel of a radar, and by means of the correction, the amplitude and phase of each channel of the radar are guaranteed to be consistent.
At present, most phased array three-coordinate radars are used for remote early warning, tens of thousands of array elements and thousands of receiving channels are frequently used, the cost is very high, and the real-time calibration of a network is also extremely complex.
Disclosure of Invention
The purpose of the invention is: the three-coordinate radar system applied to low-speed small target detection is provided, and has a low-cost and multi-beam phased array radar framework and a low-cost and simple real-time calibration network.
In order to achieve the purpose, the invention provides the following technical scheme:
a three-coordinate radar system applied to low-slow small target detection comprises an antenna, a coupling feeder network, a channel module and a signal processing module which are sequentially cascaded;
the antenna is divided into N antenna channels;
the channel module comprises a correction unit, a frequency synthesis component and M TR components; wherein:
the TR component comprises N/M radio frequency interfaces which are butted with the antenna channels and is butted with the frequency synthesis component through a power division synthesis network; the power division synthesis network is provided with a receiving and transmitting switch for switching the working state to realize the receiving and transmitting time-sharing work of the TR component;
the frequency synthesizer component is used for generating an intermediate frequency transmitting signal, an intermediate frequency transmitting signal time pulse signal and a local oscillator signal of up-down frequency conversion required by the TR component;
the correction unit is used for respectively correcting the receiving channel and the transmitting channel according to the switching state of the receiving and transmitting switch;
the coupling feeder network is connected with a signal to the TR component in the channel module in a butt joint mode, and simultaneously feeds the signal to the correction unit in the channel module to realize real-time correction of the transmitting and receiving channels of the TR component;
and the signal processing module is used for carrying out digital processing on signals obtained by synthesizing M TR component sub-arrays and then carrying out amplitude-phase weighting to complete DBF processing so as to finally obtain radar target information.
Based on the technical scheme, the invention can further carry out the following optimization or specific selection:
optionally, the calibration unit is a radio frequency coupler for coupling the calibration signal to the TR transmit/TR receive channel.
Optionally, each antenna channel is composed of a plurality of slot antenna elements; for example each antenna channel consists of 12 slot antenna elements.
Optionally, the number of the antenna channels is 64, and the number of the TR components is 16; each TR component receives 4 paths of antenna channel signals, amplifies, filters, mixes, filters and synthesizes the signals into 1 path of signals by power, thereby realizing the function of subarray synthesis; correspondingly, each TR component receives 1 path of intermediate frequency signals from the frequency synthesis component, then the signals are divided into 4 paths of transmitting channels, and 4 paths of radio frequency signals are output to corresponding antenna channels after the signals are amplified, up-converted, filtered and amplified by the 4 paths of transmitting channels.
Optionally, for the correction unit, there are 4 of the coupled feeder networks; when the receiving channel of the TR component needs to be corrected, the correction unit transmits a correction signal, the correction signal is coupled to 4 coupling feeder networks through 1-4 power dividers, and each coupling feeder network couples the correction signal to 16 signal channels, so that the correction signal is coupled to 64 TR receiving channels in total.
Optionally, the signal processing module includes an ADC unit, an FPGA, and a DSP that are sequentially cascaded; the FPGA is used for generating a radar time sequence control signal, a radar wave control signal, receiving data output by the ADC unit, and extracting, filtering and DBF processing baseband data; the DSP performs operations to form a radar target description word.
Optionally, a wave control circuit is arranged in the FPGA to generate the radar wave control signal; specifically, according to the beam direction, the weighting coefficients of different beam directions are calculated and generated in real time, so that the beam direction is dynamically changed, and the function of receiving multi-beam tracking is realized.
Optionally, the DSP specifically performs pulse reduction, MTD/MTI, decision and CFAR operation on the large echo data to finally obtain a radar target description word.
Optionally, the frequency synthesizer component is further configured to generate a reference clock of an ADC sampling clock inside the signal processing module, so as to ensure homologous and coherent of the whole system, and provide a precondition for DBF processing.
Optionally, the radar system adopts a mode of azimuth mechanical scanning and pitch electrical control scanning, and the pitch reception adopts a DBF technology to form multiple beams.
Compared with the prior art, the invention has at least the following beneficial effects:
1. the invention provides a novel low-altitude and ultra-low-altitude radar architecture aiming at the low-speed and small-target detection requirements, namely, a sub-array synthesis mode is adopted and then a DBF (direct bus function) processing mode is adopted, so that the number of ADCs can be effectively reduced, and the low cost of the whole radar system is realized.
2. The invention skillfully applies the radio frequency coupler to the correction network to replace a switch device in the conventional correction network. Firstly, the coupler couples partial energy of the main channel, does not influence the attenuation characteristic of the main channel from TR to the antenna on hardware, can reduce the attenuation to the antenna, and improve the transmitting power of the system; secondly, as the radio frequency coupler is a passive device, the switch is an active device and needs a driving circuit, and a correction network of the coupler is adopted, the stability of the system can be greatly improved, and the correction cost of the radar system is reduced; meanwhile, the characteristic of the coupler changes little with the temperature, and the switch changes greatly with the temperature, so the effect of the coupler correction is better than that of the switch correction.
3. The invention can utilize the fragment time in the radar running process to correct the radar in real time so as to prevent the influence on DBF treatment caused by the change of channel characteristics at different times due to factors such as temperature, mechanical stress and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
The drawings in the present specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure.
FIG. 1 is a schematic diagram of one embodiment of the present invention.
Fig. 2 is a schematic diagram of a subarray synthesis 16-channel DBF design according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a calibration network based on a switch implementation in a conventional scheme.
Fig. 4 is a diagram illustrating calibration performed by a coupled feeder network according to an embodiment of the present invention.
Detailed Description
Other advantages and features of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein it is to be understood that the embodiments of the invention are shown and described, simply by way of illustration of specific embodiments thereof, but not by way of limitation of the invention.
For the phased array radar which is used and developed at present, in order to reduce the development cost and the like, a phased array antenna adopting one-dimensional phase scanning is more adopted, the research of the embodiment is an array multi-beam three-coordinate radar which mechanically scans in the azimuth and scans in the pitching phase, and flexible beam configuration is realized by adopting a transmitted beam forming design and a received Digital Beam Forming (DBF) technology, so that the method is suitable for different working modes and can realize higher data rate; also needed to be investigated is a low cost, simple real-time calibration network.
One, low cost, multi-beam phased array radar architecture
The embodiment provides a three-coordinate radar system with a unique architecture and multi-target tracking capability, which is mainly used for low-altitude defense, has very low cost, and can realize the DBF technology only by 64 array elements and 16 channels (16 intermediate frequency signals are designed on hardware, then are digitized, and then are subjected to amplitude-phase weighting to realize the receiving multi-beam in the pitching direction).
The radar adopts a mode of azimuth mechanical scanning and pitch electrical control scanning. On the basis of the same azimuth direction, the pitching direction emitting wave beams scan from top to bottom, the pitching direction receiving adopts the DBF technology, so that multi-wave beams are formed, and a plurality of targets can be tracked simultaneously.
As shown in fig. 1, the three-coordinate radar system applied to low-slow small target detection includes an antenna, a coupled feeder network, a channel module, and a signal processing module, which are sequentially cascaded.
The antenna has 64 antenna channels, and each antenna channel (unit waveguide slot antenna) is composed of 12 slot antenna units.
The coupling feeder network is connected with the signal to the TR component of the channel module in a butt joint mode, and meanwhile the signal is fed into the receiving correction channel to achieve real-time correction of the transmitting channel and the receiving channel of the TR component.
The rear stage of the coupling feeder line unit is a channel module which mainly comprises a correction unit, a frequency synthesis component and 16 TR components; wherein:
the TR component comprises 4 radio frequency interfaces which are in butt joint with the antenna channels, receives signals of the 4 antenna connecting channels, amplifies, filters, mixes, filters and synthesizes power to 1 path, and realizes the function of sub-array synthesis (namely, one TR component establishes 1 sub-array). Similarly, the TR module receives 1 channel of intermediate frequency signals, then divides the signals into 4 channels of transmitting channels, and outputs 4 channels of radio frequency signals to the antenna through the amplification, up-conversion, filtering, power amplification and other processes of the 4 channels of transmitting channels. The TR component works in a time-sharing mode through receiving and transmitting and is switched through a switch.
The frequency synthesizer is used for generating an intermediate frequency transmission signal, the intermediate frequency transmission signal is a pulse signal, and a linear frequency hopping signal is arranged in the pulse. The same time frequency synthesis is used for the local oscillator signals of up-down frequency conversion required by the TR component of the product, and the same time frequency synthesis is used for the reference clock of the ADC sampling clock in the signal processing module of the product, so that the homology and the coherence of the whole system are ensured, and the precondition is provided for DBF processing.
The channel module also contains a correction unit (correction channel), when the receiving channel of the TR component needs to be corrected, the correction channel transmits a correction signal, the correction signal is coupled to 4 coupled feeder networks through 1-4 power dividers, and each coupled feeder network couples the correction signal to 16 signal channels, and the total number of the channels is 64. The correction signals are coupled to 64 TR receiving channels and then are subjected to 4 unifications in the TR component to form 16 paths of signals which are subjected to signal processing through the ADC, so that a closed-loop correction loop aiming at the whole receiving channel is formed and can be used for correcting the 64 receiving channels;
similarly, the intermediate frequency signal is transmitted through the frequency synthesis assembly, then the control switch transmits the signal through the transmitting channel of the coupling TR assembly, then the transmitting signal is coupled to the correction receiving channel through the coupling feeder network, and the signal is sent to the correction ADC for digitalization after being processed by down-conversion, amplification, filtering and the like of the correction receiving channel, so that the signal characteristic of the current transmitting channel is obtained. In the same way, the transmitting channel is replaced, the correction receiving channel is kept unchanged, and the signal characteristic of the next transmitting channel can be obtained; thus, the signal characteristics of 64 transmitting channels can be tested, and then a correction word for each transmitting channel is formed according to the test data, so that the correction of 64 radio frequency transmitting channels can be realized.
The signal processing module internally comprises a digitization circuit for receiving intermediate frequency signals of 16 paths of receiving channels and a digitization circuit for correcting the received intermediate frequency signals; the digital data receiving, calculating and processing circuit also comprises a control circuit. The FPGA is mainly used for generating radar time sequence control signals, generating radar wave control signals, receiving ADC data, performing down-conversion and filtering on the data and the like. The FPGA is used for receiving ADC data and extracting, filtering and DBF processing the baseband data; the DSP is used for carrying out pulse reduction, MTD/MTI, judgment, CFAR operation and other processing on the large echo data to form a radar target description word.
In fig. 1, the display and control unit is not shown; in practical applications, the display and control unit is usually a PC. The display control unit is mainly composed of software which is divided into a database and a display control front-end interface. The database is mainly responsible for storing historical data and pictures, and the database equipment end is responsible for interacting with the radar, sending control data according to a protocol and receiving radar data. The display control front end is mainly used for sending and receiving radar parameter setting values and displaying radar parameters in real time.
The wave control circuit is contained in the signal processing module and mainly realizes the real-time calculation and generation of weighting coefficients of different beam directions according to the beam directions, thereby dynamically transforming the beam directions and realizing the function of receiving multi-beam tracking.
Generally, the most expensive part of a hardware system is a power amplifier and an ADC, and the architecture shown in fig. 1 is unique for a low-altitude and ultra-low-altitude radar architecture, and the number of ADCs can be effectively reduced through a sub-array synthesis mode and then through a DBF implementation mode, so that the low cost of the whole radar system is realized.
The principle of 4-subarray synthesis of 16-channel DBF is shown in fig. 2.
Through tests, if the subarray weighting is directly carried out, then the DBF is carried out, and side lobes are only 13dB according to the general coefficient; referring to various existing research papers, by adaptively optimizing analog and digital weighting coefficients, the side lobe of a beam directional diagram can reach about 23Db, although the digital weighting effect is slightly poorer than that of directly carrying out digital weighting on 64 channels, the requirements of saving cost, reducing system complexity and improving system stability can be met on the premise of not influencing the overall performance of the radar.
In the embodiment, the radio frequency amplitude and phase in the traditional phased array radar are weighted and shifted to a digital baseband by using Digital Beam Forming (DBF), namely, the attenuation and phase shift control of the array is changed into the direct weighting operation of digital signals. The weights can be updated according to the array element sampling data by using a beam forming algorithm of a hardware platform based on the FPGA, so that the receiving or transmitting beam has a specific shape and an expected zero point.
Two, low cost calibration network
Generally, the design of the calibration network is realized by calibration switches, and the conventional switch design network realizes the calibration of the consistency of the transmitting and receiving channels of the TR by using the calibration switches as shown in fig. 3.
When the system starts to correct the transmission channel of the TR, all 64 correction switches are turned on, and the correction reception channels are turned on, turning on the transmission inside the TR one by one. For example, a transmitting signal of a TR1 channel is firstly switched on, at the moment, a correction receiving signal receives the transmitted signal, the signal is amplified, frequency-converted and filtered to form an intermediate frequency signal which is sent to an ADC (analog to digital converter), and the intermediate frequency signal is sent to the rear end after being digitized to calculate the amplitude and phase characteristics of the signal; secondly, switching on the transmitting signal of the TR2 channel, switching off other TR transmitting signals, and calculating the amplitude and phase characteristics of the signal 2 according to the steps; the amplitude phase characteristics of the signals 1 and 2 … … and 64 are calculated in this way, because the receiving channels are shared, the amplitude phase characteristics of the transmitting channels at the current time TR1, TR2 and TR … … 64 can be calculated by comparing the amplitude phase characteristics of the signals 1 and 2 … and 64, so that the transmitting channel correction words are calculated and are brought into the system, and the consistency correction of the transmitting channels of all TRs can be realized.
In the same way, in turn, through correcting the transmitting signal of the transmitting channel and receiving the signal by the TR channel, the correction word of the receiving channel can be calculated, and the correction of the TR receiving channel is realized.
The conventional calibration network shown in fig. 3 is switched by a switch, and the rf switch has a high cost and may affect the main channel connected to the antenna, so that the calibration cost is high and the stability is poor.
The present embodiment proposes a coupler-based calibration network, and specifically, as shown in fig. 4, utilizes a radio frequency coupler to implement calibration of the consistency of the TR transmitting and receiving channels in transceiving.
When the system starts to correct the transmission channel of the TR, all 64 couplers are always turned on by default, and the correction reception channel is turned on, turning on the transmission inside the TR one by one. For example, the transmitting signal of the TR1 channel is firstly switched on, the corrected receiving signal receives the coupling signal of the TR1 transmitting channel, the signal is amplified, frequency-converted and filtered to form an intermediate frequency signal which is sent to the ADC, and the intermediate frequency signal is sent to the rear end after being digitized to calculate the amplitude and phase characteristics of the signal; secondly, switching on the transmitting signal of the TR2 channel, switching off other TR transmitting signals, and calculating the amplitude and phase characteristics of the signal 2 according to the steps; the amplitude phase characteristics of the signals 1 and 2 … … and 64 are calculated, the output of the coupler is connected into the same receiving channel, and the amplitude phase characteristics of the transmitting channels at the current moments TR1, TR2 and … … TR64 can be calculated by comparing the amplitude phase characteristics of the signals 1 and 2 … and 64, so that the transmitting channel correction words are calculated and are brought into the system, and the consistency correction of the transmitting channels of all TRs can be realized.
In the same way, in turn, by correcting the transmission channel transmission signal, the transmission signal is coupled to the receiving channel of each TR module through the coupler, and then passes through the rear end of the receiving channel of the TR module, the ADC (refer to fig. 1) of the signal processing module is digitized, and the digital of each channel receives the correction signal; through the digital correction signals of 64 channels, a correction word of a receiving channel can be calculated, and the TR receiving channel is corrected.
In the embodiment, the coupler is used for coupling partial energy of the main channel, the attenuation characteristic of the main channel from the TR to the antenna is not influenced on hardware, the attenuation to the antenna can be reduced, and the transmitting power of the system is improved.
Meanwhile, the radio frequency coupler is a passive device, the switch is an active device and needs a driving circuit, and a correction network of the coupler is adopted, so that the stability of the system can be greatly improved, and the correction cost of the radar system is reduced.
Moreover, the coupler characteristic changes little with temperature and the switch changes much with temperature, so the effect of correction using the coupler will be better than that using the switch.
While the invention has been described in detail by way of the general description and the specific examples, it will be apparent to those skilled in the art that many modifications may be made thereto without departing from the invention. Accordingly, such modifications are intended to be included within the scope of this invention as claimed, without departing from the spirit thereof.