1. An apparatus for performing failure analysis on a chip, comprising:

the infrared metallographic microscope is suitable for observing the electroluminescence condition of the emission area of the chip to be detected;

the display is connected with the infrared metallographic microscope and is suitable for displaying the condition observed by the infrared metallographic microscope;

the chip carrying platform is suitable for containing the chip to be tested;

the current source is suitable for outputting direct current and controlling the magnitude of the output direct current;

a first metal probe electrically connected to a positive electrode of the current source;

a second metal probe electrically connected to the negative pole of the current source;

the first probe adjusting seat is suitable for adjusting the first metal probe to enable the probe tip of the first metal probe to be in contact with the P electrode of the chip to be detected;

and the second probe adjusting seat is suitable for adjusting the second metal probe to enable the probe tip of the second metal probe to be in contact with the N electrode of the chip to be detected.

2. The device of claim 1, wherein the chip to be tested is a die or a package tube; and/or the chip to be tested is a VCSEL device.

3. The apparatus of claim 1, wherein the first metal probe and the second metal probe are made of the same material; and/or the first metal probe and the second metal probe are respectively and independently an alloy bent needle.

4. The apparatus of claim 1, wherein the current resolution of the current source is no greater than 0.5 μ Α.

5. The device of claim 1, wherein the current resolution of the current source is 0.01-0.1 μ A.

6. A method for failure analysis of a chip using the apparatus of any one of claims 1 to 5, comprising:

(1) placing a chip to be tested on a chip carrier and enabling the chip to be tested to be located in an observation area of an infrared metallographic microscope;

(2) the probe tip of the first metal probe is contacted with the P electrode of the chip to be detected by using the first probe adjusting seat, and the probe tip of the second metal probe is contacted with the N electrode of the chip to be detected by using the second probe adjusting seat;

(3) adjusting the focal length of the infrared metallographic microscope so as to clearly observe the surface of the emission area of the chip to be detected;

(4) and turning off a light source of the infrared metallographic microscope, starting a current source, increasing output current of the current source step by step at fixed current intervals from 0 muA, and observing the brightness of a picture observed by the infrared metallographic microscope through a display to judge the failure position of the chip to be detected, wherein a light emitting area of the failure position is a dark spot during observation.

7. The method of claim 6, wherein step (1) further comprises: forming a positioning mark on the edge of the chip to be detected; and/or the presence of a gas in the gas,

in the step (4), the fixed current interval is not more than 0.5 muA.

8. The method according to claim 6, wherein in the step (4), the light source of the infrared metallographic microscope is turned off, the current source is turned on, and the output current of the current source is increased in steps at fixed current intervals from 0 μ A until the emission area of the chip to be tested is observed to have a slight light through the display:

if the light emitting area does not have dark spots, judging that the emitting area of the chip to be tested does not have a failure position;

and if the light emitting area has the dark spots, judging that the surface and/or the inside of the area where the dark spots of the chip to be detected are located have failure positions.

9. The method of claim 6, further comprising, prior to performing step (4): observing whether the surface of the chip to be detected is abnormal or not by using the infrared metallographic microscope and the display:

if the surface of the chip to be detected is abnormal, judging that the surface of the chip to be detected has a failure position;

and if the surface of the chip to be detected is not abnormal, judging that the surface of the chip to be detected does not have a failure position.

10. The method according to claim 9, wherein in the step (4), the light source of the infrared metallographic microscope is turned off, the current source is turned on, and the output current of the current source is increased in steps at fixed current intervals from 0 μ Α until the emission area of the chip to be tested can be observed to have a slight light through the display:

if the light emitting area does not have dark spots, judging that the emitting area of the chip to be tested does not have a failure position;

if dark spots exist in the light emitting area, and no abnormality exists on the surface of the chip to be tested or the area where the dark spots are located is inconsistent with the abnormal position, determining that the failure position of the area where the dark spots are located is located inside the chip to be tested;

if the light emitting area has dark spots and the surface of the chip to be tested has abnormal positions, and meanwhile, the area where the dark spots are located is consistent with the abnormal positions, the output current of the current source is continuously increased step by step at fixed current intervals, whether the area of the dark spots is bright or not is observed, and if the area of the dark spots is bright, the surface and the inside of the area where the abnormal positions of the chip to be tested are located are judged to have failure positions; and if the dark spot area is not lightened, judging that a failure position exists on the surface of the area where the abnormal position of the chip to be detected is located.

Background

The failure of the chip is inevitable in the processes of development, production and use, failure analysis is a necessary means for determining the failure mechanism of the chip, provides necessary information for effective fault diagnosis, and provides directions for design engineers to continuously improve or repair the design of the chip. For example, through failure analysis, potential failures such as open circuit, short circuit and the like in the production process of a product can be found out, the occurrence reason and mechanism of the failures are analyzed, basis and direction are provided for designers of integrated circuits and the like to find out problems such as defects in design, mismatching of process parameters or improper design and operation, and the method has very important significance for seeking improvement measures, avoiding failure occurrence, improving product quality and reliability and reducing cost loss.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide an apparatus and a method for failure analysis of a chip. The device is simple in structure, can also inject certain electric current into the chip, accurately judges whether the chip to be detected has failure or not, whether the chip to be detected has failure position or not inside the chip to be detected, the shape of the failure position and whether the failure position is located inside the chip or on the surface of the chip, and can judge the electrical property form of the chip to be detected failure simultaneously, thereby greatly improving the accuracy and reliability of failure analysis of the chip.

The present application is primarily based on the following problems:

in the failure analysis process of the VCSEL chip product, the failure reason of the light emitting surface needs to be analyzed. At present, failure analysis of VCSEL products is mainly carried out from the aspects of appearance and electrical property, wherein appearance detection is to observe the surface of the emitting cavity by using a high-magnification microscope, so that abnormal positions on the surface of the emitting cavity can be found for analysis and improvement, but the method cannot find the internal structure abnormality of the emitting cavity; the electrical detection is to detect the output result through current injection, and determine whether the interior of the VCSEL device is failed from data, but the method cannot confirm the specific failure position and cannot improve the specificity.

To this end, according to one aspect of the invention, an apparatus for failure analysis of a chip is provided. According to an embodiment of the invention, the apparatus comprises:

the infrared metallographic microscope is suitable for observing the electroluminescence condition of the emission area of the chip to be detected;

the display is connected with the infrared metallographic microscope and is suitable for displaying the condition observed by the infrared metallographic microscope;

the chip carrying platform is suitable for containing the chip to be tested;

the current source is suitable for outputting direct current and controlling the magnitude of the output direct current;

a first metal probe electrically connected to a positive electrode of the current source;

a second metal probe electrically connected to the negative pole of the current source;

the first probe adjusting seat is suitable for adjusting the first metal probe to enable the probe tip of the first metal probe to be in contact with the P electrode of the chip to be detected;

and the second probe adjusting seat is suitable for adjusting the second metal probe to enable the probe tip of the second metal probe to be in contact with the N electrode of the chip to be detected.

The inventor finds that when the chip surface or the chip interior has a failure position, the failure position of the chip emitting area generates dark spots relative to other light emitting areas during electroluminescence, and when the failure position exists only on the chip surface and only in the chip interior, the electroluminescence conditions of the chip emitting area and the chip emitting area are different when the current is continuously increased, and when the failure position exists only on the chip surface, the dark spots of the failure position cannot disappear even if the current is continuously increased; and if only the chip has a failure position, the dark spots of the failure position gradually disappear when the current is continuously increased. According to the device for failure analysis of the chip in the embodiment of the invention, whether the failure position exists on the surface of the chip to be detected can be observed by using the infrared metallographic microscope in combination with the display, whether the failure position exists in the chip to be detected and/or on the surface of the chip to be detected can be accurately judged by further combining the current source through observing the electroluminescence condition of the emission area of the chip to be detected in the current step-by-step increasing process, and meanwhile, whether the failure position is specifically positioned on the surface of the chip or in the chip can be accurately judged. Compared with the prior art, the device has at least the following advantages: 1. the device has the advantages that the structure is simple, the phenomenon is obvious, the sensitivity is high, whether the chip to be tested fails or not can be judged only through the brightness degree of the light-emitting area, and whether the failure position is specifically positioned on the surface or inside the chip to be tested can be accurately judged according to the electroluminescence condition, so that the problems that whether the chip fails or not can not be observed and the distribution area of the failure position inside the chip can not be confirmed by the conventional device are solved; 2. by observing the shape of electroluminescence, the shape of the area of the failure position of the chip can be clearly seen, and the light-emitting area of the failure position is a dark spot during observation; 3. the electric property form of the failure of the chip to be tested can be judged by adjusting the output current of the current source; 4. the accuracy and the reliability of failure analysis of the chip can be greatly improved.

In addition, the apparatus for failure analysis of a chip according to the above embodiment of the present invention may further have the following additional technical features:

in some embodiments of the present invention, the chip to be tested is a die or a package tube; and/or the chip to be tested is a VCSEL device.

In some embodiments of the present invention, the first metal probe and the second metal probe are made of the same material; and/or the first metal probe and the second metal probe are respectively and independently an alloy bent needle.

In some embodiments of the invention, the current resolution of the current source is no greater than 0.5 μ Α.

In some embodiments of the present invention, the current resolution of the current source is 0.01-0.1 μ A.

According to a second aspect of the present invention, the present invention provides a method for performing failure analysis on a chip by using the apparatus for performing failure analysis on a chip. According to an embodiment of the invention, the method comprises:

(1) placing a chip to be tested on a chip carrier and enabling the chip to be tested to be located in an observation area of an infrared metallographic microscope;

(2) the probe tip of the first metal probe is contacted with the P electrode of the chip to be detected by using the first probe adjusting seat, and the probe tip of the second metal probe is contacted with the N electrode of the chip to be detected by using the second probe adjusting seat;

(3) adjusting the focal length of the infrared metallographic microscope so as to clearly observe the surface of the emission area of the chip to be detected;

(4) and turning off a light source of the infrared metallographic microscope, starting a current source, increasing output current of the current source step by step at fixed current intervals from 0 muA, and observing the brightness of a picture observed by the infrared metallographic microscope through a display to judge the failure position of the chip to be detected, wherein a light emitting area of the failure position is a dark spot during observation.

The method for analyzing the failure of the chip in the embodiment of the invention can utilize the infrared metallographic microscope and the display to observe whether the failure position exists on the surface of the chip to be detected, can further combine the current source to accurately judge whether the failure position exists in the chip to be detected and/or on the surface of the chip to be detected by observing the electroluminescence condition of the emission area of the chip to be detected in the current step-by-step increasing process, and can also accurately judge whether the failure position is specifically positioned on the surface of the chip or in the chip. Compared with the prior art, the method has at least the following advantages: 1. the method has the advantages that the operation is simple, the phenomenon is obvious, the sensitivity is high, whether the chip to be tested fails or not can be judged only through the brightness degree of the light-emitting area, and whether the failure position is specifically positioned on the surface or inside of the chip to be tested can be accurately judged according to the electroluminescence condition, so that the problems that whether the chip fails or not and the distribution area of the failure position inside the chip cannot be confirmed in the prior art are solved; 2. by observing the shape of electroluminescence, the shape of the area of the failure position of the chip can be clearly seen, and the light-emitting area of the failure position is a dark spot during observation; 3. the electric property form of the failure of the chip to be tested can be judged by adjusting the output current of the current source; 4. the accuracy and the reliability of failure analysis of the chip can be greatly improved.

In some embodiments of the present invention, step (1) further comprises: forming a positioning mark on the edge of the chip to be detected; and/or, in the step (4), the fixed current interval is not more than 0.5 muA.

In some embodiments of the present invention, in step (4), the light source of the infrared metallographic microscope is turned off, the current source is turned on, and the output current of the current source is increased step by step at fixed current intervals from 0 μ Α until the display can observe that there is slight light in the emission area of the chip to be measured: if the light emitting area does not have dark spots, judging that the emitting area of the chip to be tested does not have a failure position; and if the light emitting area has the dark spots, judging that the surface and/or the inside of the area where the dark spots of the chip to be detected are located have failure positions.

In some embodiments of the present invention, before performing step (4), further comprising: observing whether the surface of the chip to be detected is abnormal or not by using the infrared metallographic microscope and the display: if the surface of the chip to be detected is abnormal, judging that the surface of the chip to be detected has a failure position; and if the surface of the chip to be detected is not abnormal, judging that the surface of the chip to be detected does not have a failure position.

In some embodiments of the present invention, in step (4), the light source of the infrared metallographic microscope is turned off, the current source is turned on, and the output current of the current source is increased step by step at fixed current intervals from 0 μ Α until the display can observe that there is slight light in the emission area of the chip to be measured: if the light emitting area does not have dark spots, judging that the emitting area of the chip to be tested does not have a failure position; if dark spots exist in the light emitting area, and no abnormality exists on the surface of the chip to be tested or the area where the dark spots are located is inconsistent with the abnormal position, determining that the failure position of the area where the dark spots are located is located inside the chip to be tested; if the light emitting area has dark spots and the surface of the chip to be tested has abnormal positions, and meanwhile, the area where the dark spots are located is consistent with the abnormal positions, the output current of the current source is continuously increased step by step at fixed current intervals, whether the area of the dark spots is bright or not is observed, and if the area of the dark spots is bright, the surface and the inside of the area where the abnormal positions of the chip to be tested are located are judged to have failure positions; and if the dark spot area is not lightened, judging that a failure position exists on the surface of the area where the abnormal position of the chip to be detected is located.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a structural view of an apparatus for performing failure analysis on a chip according to an embodiment of the present invention.

FIG. 2 is a flow diagram of a method for failure analysis of a chip according to yet another embodiment of the invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

According to one aspect of the invention, an apparatus for performing failure analysis on a chip is provided. According to an embodiment of the invention, as shown with reference to fig. 1, the apparatus comprises: the device comprises an infrared metallographic microscope 10, a display 20, a chip carrier 30, a current source 40, a first metal probe 50, a second metal probe 60, a first probe adjusting base 70 and a second probe adjusting base 80. Wherein, the infrared metallographic microscope 10 is suitable for observing the electroluminescent condition of the emission area of the chip 90 to be measured; the display 20 is connected with the infrared metallographic microscope 10 and is suitable for displaying the condition observed by the infrared metallographic microscope 10; the chip carrier 30 is adapted to hold a chip 90 to be tested; the current source 40 is adapted to output a direct current and control the magnitude of the output direct current; the first metal probe 50 is electrically connected to the positive electrode of the current source 40; the second metal probe 60 is electrically connected to the negative pole of the current source 40; the first probe adjusting seat 70 is adapted to adjust the first metal probe 50 so that the probe tip of the first metal probe 50 contacts with the P electrode of the chip 90 to be tested; the second probe adjusting seat 80 is adapted to adjust the second metal probe 60 so that the probe tip of the second metal probe 60 contacts with the N electrode of the chip 90 to be tested. The device is simple in structure, can also inject certain electric current into the chip, accurately judges whether the chip to be detected has failure or not, whether the chip to be detected has failure position or not inside the chip to be detected, the shape of the failure position and whether the failure position is located inside the chip or on the surface of the chip, and can judge the electrical property form of the chip to be detected failure simultaneously, thereby greatly improving the accuracy and reliability of failure analysis of the chip.

The apparatus for failure analysis of a chip according to the above embodiment of the present invention will be described in detail with reference to fig. 1.

According to the embodiment of the invention, the inventor finds that a certain current can be injected into a chip to be tested, whether the chip to be tested has failure or not is accurately judged through the electroluminescence condition, the failure position is confirmed, when the failure position exists on the surface or inside of the chip, dark spots are generated at the failure position of a chip emitting area in electroluminescence relative to other light emitting areas, when the failure positions exist only on the surface and only inside of the chip, the electroluminescence conditions of the chip emitting area and the chip emitting area are different when the current is continuously increased, and when the failure position exists only on the surface of the chip, the dark spots at the failure position cannot disappear even if the current is continuously increased; if only the chip has a failure position, the dark spots at the failure position gradually disappear when the current is continuously increased, because the dark spots are covered due to the fact that the photon concentration in the chip is increased after the current is continuously increased, and the dark spots on the surface of the chip are not covered by photons, the problem that the existing detection equipment cannot confirm the failure position in the chip can be effectively solved. In addition, the inventor also finds that the light and dark degree of a light emitting area of a chip emitting area can be more sensitively distinguished by adopting the infrared metallographic microscope, so that dark spots of the light emitting area can be effectively captured, and therefore a failure position can be confirmed, and the situation that the light spots are difficult to capture by adopting other microscopes is also difficult. Specifically, a chip to be tested can be placed on a chip carrier, the probe tip of a first metal probe is fully contacted with a PPAD (P electrode) of the chip to be tested by adjusting a probe adjusting seat, the probe tip of a second metal probe is fully contacted with an NPAD (N electrode) of the chip to be tested, the focal length of an infrared metallographic microscope is adjusted until the surface of an emitting area of the chip to be tested can be clearly observed, a light source of the microscope is closed, the chip to be tested is in a dark field environment in the microscope, a current source is started, and increasing the output current of the current source at intervals of any fixed value of 0.01-0.5 muA from 0 muA until the emission region appears in the image of the observation microscope, and then confirming the region of the failure position by observing the position of the dark spot, on the premise of confirming that the surface of the chip to be detected is not abnormal, generating a position with dark spots, namely a failure position in the chip; further, whether failure positions exist on the surface of the chip to be detected or not can be observed in advance by utilizing an infrared metallographic microscope, and whether dark spots exist in a light emitting area of a chip emitting area or not, whether the positions of the dark spots are consistent with the failure positions of the surface of the chip or not and whether the dark spots disappear after the current is continuously increased are combined to determine whether all the failure positions are specifically positioned on the surface of the chip or in the chip and the distribution area of the failure positions; in addition, the electric property form of the failure of the chip to be tested can be judged by adjusting the output current of the current source. Therefore, the accuracy and the reliability of failure analysis of the chip can be greatly improved. It should be noted that the "slight brightness" in the present invention refers to the brightness of the bright light generated by the emission region of the chip to be measured when the current injected into the chip to be measured just enables the photon concentration generated by the emission region of the chip to be measured to be captured by the infrared metallographic microscope.

According to an embodiment of the present invention, the chip 90 to be tested is fixed, the metal probe electrically connected to the output terminal of the current source 40 is connected to the electrode of the chip 90 to be tested, and after the infrared metallographic microscope 10 is focused, the light source of the infrared metallographic microscope 10 can be turned off, the current source is turned on, and the output current of the current source is increased step by step at a fixed current interval from 0 μ a until the display can observe that the emitting area of the chip to be tested has a bright light: if the light emitting area does not have dark spots, judging that the emitting area of the chip to be tested does not have a failure position; and if the light-emitting region has the dark spots, judging that the surface and/or the inside of the region where the dark spots of the chip to be detected are located have failure positions.

According to another embodiment of the present invention, the chip 90 to be measured is fixed, the metal probe electrically connected to the output terminal of the current source 40 is connected to the electrode of the chip 90 to be measured, and after the infrared metallographic microscope 10 is focused, the infrared metallographic microscope 10 and the display 20 may be used to observe whether there is an abnormality on the surface of the chip to be measured: if the surface of the chip to be detected is abnormal, judging that the surface of the chip to be detected has a failure position; if the surface of the chip to be detected is not abnormal, judging that no failure position exists on the surface of the chip to be detected; then, the light source of the infrared metallographic microscope 10 is turned off, the current source 40 is turned on, and the output current of the current source is increased step by step at a fixed current interval from 0 μ a until the display can observe that the emitting area of the chip to be measured has bright light: if the light emitting area has no dark spots, the emitting area of the chip to be tested has no failure position; if the light emitting region has dark spots, and the surface of the chip to be tested does not have abnormity or the area where the dark spots are located is inconsistent with the abnormal position of the surface of the chip, judging that a failure position exists in the chip to be tested; if the light emitting area has dark spots, the surface of the chip to be tested has abnormal positions, and meanwhile, the area where the dark spots are located is consistent with the abnormal positions, the output current of the current source can be continuously increased step by step at fixed current intervals, whether the dark spot area is bright or not is observed, and if the dark spot area is bright, the surface and the inner part of the area where the abnormal positions of the chip to be tested are both determined to have failure positions; and if the dark spot area is not lightened, judging that the failure position exists on the surface of the area where the abnormal position of the chip to be detected is located.

According to another embodiment of the present invention, the type of the chip 90 to be tested is not particularly limited as long as it has an electroluminescent effect, and those skilled in the art can select the chip 90 to be tested according to actual needs, for example, the chip 90 to be tested can be a die or a package tube, and the inventors found that a chip may include a plurality of dies with the same structure and the same function, and each die can be packaged to form a microelectronic device, such as a VCSEL device, and the number of the microelectronic devices that can be manufactured by each chip is considerable, and if a defect is generated due to carelessness of manufacturing, the defect may spread to hundreds of thousands of products, so that failure analysis of a single die or VCSEL device can be found, defects or improvements that may be generated during production or preparation can be found in time, and design defects, and design defects can be found for designers, The problems of mismatching of process parameters or improper design and operation and the like provide basis and direction, and the method has very important significance for seeking improvement measures, avoiding failure occurrence, improving product quality and reliability and reducing cost loss. And for the chip after the encapsulation, the failure analysis can be carried out on the chip without dismounting, and the operation is more convenient. For another example, the chip to be tested may be a VCSEL device, so that the problem that it is difficult for the existing detection device to determine whether the internal structure of the emission cavity has a failure location and the failure location distribution area inside the emission cavity is difficult to determine can be effectively solved.

According to another embodiment of the present invention, the materials and structures of the first metal probe 50 and the second metal probe 60 are not particularly limited, and those skilled in the art can select them according to actual needs as long as they have good conductivity and are stable with the current source and the current path formed by the chip to be tested, for example, the first metal probe 50 and the second metal probe 60 can be alloy bent pins independently; preferably, the first metal probe 50 and the second metal probe 60 may be made of the same material, so that the stability of the current path and the stability of the electroluminescence effect of the chip to be detected can be further improved, and the accuracy and reliability of the detection result can be further ensured.

According to another embodiment of the present invention, the current resolution of the current source 40 may be not greater than 0.5 μ a, for example, 0.01 μ a, 0.02 μ a, 0.05 μ a, 0.1 μ a, 0.2 μ a, 0.3 μ a, 0.4 μ a, or 0.5 μ a, etc., and the inventors found that, if the current resolution of the current source is smaller, the selectable value of the fixed value is smaller when the current is increased at fixed value intervals, the test effect is more sensitive, and if the current resolution of the current source is too large, the fixed value when the current is increased at fixed value intervals is larger, the generated photon concentration is too large to cover dark spots at the failure position, and the accuracy and reliability of the test result are greatly reduced. Preferably, the current resolution of the current source may be 0.01 to 0.1 μ a, for example, the current source may be turned on and the output current of the current source may be increased step by step at current intervals of 0.1 μ a from 0 μ a until the display can observe that the emission area of the chip to be detected has the appearance of bright light, so that the detection sensitivity may be further improved, and the accuracy and reliability of the detection result may be ensured to be higher.

According to another embodiment of the present invention, before failure analysis is performed on the chip 90 to be tested, a positioning mark may be formed on the edge of the chip 90 to be tested, so that when an abnormality or a dark spot of the chip is observed through a microscope and a display, the precise position of the abnormality or the dark spot may be determined according to the positioning mark, thereby improving the accuracy of positioning the failure position.

In summary, according to the device for analyzing the failure of the chip in the above embodiment of the present invention, it is able to use the infrared metallographic microscope in combination with the display to observe whether there is a failure position on the surface of the chip to be tested, and further combine with the current source to accurately determine whether there is a failure position inside and/or on the surface of the chip to be tested by observing the electroluminescence condition of the emission area of the chip to be tested in the process of current increasing step by step, and at the same time, it is able to accurately determine whether the failure position is specifically located on the surface of the chip or inside the chip. Compared with the prior art, the device has at least the following advantages: 1. the device has the advantages that the structure is simple, the phenomenon is obvious, the sensitivity is high, whether the chip to be tested fails or not can be judged only through the brightness degree of the light-emitting area, and whether the failure position is specifically positioned on the surface or inside the chip to be tested can be accurately judged according to the electroluminescence condition, so that the problems that whether the chip fails or not can not be observed and the distribution area of the failure position inside the chip can not be confirmed by the conventional device are solved; 2. by observing the shape of electroluminescence, the shape of the area of the failure position of the chip can be clearly seen, and the light-emitting area of the failure position is a dark spot during observation; 3. the electric property form of the failure of the chip to be tested can be judged by adjusting the output current of the current source; 4. the accuracy and the reliability of failure analysis of the chip can be greatly improved.

According to a second aspect of the present invention, the present invention provides a method for performing failure analysis on a chip by using the apparatus for performing failure analysis on a chip. According to an embodiment of the invention, as shown with reference to fig. 2, the method comprises: (1) placing a chip to be tested on a chip carrier and enabling the chip to be tested to be located in an observation area of an infrared metallographic microscope; (2) the probe tip of the first metal probe is contacted with the P electrode of the chip to be detected by using the first probe adjusting seat, and the probe tip of the second metal probe is contacted with the N electrode of the chip to be detected by using the second probe adjusting seat; (3) adjusting the focal length of the infrared metallographic microscope so as to clearly observe the surface of the emission area of the chip to be detected; (4) and turning off a light source of the infrared metallographic microscope, starting a current source, increasing output current of the current source step by step at fixed current intervals from 0 muA, and judging the failure position of the chip to be detected by observing the brightness of a picture observed by the infrared metallographic microscope through a display, wherein the light-emitting area of the failure position is a dark spot during observation. The method is simple to operate, obvious in phenomenon and high in sensitivity, can solve the problems that whether the inside of the chip is invalid or not can not be observed and the distribution area of invalid positions in the chip can not be confirmed in the conventional process, and is high in accuracy and reliability of the failure analysis of the chip.

According to an embodiment of the invention, before failure analysis is performed on a chip to be detected, a positioning mark can be formed on the edge of the chip to be detected, so that when the abnormality or dark spots of the chip are observed through a microscope and a display, the accurate position of the abnormality or dark spots can be confirmed according to the positioning mark, and the accuracy of positioning the failure position is improved. Further, the type of the chip to be tested is not particularly limited as long as the chip has an electroluminescence effect, and a person skilled in the art can select the chip to be tested according to actual needs, for example, the chip to be tested may be a die or a package tube, and specifically may be a VCSEL device, and the like.

According to still another embodiment of the present invention, in the step (4), the fixed current interval may be not more than 0.5 μ a, and preferably may be 0.01 to 0.1 μ a, thereby further improving the sensitivity of detection.

According to another embodiment of the present invention, in step (4), after the light source of the infrared metallographic microscope is turned off, the current source may be turned on and the output current of the current source may be increased step by step at a fixed current interval (e.g. 0.1 μ a) from 0 μ a until the display can observe that a slight bright light appears in the emitting area of the chip to be tested: if the light emitting area has no dark spots, the emitting area of the chip to be tested can be judged to have no failure position; and if the light-emitting region has the dark spots, the surface and/or the inner part of the region where the dark spots of the chip to be detected are/is judged to have the failure positions.

According to another specific embodiment of the present invention, in the actual operation process, there is a case that it is not possible to confirm whether the defect at the dark spot position is a surface defect or an internal defect, and at this time, the specific distribution position of the dark spot can be confirmed by further observing whether there is an abnormality on the surface of the chip to be tested and/or continuously increasing the output current of the current source to observe the brightness change of the dark spot through the infrared metallographic microscope and the display. Specifically, before performing step (4), the method may further include: observing whether the surface of the chip to be detected is abnormal by using an infrared metallographic microscope and a display: if the surface of the chip to be detected is abnormal, judging that the surface of the chip to be detected has a failure position; and if the surface of the chip to be detected is not abnormal, judging that the surface of the chip to be detected does not have a failure position. Under this prerequisite, when step (4) is carried out, after the light source of infrared metallographic microscope was closed, the current source was opened and the output current of current source was increased step by step with fixed current interval (as 0.1 mu A) from 0 mu A, until can observe through the display that the emitting area of the chip that awaits measuring has the bright light to appear: if the light emitting area does not have dark spots, judging that the emitting area of the chip to be tested does not have a failure position; if the light emitting region has dark spots, and the surface of the chip to be tested has no abnormality or the area where the dark spots are located is inconsistent with the abnormal position, determining that the failure position of the area where the dark spots are located is located inside the chip to be tested; if the light emitting area has dark spots and the surface of the chip to be tested has abnormal positions, and meanwhile, the area where the dark spots are located is consistent with the abnormal positions, the output current of the current source is continuously increased step by step at fixed current intervals, whether the area of the dark spots is bright or not is observed, and if the area of the dark spots is bright, the surface and the inner part of the area where the abnormal positions of the chip to be tested are located are judged to have failure positions; and if the dark spot area is not lightened, judging that the failure position exists on the surface of the area where the abnormal position of the chip to be detected is located. The distribution of the failure locations of the chip and whether the failure locations are on the chip surface or inside the chip can thus be determined accurately.

In summary, the method for analyzing the failure of the chip according to the above embodiment of the present invention may use an infrared metallographic microscope in combination with a display to observe whether the surface of the chip to be tested has a failure position, may further use a current source to accurately determine whether the chip to be tested has a failure position and/or the surface of the chip to be tested has a failure position by observing the electroluminescence condition of the emission area of the chip to be tested in the process of current increasing step by step, and may also accurately determine whether the failure position is specifically located on the surface of the chip or inside the chip. Compared with the prior art, the method has at least the following advantages: 1. the method has the advantages that the operation is simple, the phenomenon is obvious, the sensitivity is high, whether the chip to be tested fails or not can be judged only through the brightness degree of the light-emitting area, and whether the failure position is specifically positioned on the surface or inside of the chip to be tested can be accurately judged according to the electroluminescence condition, so that the problems that whether the chip fails or not and the distribution area of the failure position inside the chip cannot be confirmed in the prior art are solved; 2. by observing the shape of electroluminescence, the shape of the area of the failure position of the chip can be clearly seen, and the light-emitting area of the failure position is a dark spot during observation; 3. the electric property form of the failure of the chip to be tested can be judged by adjusting the output current of the current source; 4. the accuracy and the reliability of failure analysis of the chip can be greatly improved. It should be noted that the features and effects described for the apparatus for performing failure analysis on a chip are also applicable to the method for performing failure analysis on a chip, and are not described in detail here.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.