1. A method for testing a chip, comprising:

acquiring a control instruction, and respectively acquiring a first maximum reference voltage and a first minimum reference voltage of a chip at a first preset temperature and a second preset temperature according to the control instruction;

calculating a temperature calibration value of the chip according to the first maximum reference voltage and the first minimum reference voltage, wherein the temperature calibration value is used for calibrating the temperature characteristic of the chip reference voltage;

and writing the temperature calibration value into a memory of the chip, and testing the chip.

2. The chip testing method according to claim 1, wherein the obtaining a first maximum reference voltage and a first minimum reference voltage of the chip at a first preset temperature and a second preset temperature respectively according to the control instruction comprises:

writing a first register value and a second register value into a register of the chip according to the control instruction;

respectively acquiring reference voltages corresponding to the first register value and the second register value output by the chip at a first preset temperature by using a field effect transistor, wherein the first register value is used for determining the maximum reference voltage, and the second register value is used for determining the minimum reference voltage;

and respectively acquiring the reference voltages corresponding to the first register value and the second register value output by the chip at a second preset temperature by using a field effect transistor.

3. The chip testing method of claim 1, prior to calculating the temperature calibration value for the chip based on the first maximum reference voltage and the first minimum reference voltage, comprising:

and acquiring wafer information of the wafer, and storing the first maximum reference voltage and the first minimum reference voltage of each chip on the wafer corresponding to the first preset temperature in a preset format according to the wafer information.

4. The method for testing chips as claimed in claim 3, wherein before storing the first maximum reference voltage and the first minimum reference voltage of each chip on the wafer corresponding to the first preset temperature in a preset format according to the wafer information, the method comprises:

converting the maximum reference voltage and the minimum reference voltage of the chips at different positions on the wafer into data graphs;

and when the data graph has a missing part, determining a chip with data abnormity on the wafer according to the missing position.

5. The chip testing method of claim 1, prior to testing the chip, comprising:

writing the temperature calibration value into a register of the chip, and acquiring a second maximum reference voltage and a second minimum reference voltage of the chip at a third preset temperature;

calculating an absolute precision calibration value of the chip according to the second maximum reference voltage and the second minimum reference voltage, wherein the absolute precision calibration value is used for calibrating the absolute precision of the chip reference voltage;

writing the absolute precision calibration value into a memory of the chip.

6. The chip testing method of claim 1, prior to testing the chip, comprising:

writing a preset value into a register of the chip according to the control command, and measuring a clock frequency signal of the chip;

determining a frequency calibration value corresponding to a range of the clock frequency signal, wherein the frequency calibration value is used for calibrating the frequency of a clock oscillator of the chip;

writing the frequency calibration value into a memory of the chip.

7. The chip testing method according to any one of claims 1 to 6, comprising, after writing the temperature calibration value into the memory of the chip:

acquiring a parameter value of a preset position of a memory of the chip;

and when the parameter value is consistent with the temperature calibration value, determining that the temperature calibration value is successfully written.

8. A chip testing apparatus, comprising:

the acquisition module is used for acquiring a control instruction and respectively acquiring a first maximum reference voltage and a first minimum reference voltage of the chip at a first preset temperature and a second preset temperature according to the control instruction;

a calculation module, configured to calculate a temperature calibration value of the chip according to the first maximum reference voltage and the first minimum reference voltage, where the temperature calibration value is used to calibrate a temperature characteristic of the chip reference voltage;

and the test module is used for writing the temperature calibration value into a memory of the chip and testing the chip.

9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of a chip testing method according to any of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of a method for chip testing according to any one of claims 1 to 7.

Background

With the development of society, chips are more and more common in people's lives, and mobile phones, computers, smart speakers and other terminal devices utilizing the chips to support corresponding functions are more and more diversified, and the chips are more and more valued by people due to the advantages of small size, large-scale integration, high-speed processing performance and the like.

After the chip is produced, the chip needs to be tested so as to verify whether the chip meets the corresponding specification, but a certain deviation is easy to exist between the actual value of the chip parameter and the design standard value due to the limitation of the chip manufacturing process, so that the accuracy of the test result of the chip is low.

Disclosure of Invention

The embodiment of the application provides a chip testing method, a chip testing device, terminal equipment and a storage medium, and can solve the problem that the accuracy of a chip testing result is low.

In a first aspect, an embodiment of the present application provides a chip testing method, including:

acquiring a control instruction, and acquiring a first maximum reference voltage and a first minimum reference voltage of the chip at a first preset temperature and a second preset temperature respectively according to the control instruction;

calculating a temperature calibration value of the chip based on the first maximum reference voltage and the first minimum reference voltage, wherein the temperature calibration value is used for calibrating the temperature characteristic of the chip reference voltage;

and writing the temperature calibration value into a memory of the chip, and testing the chip.

In a second aspect, an embodiment of the present application provides a chip testing apparatus, including:

the acquisition module is used for acquiring a control instruction and respectively acquiring a first maximum reference voltage and a first minimum reference voltage of the chip at a first preset temperature and a second preset temperature according to the control instruction;

a calculation module, configured to calculate a temperature calibration value of the chip according to the first maximum reference voltage and the first minimum reference voltage, where the temperature calibration value is used to calibrate a temperature characteristic of the chip reference voltage;

and the test module is used for writing the temperature calibration value into a memory of the chip and testing the chip.

In a third aspect, an embodiment of the present application provides a terminal device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements any of the steps of the chip testing method when executing the computer program.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where a computer program is stored, and the computer program, when executed by a processor, implements the steps of any one of the chip testing methods.

In a fifth aspect, an embodiment of the present application provides a computer program product, which, when running on a terminal device, causes the terminal device to execute any one of the chip testing methods in the first aspect.

In the embodiment of the application, a control instruction is obtained, a first maximum reference voltage and a first minimum reference voltage of a chip are respectively obtained at a first preset temperature and a second preset temperature according to the control instruction, and the reference voltages of the chip are obtained by designing different temperatures, so that the accuracy of determining a subsequent calibration value is improved. And calculating the first maximum reference voltage and the first minimum reference voltage according to a first preset formula, determining a temperature calibration value of the chip, wherein the temperature calibration value is used for calibrating the temperature characteristic of the chip reference voltage, namely calibrating a standard value designed initially for the temperature characteristic, so that the temperature characteristic of the chip reference voltage is close to an actual value of a chip parameter, and parameter deviation caused by a manufacturing process is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a first schematic flowchart of a chip testing method according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a chip test system according to an embodiment of the present disclosure;

FIG. 3 is a schematic flow chart of the working state of the chip according to the embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of the field effect transistor provided in the embodiments of the present application;

FIG. 5 is a schematic diagram of a chip data exception provided in an embodiment of the present application;

FIG. 6 is a diagram illustrating a normal chip data provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a terminal device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Fig. 1 is a schematic flow chart of a chip testing method in an embodiment of the present application, where an execution main body of the method may be a terminal device, and the terminal device may be a TRI tester, such as a TR6836 tester, and this embodiment is described by taking the TR6836 tester as an example. As shown in fig. 1, the chip testing method may include the following steps:

step S101, acquiring a control instruction, and respectively acquiring a first maximum reference voltage and a first minimum reference voltage of the chip at a first preset temperature and a second preset temperature according to the control instruction.

In this embodiment, as shown in fig. 2, fig. 2 is a schematic structural diagram of a chip testing system, in order to minimize the amplitude of the reference voltage in the chip along with the temperature change, a TR6836 tester obtains a control instruction issued by a user through a PC terminal, so as to obtain a maximum reference voltage and a minimum reference voltage corresponding to the chip from a testing module respectively at a first preset temperature and a second preset temperature at which a temperature difference satisfies a preset condition, so as to calibrate the temperature characteristic of the chip reference voltage, where the reference voltage can be obtained by setting different register values. The larger the temperature difference between the first preset temperature and the second preset temperature is, the more accurate the subsequent calibration result is, and in order to make the subsequent calibration result more accurate, the temperature difference between the first preset temperature and the second preset temperature may be further set to be greater than or equal to a preset threshold. The chip can adopt a digital-to-analog conversion chip.

By way of specific example and not limitation, if the first preset temperature is 30 degrees celsius and the second preset temperature is 120 degrees celsius, the chip reference voltage output values are obtained at corresponding temperature settings, so as to obtain a first minimum reference voltage V0 and a first maximum reference voltage V1 at 30 degrees celsius, and a first minimum reference voltage V2 and a first maximum reference voltage V3 at 120 degrees celsius.

Further, as shown in fig. 3, fig. 3 is a schematic flow chart of a chip operating state, after detecting that the chip starts operating, if the TR6836 tester detects that a user sends a control instruction through a single-wire interface at the PC end within a preset time, and sends the control instruction to the chip to prompt the chip to enter an input instruction state, where the input instruction state can stop the chip from a normal measurement state, that is, stop the measurement sensor, so that the chip stops acquisition of signals, processes digital signals, converts the signals, and establishes a signal output with a stable time, and a corresponding pin of the chip performs serial communication with the outside by using a single-wire interface serial communication protocol. When the chip is in the state of inputting commands, the user can modify the settings of the chip register or the memory by using the PC terminal, and the parameters of the calibration algorithm are issued through the single-wire interface to change the relevant values of the chip, after the settings of all the registers or the memories of the chip are completed, the user can issue a control instruction for replacing the working state of the chip at the PC terminal so that the chip enters a normal measurement state according to the control instruction, the normal measurement state can enable the chip to continuously measure the sensor, and the measurement result is output to the TR6836 tester through the single-wire interface. If the chip does not detect the control command issued by the PC end within the preset time, the chip can read the value in the OTP, copy the read value into the corresponding register, and automatically enter a normal measurement state, and the chip can continuously acquire, convert and calibrate the sensor signal and output the analog or digital signal according to the setting in the register in the state. The chip can also enter a test state according to the control instruction so as to output a corresponding test signal, and the chip can stop working when the power is off. After the chip enters the normal measurement state from the input command state, the chip will not copy the value in the memory to the register, where the memory is an OTP memory, and this embodiment takes the OTP memory as an example for description. The preset time may be 6 ms.

It can be understood that the design of the working state of the chip provides convenience for later calibration, when calibration is carried out, the register can be preset in the working state, the working mode of the analog circuit is defined, and meanwhile, the digital circuit is closed, so that the chip outputs the original bridge reading and the temperature reading which are not calibrated after entering the normal measurement state. The original bridge readings and temperature readings are calibrated by the TR6836 tester on the PC to obtain the values of the parameters after the calibration algorithm, and these values can be written into the OTP when the chip inputs a command.

In one embodiment, as shown in fig. 2, the step S101 may include: the TR6836 tester writes a first register value and a second register value into a register of the chip according to the control instruction, so as to accurately obtain an expected reference voltage by using the register values, and specifically, the TR6836 tester obtains the reference voltages corresponding to the first register value and the second register value output by the chip at a first preset temperature by using a field effect transistor and a PEB board card configured by the field effect transistor, and then obtains the reference voltages corresponding to the first register value and the second register value output by the chip at a second preset temperature by using the field effect transistor, wherein the first register value is used for determining the maximum reference voltage, and the second register value is used for determining the minimum reference voltage.

Specifically, as shown in fig. 4, fig. 4 is a schematic structural diagram of the operation of the fet, a fet is switched and connected to the periphery of the chip through a relay, and the fet may be a J107 fet, whose model is BSS169, so as to be connected to a VDD voltage regulator inside the chip to form a PNP voltage regulator circuit, so as to achieve the functions of switching and VDD output voltage regulation. When the relay does not work, pins VDD and VDD _ OTP of the chip and an external direct-current power supply VSUPPULY are 0V, at the moment, only a VGATE pin and a first pin of a J107 field-effect tube are connected at the joint of the J107 field-effect tube and the chip, but at the moment, a second pin and a third pin of the J107 field-effect tube are suspended, so that the current field-effect tube does not work, and the chip does not output reference voltages at different temperatures.

When the relay in fig. 4 starts to work, the chip pin VDD is shorted with VDD _ OTP and connected to the second pin of the J107 fet, and the external power supply VSUPPLY is 6.0V and connected to the third pin of the J107 fet. At this time, the fet is operating, and the second pin, i.e., VDD, will output the reference voltage. When a register for temperature characteristic calibration in the chip is set to 00000, the chip outputs a minimum reference voltage through a VDD pin, that is, V0 corresponding to a first preset temperature of 30 degrees celsius and V2 corresponding to a second preset temperature of 120 degrees celsius; when the register for temperature characteristic calibration in the chip is set to 11111, the chip outputs the maximum reference voltage through the VDD pin, that is, V1 corresponding to the first preset temperature of 30 degrees celsius and V3 corresponding to the second preset temperature of 120 degrees celsius. In fig. 4, UR is an input signal terminal of the relay, and the relay is controlled to be closed by the input signal.

In one embodiment, because one CP flow can only use the same temperature condition during the factory IC test, how to acquire the reference voltage under different temperature conditions can only be processed through the cross flow, and the cross flow saving and the extraction of the calling test data become the key for the test. Most of the existing methods for storing and extracting data upload test data to a specific server and extract the test data through the server, and the method not only needs a lot of manpower and material resources and increases the cost, but also increases certain operation difficulty to a certain extent, for example, how to accurately find required data from multiple sets of data becomes a key for normally continuing a next process test on proper storage of the data. In this embodiment, the TR6836 tester obtains wafer information of a wafer having a plurality of chips, generates a file in a preset format according to the wafer information by using a corresponding program, and obtains coordinates of each chip on the wafer through an interface bus when the probe station communicates with the tester, so as to store a first maximum reference voltage and a first minimum reference voltage corresponding to each chip in the wafer in the file in the preset format at a first preset temperature.

Correspondingly, in order to facilitate the calculation of the temperature calibration value in this embodiment, when the temperature calibration value is at the second preset temperature, all the currently existing lot number and piece number information may be obtained in advance, that is, the files corresponding to each wafer in the same batch and piece number are measured, the file corresponding to the current wafer information is selected from the file corresponding to each wafer according to the wafer model in the wafer information, the first maximum reference voltage and the first minimum reference voltage at the first preset temperature corresponding to the extracted file are extracted according to different coordinates of each chip in the selected file, the first maximum reference voltage and the first minimum reference voltage corresponding to the same coordinate chip at the second preset temperature are obtained, the maximum reference voltage and the minimum reference voltage at the same chip at different temperatures are processed, and by the cross-flow data obtaining means, to increase the speed of data processing. The Wafer information includes a Wafer model, a Lot number (Wafer _ ID), a Lot number (Lot _ ID), and the like, the Wafer model is fixedly set by a program according to a Wafer, and the Lot number are automatically obtained by an interface bus used when the probe station and the tester communicate.

Furthermore, the multiple chips on the wafer can be tested in parallel at the same time, and when the multiple chips are tested simultaneously, different chips are distinguished by specific marks so as to distinguish the chips.

In an embodiment, to prevent data loss or side leakage of each chip on a wafer, as shown in fig. 5, fig. 5 is a schematic diagram of abnormal chip data, so that data cannot be found at a later stage, and a new environment needs to be debugged and then a test is performed, before a TR6836 tester stores a first maximum reference voltage and a first minimum reference voltage of each chip on the wafer corresponding to the first preset temperature in a preset format according to the wafer information, the TR6836 tester may convert the maximum reference voltage and the minimum reference voltage of each chip at different positions on the wafer into a data pattern; and when the data graph has a missing part, determining a chip with data abnormity on the wafer according to the missing position, and acquiring the data of the chip with data abnormity again. If the data pattern conforms to the predetermined shape, it is determined that the current data is not lost, as shown in fig. 6, where fig. 6 is a normal diagram of chip data.

Specifically, when the maximum reference voltage and the minimum reference voltage of each chip at different positions on the wafer, that is, the data to be converted, are obtained, the position to be converted into the graph and the corresponding rule, for example, the starting number, english comma, and the ending character, english #, are obtained, and then the conversion instruction is obtained, and the data to be converted is subjected to data mapping processing according to the conversion instruction, so that the data graph is obtained.

Step S102 is to calculate a temperature calibration value of the chip according to the first maximum reference voltage and the first minimum reference voltage, where the temperature calibration value is used to calibrate a temperature characteristic of the chip reference voltage.

In this embodiment, the temperature calibration value in the chip OTP should be set to a suitable value during the chip factory test, so as to minimize the amplitude of the reference voltage in the chip varying with the temperature, and the TR6836 tester calculates the optimized temperature calibration value according to the obtained reference voltage values at different temperatures by using a first preset formula. The first preset formula is as follows:

wherein, the R is a temperature calibration value, and round represents rounding.

Step S103, writing the temperature calibration value into a memory of the chip, and testing the chip.

In this embodiment, the TR6836 tester writes the temperature calibration value into the OTP of the chip to make the temperature characteristic of the chip reference voltage approach the actual value of the chip parameter, and then performs subsequent factory test on the chip to improve the accuracy of the subsequent test result of the chip.

In one embodiment, data can be written, but also read through a specific timing because of the OTP. Therefore, after the temperature calibration value is written into the memory of the chip, the TR6836 tester can obtain the parameter value of the preset position of the memory of the chip, the preset position is the position for storing the temperature calibration value, then the parameter value of the position for storing the temperature calibration value is compared with the temperature calibration value, and when the parameter value is consistent with the temperature calibration value, the temperature calibration value is determined to be successfully written.

In one embodiment, before testing the chip in step S103, an appropriate value may be set in the memory of the chip, so that the absolute value of the reference voltage in the chip is close to 1V, and the appropriate value is an absolute precision calibration value, and the determination of the specific absolute precision calibration value may include: since the ambient test temperature cannot be kept at a fixed value all the time and changes, and the chip is only affected by the temperature change after the temperature characteristic calibration is performed, the chip is affected the minimum, so that the measured reference voltage value is more accurate, the TR6836 tester writes the calculated temperature calibration value into the register of the chip in advance, then obtains the second maximum reference voltage and the second minimum reference voltage of the chip at the third preset temperature, calculates the absolute precision calibration value of the chip according to the second maximum reference voltage and the second minimum reference voltage in a preset manner, and writes the absolute precision calibration value into the memory of the chip after calculating the absolute precision calibration value. Wherein, the absolute accuracy calibration value is used for calibrating the absolute accuracy of the chip reference voltage. The third preset temperature may be 23 ℃.

Specifically, the preset manner may specifically include: and judging the second maximum reference voltage and the second minimum reference voltage to determine the absolute precision calibration value. If the second minimum reference voltage is greater than 1V, the absolute accuracy calibration value is the register value corresponding to the obtained second minimum reference voltage, for example, the register at the corresponding position of the chip is set to 00000 to obtain the second minimum reference voltage, and the current absolute accuracy calibration value is 00000; if the second maximum reference voltage is less than 1V, the absolute accuracy calibration value is the register value corresponding to the second maximum reference voltage, for example, if the register at the position corresponding to the chip is 11111, the current absolute accuracy calibration value is 11111; if the second minimum reference voltage is not greater than 1V and the second maximum reference voltage is not less than 1V, the absolute accuracy calibration value is obtained by using a second preset formula for the second maximum reference voltage and the second minimum reference voltage, where the second preset formula is:

wherein S is an absolute accuracy calibration value, V3 is a second minimum reference voltage, and V4 is a second maximum reference voltage.

Specifically, the second preset manner may specifically include: and calculating a target parameter by a third preset formula according to the second maximum reference voltage and the second minimum reference voltage, and determining the absolute precision calibration value according to the target parameter. If the target parameter is less than or equal to 0V, the absolute accuracy calibration value is a register value corresponding to the second minimum reference voltage, for example, the register at the corresponding position of the chip is set to 00000 to obtain the second minimum reference voltage, and the current absolute accuracy calibration value is 00000; if the target parameter is greater than or equal to 31V, the absolute accuracy calibration value is the register value corresponding to the second maximum reference voltage, for example, the register at the position corresponding to the chip is set to 11111, so as to obtain the second maximum reference voltage, and the current absolute accuracy calibration value is 11111; if the target parameter is greater than 0V and less than 31V, the absolute accuracy calibration value is obtained by rounding the target parameter, and the third predetermined formula is:

wherein, the T is a target parameter.

Further, since the OTP can not only write data but also read data through a specific timing. Therefore, after the absolute precision calibration value is written into the memory of the chip, the TR6836 tester can obtain the parameter value of the corresponding position of the memory of the chip, wherein the corresponding position is the position for storing the absolute precision calibration value, then compares the parameter value of the position for storing the absolute precision calibration value with the absolute precision calibration value, and determines that the absolute precision calibration value is successfully written when the parameter value is consistent with the absolute precision calibration value.

In one embodiment, before the chip is tested in step S103, the TR6836 tester may calibrate the frequency of the clock oscillator to improve the accuracy of the test result obtained when the chip is subjected to factory test items, and specifically, the TR6836 tester may write a preset value into a register of the chip when the chip is in an input command state according to the control command, measure the clock frequency signal output from a corresponding pin of the chip, determine a frequency calibration value corresponding to a range in which the clock frequency signal is located from a preset table, and write the frequency calibration value into a memory of the chip, where the frequency calibration value is used to calibrate the frequency of the clock oscillator of the chip. The preset table is as follows:

further, since the OTP can not only write data but also read data through a specific timing. Therefore, after the frequency calibration value is written into the memory of the chip, the TR6836 tester can obtain the parameter value of the corresponding position of the memory of the chip, the corresponding position is the position for storing the frequency calibration value, then the parameter value of the position for storing the frequency calibration value is compared with the frequency calibration value, and when the parameter value is consistent with the frequency calibration value, the frequency calibration value is determined to be successfully written.

Furthermore, after different calibration values need to be written into corresponding registers during calibration, the current calibration value is saved when the measured value meets the condition so as to wait for the OTP to be written in subsequently. The value in the register is emptied when the chip is reset, and the calibrated value is not emptied due to the reset of the chip after being written into the OTP, so that the TR6836 tester can write the calibrated values into the corresponding position of the OTP of the chip once after the temperature calibrated value, the absolute accuracy calibrated value and the frequency calibrated value are obtained, and then verify whether the write is successful, so as to improve the testing efficiency of the chip.

In an embodiment, as shown in fig. 2, the testing the chip in the testing module specifically includes: DC parametric tests, data retention tests, and functional tests. The DC parameter test comprises an open short circuit test, a reference voltage test under different temperature conditions and the like, and a test program is mainly written by a conventional test method of a PEB (positive emitter) and DPS (differential phase detector) board card configured in a TR6836 tester so as to complete the test according to the test program. In the data retention capacity test, partial data of the chip is burned to the OTP through a normal temperature test (CP1) process, and the OTP is tested again after the CP1 test and the high temperature aging at 250 ℃ for 24H, so that the data retention capacity of the chip is determined, and the OTP data is written in and read out by utilizing the memory function of a PEB board card of a TR6836 tester. The functional test is performed through a cross CP process, and the test comprises the step of realizing the calibration of the reference voltage temperature characteristic, the absolute precision and the frequency of the clock oscillator of the chip by using the field effect transistor.

Further, if a certain test item fails, the chip is determined as an abnormal chip, and abnormal information including a test result and chip information is recorded to distinguish and accurately search the abnormal chip, so that the processing means of testing the test item which does not pass the chip, performing abnormal cutting, discarding and the like can be rapidly performed in the later period. When the card is used, related devices need to be packaged in a surface mounting mode, and the related devices need to be close to the pin elements.

In the embodiment of the application, a control instruction is obtained, a first maximum reference voltage and a first minimum reference voltage of a chip are respectively obtained at a first preset temperature and a second preset temperature according to the control instruction, and the reference voltages of the chip are obtained by designing different temperatures, so that the accuracy of determining a subsequent calibration value is improved. And calculating the first maximum reference voltage and the first minimum reference voltage according to a first preset formula, determining a temperature calibration value of the chip, wherein the temperature calibration value is used for calibrating the temperature characteristic of the chip reference voltage, namely calibrating a standard value designed initially for the temperature characteristic, so that the temperature characteristic of the chip reference voltage is close to an actual value of a chip parameter, and parameter deviation caused by a manufacturing process is reduced.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

Fig. 7 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present disclosure, corresponding to the chip testing method described above, and as shown in fig. 7, the chip testing apparatus may include:

the obtaining module 701 is configured to obtain a control instruction, and obtain a first maximum reference voltage and a first minimum reference voltage of the chip at a first preset temperature and a second preset temperature according to the control instruction.

A calculating module 702, configured to calculate a temperature calibration value of the chip according to the first maximum reference voltage and the first minimum reference voltage, where the temperature calibration value is used to calibrate a temperature characteristic of the chip reference voltage.

The testing module 703 is configured to write the temperature calibration value into a memory of the chip, and test the chip.

In an embodiment, the obtaining module 701 may include:

and the writing unit is used for writing the first register value and the second register value into the register of the chip according to the control instruction.

And a first obtaining unit, configured to obtain, by using a field effect transistor, reference voltages corresponding to the first register value and the second register value output by the chip at a first preset temperature, where the first register value is used to determine the maximum reference voltage, and the second register value is used to determine a minimum reference voltage.

And the second acquisition unit is used for acquiring the reference voltages corresponding to the first register value and the second register value output by the chip by using a field effect transistor at a second preset temperature.

In one embodiment, the chip testing apparatus may further include:

and the storage module is used for acquiring the wafer information of the wafer and storing the first maximum reference voltage and the first minimum reference voltage of each chip on the wafer corresponding to the first preset temperature in a preset format according to the wafer information.

In one embodiment, the chip testing apparatus may further include:

and the conversion module is used for converting the maximum reference voltage and the minimum reference voltage of the chips at different positions on the wafer into a data graph.

And the abnormity determining module is used for determining a chip with data abnormity on the wafer according to the missing position when the data graph has the missing.

In one embodiment, the chip testing apparatus may further include:

and the writing module is used for writing the temperature calibration value into a register of the chip and acquiring a second maximum reference voltage and a second minimum reference voltage of the chip at a third preset temperature.

And a calibration value calculation module, configured to calculate an absolute accuracy calibration value of the chip according to the second maximum reference voltage and the second minimum reference voltage, where the absolute accuracy calibration value is used to calibrate the absolute accuracy of the chip reference voltage.

And the first calibration value writing module is used for writing the absolute precision calibration value into the memory of the chip.

In one embodiment, the chip testing apparatus may further include:

and the measuring module is used for writing a preset value into a register of the chip according to the control command and measuring the clock frequency signal of the chip.

And the calibration value determining module is used for determining a frequency calibration value corresponding to the range of the clock frequency signal, wherein the frequency calibration value is used for calibrating the frequency of the clock oscillator of the chip.

And a second calibration value writing module for writing the frequency calibration value into the memory of the chip.

In one embodiment, the chip testing apparatus may further include:

and the parameter value acquisition module is used for acquiring the parameter value of the preset position of the memory of the chip.

And the writing determining module is used for determining that the temperature calibration value is successfully written when the parameter value is consistent with the temperature calibration value.

In the embodiment of the application, a control instruction is obtained, a first maximum reference voltage and a first minimum reference voltage of a chip are respectively obtained at a first preset temperature and a second preset temperature according to the control instruction, and the reference voltages of the chip are obtained by designing different temperatures, so that the accuracy of determining a subsequent calibration value is improved. And calculating the first maximum reference voltage and the first minimum reference voltage according to a first preset formula, determining a temperature calibration value of the chip, wherein the temperature calibration value is used for calibrating the temperature characteristic of the chip reference voltage, namely calibrating a standard value designed initially for the temperature characteristic, so that the temperature characteristic of the chip reference voltage is close to an actual value of a chip parameter, and parameter deviation caused by a manufacturing process is reduced.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the apparatus and the module described above may refer to corresponding processes in the foregoing system embodiments and method embodiments, and are not described herein again.

Fig. 8 is a schematic structural diagram of a terminal device according to an embodiment of the present application. For convenience of explanation, only portions related to the embodiments of the present application are shown.

As shown in fig. 8, the terminal device 8 of this embodiment includes: at least one processor 800 (only one shown in fig. 8), a memory 801 connected to the processor 800, and a computer program 802, such as a chip test program, stored in the memory 801 and executable on the at least one processor 800. The processor 800 executes the computer program 802 to implement the steps in the chip testing method embodiments, such as the steps S101 to S103 shown in fig. 1. Alternatively, the processor 800 implements the functions of the modules in the device embodiments, for example, the functions of the modules 701 to 703 shown in fig. 7, when executing the computer program 802.

Illustratively, the computer program 802 may be divided into one or more modules, which are stored in the memory 801 and executed by the processor 800 to implement the present application. The one or more modules may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution process of the computer program 802 in the terminal device 8. For example, the computer program 802 may be divided into an acquisition module 701, a calculation module 702, and a test module 703, and the specific functions of each module are as follows:

an obtaining module 701, configured to obtain a control instruction, and obtain a first maximum reference voltage and a first minimum reference voltage of a chip at a first preset temperature and a second preset temperature according to the control instruction;

a calculating module 702, configured to calculate a temperature calibration value of the chip according to the first maximum reference voltage and the first minimum reference voltage, where the temperature calibration value is used to calibrate a temperature characteristic of the chip reference voltage;

the testing module 703 is configured to write the temperature calibration value into a memory of the chip, and test the chip.

The terminal device 8 may include, but is not limited to, a processor 800 and a memory 801. Those skilled in the art will appreciate that fig. 8 is merely an example of the terminal device 8, and does not constitute a limitation of the terminal device 8, and may include more or less components than those shown, or combine some of the components, or different components, such as an input-output device, a network access device, a bus, etc.

The Processor 800 may be a Central Processing Unit (CPU), and the Processor 800 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The storage 801 may be an internal storage unit of the terminal device 8, such as a hard disk or a memory of the terminal device 8. In other embodiments, the memory 801 may be an external storage device of the terminal device 8, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like provided on the terminal device 8. Further, the memory 801 may include both an internal storage unit and an external storage device of the terminal device 8. The memory 801 is used for storing an operating system, an application program, a Boot Loader (Boot Loader), data, and other programs, such as program codes of the computer programs. The above-described memory 801 may also be used to temporarily store data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned functions may be distributed as different functional units and modules according to needs, that is, the internal structure of the apparatus may be divided into different functional units or modules to implement all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the above modules or units is only one logical function division, and there may be other division manners in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. The computer program includes computer program code, and the computer program code may be in a source code form, an object code form, an executable file or some intermediate form. The computer-readable medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/terminal apparatus, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.