1. A semiconductor device, comprising:

a first connection pattern;

bit lines disposed over the first connection patterns in a vertical direction; and

a bit line contact pad disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed in an island shape when viewed along the vertical direction.

2. The semiconductor device according to claim 1, further comprising:

a conductive line disposed in the first layer, the conductive line not electrically connected with the bit line contact pad.

3. The semiconductor device according to claim 1,

a predetermined number of the bit line contact pads are spaced apart from each other by a predetermined distance in a first direction when viewed along the vertical direction.

4. The semiconductor device according to claim 3,

at least one of the predetermined number of bit line contact pads is offset in a second direction relative to other of the predetermined number of bit line contact pads when viewed in a plane along the vertical direction.

5. The semiconductor device according to claim 3,

the predetermined number of bit line contact pads are disposed over the same line in the first direction.

6. The semiconductor device according to claim 1, further comprising:

contacts coupling the bit line to the bit line contact pads and coupling the bit line contact pads to a lower connection structure.

7. The semiconductor device according to claim 1, wherein an arrangement of the plurality of bit line contact pads is symmetrical with respect to a dummy line formed to cross a center of the bit line contact region in the second direction.

8. The semiconductor device according to claim 1,

the bit line contact pads disposed in adjacent regions within the bit line contact region in the first direction have a mirror-symmetrical structure in the second direction based on a center point of the first direction.

9. The semiconductor device according to claim 1, further comprising:

a second connection pattern under the first connection pattern;

a first conductive contact plug coupled to a bottom surface of the second connection pattern;

a second conductive contact plug coupled between a bottom surface of the first connection pattern and a top surface of the second connection pattern;

a third conductive contact plug coupled between a bottom surface of the bit line contact pad and a top surface of the first connection pattern; and

a bit line contact coupled between the bit line and the bit line contact pad.

10. The semiconductor device according to claim 9, further comprising:

a transistor disposed under the second connection pattern,

wherein the second connection pattern is disposed over junction regions of the transistors.

11. The semiconductor device of claim 1, wherein the first connection pattern is angled to couple to the bit line contact pad.

12. A semiconductor device, comprising:

a plurality of gate electrodes formed to extend in a second direction and spaced apart from each other by a predetermined distance in a first direction when viewed from a vertical direction; and

a plurality of bit line contact pads spaced apart from each other by a predetermined distance in the first direction,

wherein each of the plurality of bit line contact pads disposed between a bit line and a lower connection structure in the vertical direction to electrically connect the bit line to the lower connection structure has an island shape when viewed along the vertical direction.

13. The semiconductor device according to claim 12,

portions of the plurality of bit line contact pads overlap the plurality of gate electrodes.

14. The semiconductor device according to claim 13,

the portions are arranged in a line in the first direction.

15. The semiconductor device according to claim 14,

one of the plurality of bit line contact pads is offset in the second direction from the remaining bit line contact pads of the plurality of bit line contact pads.

16. The semiconductor device according to claim 12,

at least one of the plurality of bit line contact pads is disposed over a junction region of a transistor along the vertical direction.

17. The semiconductor device of claim 12, wherein the plurality of bit line contact pads are arranged in a pattern.

18. A semiconductor device, comprising:

a substrate having a first region and a second region defined therein;

a logic circuit stacked on the substrate, the logic circuit including a page buffer circuit;

a memory cell array stacked on the logic circuit;

bit lines formed over the array of memory cells;

bit line contact pads formed in the first region, the bit line contact pads electrically connecting the bit lines to the page buffer circuit; and

a plurality of connection patterns formed under the bit line contact pads in a vertical direction,

wherein the bit lines and the bit line contact pads are electrically coupled to junction regions of transistors of the page buffer circuit through the plurality of connection patterns.

19. The semiconductor device according to claim 18, wherein the bit line contact pad is formed in a rectangular island shape when viewed from the vertical direction.

20. The semiconductor device according to claim 18, wherein the plurality of connection patterns comprise:

a first connection pattern formed under the bit line contact pad; and

a second connection pattern formed under the first connection pattern, the second connection pattern being electrically coupled to the junction regions of the transistors.

Background

The semiconductor device may include a memory cell array provided with a plurality of memory cells. The memory cell array may include a plurality of memory cells arranged in various shapes. In order to increase the integration of the semiconductor device, memory cells (3D) may be arranged three-dimensionally over a semiconductor substrate. In a manufacturing process for forming a three-dimensional (3D) semiconductor device, a plurality of material films may be stacked to form a stacked structure.

Disclosure of Invention

Various embodiments of the disclosed technology relate to a semiconductor device for improving the degree of freedom of wire (or wiring) connection.

According to an embodiment of the disclosed technology, a semiconductor device may include: a first connection pattern; bit lines disposed over the first connection patterns in a vertical direction; and a bit line contact pad disposed in the first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed in an island shape when viewed in a vertical direction.

According to another embodiment of the disclosed technology, a semiconductor device may include: a plurality of gate electrodes formed to extend in the second direction and spaced apart from each other by a predetermined distance in the first direction as viewed from the vertical direction; and a plurality of bit line contact pads spaced apart from each other by a predetermined distance in a first direction, wherein each of the plurality of bit line contact pads disposed between the bit line and the lower connection structure in the vertical direction to electrically connect the bit line to the lower connection structure has an island shape when viewed along the vertical direction.

In accordance with yet another embodiment of the disclosed technique, a semiconductor device may include a substrate in which a first region and a second region are defined; a logic circuit stacked on the substrate, the logic circuit including a page buffer circuit; a memory cell array stacked on the logic circuit; bit lines formed over the memory cell array; bit line contact pads formed in the first region, the bit line contact pads electrically connecting the bit lines to the page buffer circuit; and a plurality of connection patterns formed under the bit line contact pads in a vertical direction, wherein the bit lines and the bit line contact pads are electrically coupled to junction regions of transistors of the page buffer circuit through the plurality of connection patterns.

It is to be understood that both the foregoing general description and the following detailed description of the presently disclosed technology are exemplary and explanatory and are intended to provide further explanation of the scope of the disclosure to those skilled in the art.

Drawings

The above and other features and advantageous aspects of the disclosed technology will become apparent when considered with reference to the following detailed description when taken in conjunction with the accompanying drawings.

Fig. 1 is a perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 is a perspective view illustrating the semiconductor device of fig. 1 according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram illustrating a layout structure of the page buffer circuit in fig. 2 according to an embodiment of the present disclosure.

Fig. 4 is a schematic diagram illustrating the structure in fig. 1 according to an embodiment of the present disclosure.

Fig. 5 is a layout diagram illustrating elements of the semiconductor device in fig. 4 according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram illustrating a connection relationship between transistors included in the page buffer circuit in fig. 2 and bit line contact regions according to an embodiment of the present disclosure.

Fig. 7 is a plan view illustrating a layout structure of the bit line contact pad in fig. 6 according to an embodiment of the present disclosure.

Fig. 8 and 9 are plan views illustrating a layout structure of the bit line contact pad in fig. 6 according to an embodiment of the present disclosure.

Symbol of each element in the drawing

121: first conductive contact plug

123: connection pattern

125: second conductive contact plug

BLCP: bit line contact pad

Detailed Description

This patent document provides implementations and examples of a semiconductor device that substantially solve one or more problems associated with the limitations or disadvantages of the related art. Some implementations of the disclosed technology propose wire-connected semiconductor devices with improved and greater degrees of freedom.

Reference will now be made in detail to aspects of the disclosed technology, embodiments and examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

In connection with embodiments of the disclosed technology, specific structural and functional descriptions are disclosed for exemplary purposes only. The embodiments represent a limited number of possible embodiments, however, embodiments of the disclosed technology can be implemented in a variety of different ways without departing from the scope or spirit of the disclosed technology.

In describing the disclosed technology, the terms "first" and "second" may be used to describe a number of components, but the components are not limited by the terms in number or order. These terms may be used to distinguish one component from another component. For example, a first component may be termed a second component, and a second component may be termed a first component, without departing from the scope of the present disclosure.

The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the technology disclosed. Unless expressly stated otherwise, singular expressions may include plural expressions.

Unless defined otherwise, all terms used herein including technical or scientific terms have the same meaning as understood by those skilled in the art. Terms defined in general dictionaries may be analyzed to have the same meaning as the context of the relevant art and should not be analyzed to have an ideal meaning or an excessively formal meaning unless explicitly defined in the present application. The terminology used in the disclosed technology is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

Fig. 1 is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure. In fig. 1, the Third Direction (TD) is a direction perpendicular to a horizontal plane formed to extend in each of the First Direction (FD) and the Second Direction (SD). For example, the Third Direction (TD) may be perpendicular to each of the First Direction (FD) and the Second Direction (SD).

Referring to fig. 1, the semiconductor apparatus may include a logic circuit 20 and a memory cell array 30 disposed over a substrate 10.

The substrate 10 may be a single crystal semiconductor film. For example, the substrate 10 may be any one of a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, and a silicon germanium substrate, or may be an epitaxial thin film formed by a Selective Epitaxial Growth (SEG) process.

The memory cell array 30 may include a plurality of memory blocks, each of which is denoted by "BLK" to be described later. Each memory block may include a plurality of cell strings, each cell string being represented by "CST" to be described later. Each cell string may be electrically coupled to a gate stack, a bit line, and a source line. The gate stack may include a plurality of word lines and a plurality of select lines. Each select line may serve as a gate electrode of a corresponding select transistor, and each word line may serve as a gate electrode of a corresponding memory cell.

The logic circuit 20 may include an NMOS transistor, a PMOS transistor, at least one resistor, and at least one capacitor electrically coupled to the memory cell array 30. NMOS transistors, PMOS transistors, resistors, and capacitors may be used as constituent elements of the row decoder, the column decoder, the page buffer circuit, and the control circuit.

In some embodiments, the logic circuit 20 may be disposed between the memory cell array 30 and the substrate 10. For example, the memory cell array 30 may be formed to overlap with the logic circuit 20 as viewed in the Third Direction (TD). If the memory cell array 30 overlaps the logic circuit 20, the size of the area of the substrate 10 on which the memory cell array 30 and the logic circuit 20 are disposed can be reduced. In other embodiments, the memory cell array 30 may be disposed between the logic circuit 20 and the substrate 10.

Fig. 2 is a perspective view illustrating the semiconductor device of fig. 1 according to an embodiment of the present disclosure.

Referring to fig. 2, the logic circuit 20 may be disposed over the substrate 10, and the memory cell array 30 may be disposed over a source plate 31 located or disposed over the logic circuit 20.

The substrate 10 may be a first conductive semiconductor substrate, for example, a P-type conductive semiconductor substrate. The source plate 31 may be formed of a polysilicon layer.

The logic circuit 20 may include a row decoder 21, a page buffer circuit 22, and a peripheral circuit 23. The row decoder 21 may be formed to extend in the First Direction (FD) at or near the edge of the substrate 10.

The page buffer circuit 22 may be formed to extend in the Second Direction (SD). The page buffer circuit 22 may be formed under the memory cell array 30. The page buffer circuit 22 may be formed to overlap the memory cell array 30 at a lower portion of the memory cell array 30.

The peripheral circuits 23 may be disposed on the substrate 10 on opposite sides of the page buffer circuit 22 and arranged in the First Direction (FD) with the page buffer circuit 22. For convenience of description, a portion of the peripheral circuit 23 disposed on one side of the page buffer circuit 22 in the First Direction (FD) will be hereinafter defined as a first peripheral circuit 23A, and a portion of the peripheral circuit 23 disposed on the other side of the page buffer circuit 22 will be hereinafter defined as a second peripheral circuit 23B.

The first peripheral circuit 23A may be electrically connected to the second peripheral circuit 23B by a wire (RW) arranged to cross the upper portion of the page buffer circuit 22 in the First Direction (FD). The wire (RW) may transmit power and signals to the first peripheral circuit 23A and the second peripheral circuit 23B.

In some embodiments, the first and second peripheral circuits 23A and 23B may be respectively disposed at both sides of the page buffer circuit 22, and similarly, the row decoder 21 may be divided and coupled to opposite sides of the page buffer circuit 22 arranged in the first or second directions (FD, SD). However, the scope or spirit of the disclosed technology is not limited thereto, and in other embodiments, the directions and positions of the page buffer circuit 22, the peripheral circuit 23, and the row decoder 21 may be changed, and the numbers of the page buffer circuit 22, the peripheral circuit 23, and the row decoder 21 may also be changed as needed.

Bit Lines (BL) may be disposed over the memory cell array 30. The Bit Line (BL) may be formed to extend in the First Direction (FD) and may be disposed in the Second Direction (SD). Bit Lines (BL) may be used to interconnect the memory cell array 30 and the page buffer circuit 22, and may be electrically coupled to the memory cell array 30 and the page buffer circuit 22.

Page buffer circuit 22 and Bit Lines (BL) may be electrically connected through a plurality of Bit Line Contact Pads (BLCP) electrically coupled to page buffer circuit 22 and disposed in any one of line layers disposed between page buffer circuit 22 and source plate 31. The Bit Line (BL) may be coupled to the Bit Line Contact Pad (BLCP) through a Bit Line Contact (BLC) formed to penetrate the memory cell array 30 and the source plate 31 in the Third Direction (TD). The Bit Line Contact Pad (BLCP) may serve as a landing pad (landing pad) of the Bit Line Contact (BLC).

Fig. 3 is a schematic diagram illustrating a layout structure of the page buffer circuit 22 in fig. 2 according to an embodiment of the present disclosure.

Referring to fig. 3, the page buffer circuit 22 may include a plurality of Page Buffers (PB). The Page Buffer (PB) may be formed in a matrix-like shape having 8 rows. For example, the row or page buffers may extend in the Second Direction (SD), and the rows may be spaced apart in the First Direction (FD) or arranged along the First Direction (FD). The page buffer circuit 22 may include 8 stages Stage <0> to Stage <7 >. The number of stages of the page buffer circuit 22 can be understood as the number of Page Buffers (PB) arranged in the extending direction of the Bit Lines (BL). Although fig. 3 illustrates an example case in which the page buffer circuit 22 includes 8 stages for convenience of description, the scope or spirit of the disclosed technology is not limited thereto, and the number of stages may be changed in other embodiments.

The bit line contact region (BLOFC) may be disposed between two stages (i.e., a pair of stages) adjacent or neighboring each other. For example, the bit line contact region (BLOFC) may be provided between the Stage <0> and the Stage <1>, between the Stage <2> and the Stage <3>, between the Stage <4> and the Stage <5>, and between the Stage <6> and the Stage <7 >.

In the stacked semiconductor device shown in fig. 1, signal communication between the logic circuit 20 and the memory cell array 30 requires a line for electrically coupling a lower connection structure (such as, for example, a lower portion of the memory cell array) to a Bit Line (BL). Such a line may be provided in a specific region of the stacked semiconductor devices. For example, in the bit line contact area (BLOFC), a line for coupling a transistor included in the Page Buffer (PB) of the logic circuit 20 to a bit line of the memory cell array 30, and a corresponding pad may be provided.

The connection pattern 123 coupled to the Page Buffer (PB) included in the adjacent stage may be disposed in a bit line contact area (BLOFC). The connection pattern 123 may be coupled to an upper line by a contact plug 125.

Fig. 3 illustrates an exemplary case in which the connection patterns 123 are arranged in two columns in the Second Direction (SD). The connection pattern 123 in the first column (i.e., the upper column) may be coupled to the Page Buffer (PB) of the stage located at one side (i.e., the upper side) of the bit line contact region (BLOFC) in the First Direction (FD). The connection pattern 123 in the second column (i.e., the following) may be coupled to the Page Buffer (PB) of the stage located at the other side (i.e., the lower side) of the bit line contact region (BLOFC). Although fig. 3 illustrates an exemplary case where the connection patterns 123 are arranged in two columns for convenience of description, the number of columns included in the connection patterns 123 is not limited thereto.

Fig. 4 is a schematic diagram illustrating the structure in fig. 1 according to an embodiment of the present disclosure. For clarity, the interlayer insulating film is not shown in fig. 4. The First Direction (FD) and the Third Direction (TD) shown in fig. 4 are the same as those of fig. 1.

Fig. 4 illustrates a structure in which a Transistor (TR) included in the page buffer circuit 22 disposed in a lower layer or a lower portion near or adjacent to the substrate 10 is coupled to a bit line disposed in an upper layer of the page buffer circuit 22. The Transistor (TR) may be coupled through the lower connection structure 130, the Bit Line Contact Pad (BLCP), and the Bit Line Contact (BLC) such that the Transistor (TR) may be electrically connected to the corresponding Bit Line (BL).

The Transistor (TR) may be included in the Page Buffer (PB) shown in fig. 3. The Page Buffer (PB) shown in fig. 3 may include a plurality of transistors in addition to the Transistor (TR) shown in fig. 4.

The Transistor (TR) may include junctions Jn1 and Jn2 defined in an active region (ACT) of the substrate 10, and a gate electrode (G) formed in the active region (ACT) of the substrate 10. The active region (ACT) of the substrate 10 may be defined between device isolation layers (not shown) formed in the substrate 10.

The gate electrode (G) may be formed over the active region (ACT) of the substrate 10 together with a Gate Insulating Film (GIF) interposed therebetween. Each of the junctions Jn1 and Jn2 may be a region defined by injecting conductive impurities in an active region (ACT) of the substrate 10, and the junctions Jn1 and Jn2 may be disposed at opposite sides of the gate electrode (G). For example, each of junctions Jn1 and Jn2 may include an N-type impurity. Each of junctions Jn1 and Jn2 may function as a source junction or a drain junction.

The junction (Jn1) of the Transistor (TR) may be in contact with the lower connection structure 130. Junction (Jn1) may be one of the junctions of Transistor (TR) and may be defined in an active region (ACT) of substrate 10 separated by one or more device isolation layers (not shown).

The lower connection structure 130 may include a first conductive contact plug 121, a connection pattern 123, a second conductive contact plug 125, a connection pattern 131, and a third conductive contact plug 133 stacked between a junction (Jn1) of the Transistor (TR) and a Bit Line Contact Pad (BLCP).

In this example, the first conductive contact plug 121 may be in contact with the junction (Jn 1). The connection pattern 123 may be disposed over the first conductive contact plug 121. When viewed in the Third Direction (TD), the connection pattern 123 is larger in size than the first conductive contact plug 121, so that a contact margin increases. The second conductive contact plug 125 may be formed to extend in a direction from the connection pattern 123 to the Bit Line Contact Pad (BLCP).

The connection pattern 131 may be a metal pattern, and may be disposed on the second conductive contact plug 125. When viewed in the Third Direction (TD), the connection pattern 131 may be larger in size than the second conductive contact plug 125, so that a contact margin increases. The third conductive contact plug 133 may be disposed between the connection pattern 131 and the Bit Line Contact Pad (BLCP). The third conductive contact plug 133 may be disposed over the connection pattern 131, and may be formed to extend in a direction from the connection pattern 131 to the Bit Line Contact Pad (BLCP) such that the extended third conductive contact plug 133 can contact the Bit Line Contact Pad (BLCP) and the connection pattern 131.

The Bit Line Contact Pad (BLCP) may be a bit line connection pad coupling the lower connection structure 130 to the Bit Line (BL). The Bit Line Contact Pad (BLCP) may serve as a landing pad for landing the Bit Line Contact (BLC), and may be arranged to correspond to an arrangement structure of the Bit Line (BL).

The Bit Line Contact Pad (BLCP) may be electrically coupled to the connection pattern 123 and the contact plug 125 shown in fig. 3. The Bit Line Contact Pad (BLCP) may be formed of a conductive line. The Bit Line Contact Pad (BLCP) may be formed or disposed in the same layer as the conductive line (a). The Bit Line Contact Pad (BLCP) may be disconnected from the conductive line (a) so that the Bit Line Contact Pad (BLCP) may be formed in an island shape. That is, the conductive line (a) may be cut or segmented to obtain individual Bit Line Contact Pads (BLCP). As a result, the degree of freedom of line connection of the remaining portion of the conductive line (A) which is now disconnected from the Bit Line Contact Pad (BLCP) can be improved.

The Cell String (CST) may be contained in the memory Block (BLK). Each Cell String (CST) may be coupled to the Bit Line (BL) after passing through the bit line contact plug (BCT). The Cell String (CST) may be formed in various shapes. The Cell String (CST) may be coupled to the Bit Line Contact Pad (BLCP) by the Bit Line (BL) and the Bit Line Contact (BLC). In this case, the Bit Line Contact (BLC) may be formed as a conductive contact plug.

In some embodiments, the Bit Line (BL), the Bit Line Contact (BLC), the Bit Line Contact Pad (BLCP), the third conductive contact plug 133, the connection pattern 131, the second conductive contact plug 125, and the connection pattern 123 may be vertically coupled to each other in a column in the Third Direction (TD), thereby forming a vertical structure. The lower connection pattern 123 may be electrically connected to a line of the Transistor (TR) of the Page Buffer (PB) through the first conductive contact plug 121.

A specific region where the Bit Line (BL), the Bit Line Contact (BLC), the Bit Line Contact Pad (BLCP), the third conductive contact plug 133, the connection pattern 131, the second conductive contact plug 125, and the connection pattern 123 are arranged may be defined as a bit line contact region (BLOFC) (i.e., a first region to be described later) as viewed in the Third Direction (TD). In addition, a region located at both sides of the bit line contact region (BLOFC) in the First Direction (FD) may be defined as a Second Region (SR) (described later). The Transistor (TR) of the Page Buffer (PB) may be disposed above the Second Region (SR). In the Second Region (SR), the connection pattern 123 may be electrically coupled to the junction (Jn1) of the Transistor (TR) through the first conductive contact plug 121.

Fig. 5 is a layout diagram illustrating elements of the semiconductor device in fig. 4 according to an embodiment of the present disclosure. To simplify the drawings, only the line layers needed to further explain embodiments of the present disclosure are illustrated in fig. 5.

Referring to fig. 5, a first region (BLOFC) and a Second Region (SR) may be defined in a substrate (not shown). Bit Line Contact Pads (BLCP) coupled to the Page Buffers (PB) included in an adjacent pair of stages may be arranged in the first region (BLOFC).

In fig. 5, the first region (BLOFC) may be substantially the same as the bit line contact region (BLOFC) shown in fig. 4. The Second Region (SR) may be located at both sides of the bit line contact region (BLOFC) in the First Direction (FD). A Page Buffer (PB) shown in fig. 4 may be disposed above the second region SR.

The connection pattern 131 may be disposed in a lower plane of a Bit Line Contact Pad (BLCP). The connection pattern 131 may be formed in a line shape extending in the First Direction (FD). However, some portions of the connection pattern 131 may be configured to have an angle, curve, or bend such that the connection pattern 131 crosses the connection pattern 123 of the Bit Line Contact Pad (BLCP) when viewed in the Third Direction (TD). For example, the connection pattern 131 may form a folding line (doglegg) surrounding the Bit Line Contact Pads (BLCP) offset from each other in the Second Direction (SD) in the bit line contact region (BLOFC).

The overall extending direction of the connection pattern 131 may be the same as the First Direction (FD). The Second Direction (SD) may be considered as an arrangement direction of the connection patterns 131. The connection patterns 131 may be arranged at intervals of a constant pitch in the Second Direction (SD).

The Bit Line Contact Pad (BLCP) may be disposed in a lower plane or lower portion of the bit line (not shown). That is, the Bit Line Contact Pad (BLCP) may be disposed over the connection pattern 131 or over the upper surface of the connection pattern 131, and over the lower connection structure 130. The Bit Line Contact Pad (BLCP) may be formed in the bit line contact region (BLOFC). Each Bit Line Contact Pad (BLCP) may be formed in a rectangular island shape by disconnecting and removing some portions or sections of the connection line. For example, a rectangular island shape is different from a line shape formed by extending a conductive line formed on the same layer in a predetermined direction, but may refer to an integrated pad in which at least some portions of the rectangular island shape are disconnected and configured independently of each other.

Not only the lower connection structure 130 but also a contact plug (not shown) for electrically coupling the upper line contact (BLC) to the bit line may be formed over the Bit Line Contact Pad (BLCP). The Bit Line Contact Pad (BLCP) may be electrically connected to the lower connection pattern 123 through the second conductive contact plug 125. The third conductive contact plug 133 may be formed under the Bit Line Contact Pad (BLCP) such that the third conductive contact plug 133 may be electrically connected to the lower connection pattern 131. The Bit Line Contact (BLC) may be formed over the Bit Line Contact Pad (BLCP) such that the Bit Line Contact (BLC) may be electrically coupled to the bit line.

The conductive line (a) is disposed in a Second Region (SR) located at both sides (i.e., upper and lower sides) with respect to the first region (BLOFC). However, within the first region (BLOFC), the conductive line (a) may be disconnected from the Bit Line Contact Pad (BLCP) such that the conductive line (a) is not coupled to the bit line (not shown). That is, as shown in fig. 4, although the conductive line (a) is formed or disposed in the same layer as the Bit Line Contact Pad (BLCP), the conductive line (a) is not electrically coupled to the Bit Line Contact Pad (BLCP). As a result, the wires (a) have an improved degree of freedom in wire connection because they are not electrically connected to the bit lines (not shown) (i.e., the wires (a) are not used as bit line connection pads). Although the wires (a) shown in fig. 5 are disposed in the horizontal direction as an example for convenience of description, the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that the wires (a) can also be disposed in the vertical direction or other directions.

The conductive lines (a) and the connection patterns 131 disposed in the Second Region (SR) located at both sides (i.e., upper and lower sides) with respect to the bit line contact region (BLOFC) may be electrically coupled to the Page Buffers (PB) of the stages also located or disposed in the Second Region (SR) (see fig. 3).

The bitline contact pad (BLCP) may serve as a landing pad for the bitline contact, such that the bitline contact pad (BLCP) can be coupled to the bitline through the upper bitline contact (BLC). Referring to fig. 5, a dummy line formed to cross the center portion of the bit line contact region (BLOFC) in the Second Direction (SD) is represented by a line "VL". As a result, the Bit Line Contact Pad (BLCP) disposed at one side (i.e., upper side) of the line (VL) can be electrically coupled to the Page Buffer (PB) of the stage located at the same side (i.e., upper side) in the First Direction (FD) (see fig. 3). Similarly, the Bit Line Contact Pad (BLCP) located at the other side (lower side) of the line (VL) may be electrically coupled to the Page Buffer (PB) of the stage located at the same side (lower side) in the First Direction (FD) (see fig. 3).

The Bit Line Contact Pad (BLCP) located at one side of the dummy line (VL) and the other Bit Line Contact Pads (BLCP) located at the other side of the dummy line (VL) may be mirror images of each other with respect to the dummy line (VL). The Bit Line Contact Pad (BLCP) located in an adjacent region within the bit line contact region (BLOFC) may have a mirror-symmetrical structure arranged in the Second Direction (SD) based on a central portion of the First Direction (FD), i.e., a vertical direction intersecting the dummy line VL.

A predetermined number of Bit Line Contact Pads (BLCP) disposed above the bit line contact region (BLOFC) may be paired (or grouped), so that the Bit Line Contact Pads (BLCP) may be formed as the paired Bit Line Contact Pads (BLCP). As a result, such a pair of patterns may be disposed above the same connection pattern 131 in the First Direction (FD). A predetermined number of Bit Line Contact Pads (BLCP) may be continuously formed in the First Direction (FD) when viewed in the Third Direction (TD).

For example, the Bit Line Contact Pad (BLCP) may be configured in such a manner that four patterns (i.e., four bit line contact pads) on one side of the dummy line VL are arranged in the form of one line in the First Direction (FD). However, one of the four Bit Line Contact Pads (BLCP) may be disposed to be offset or shifted in the Second Direction (SD) with respect to the remaining three Bit Line Contact Pads (BLCP). Accordingly, the offset Bit Line Contact Pad (BLCP) may correspond to a connection pattern 131 different from the connection patterns 131 corresponding to the other three Bit Line Contact Pads (BLCP).

Although fig. 5 exemplarily discloses that the Bit Line Contact Pads (BLCP) are arranged in such a manner that three Bit Line Contact Pads (BLCP) are arranged in one direction and the remaining one Bit Line Contact Pad (BLCP) is offset in the other direction for convenience of description, the scope or spirit of the disclosed technology is not limited thereto and other configurations may be used.

Fig. 6 is a schematic diagram illustrating a connection relationship between transistors included in the page buffer circuit in fig. 2 and a bit line contact region (BLOFC) according to an embodiment of the present disclosure.

Referring to fig. 6, a Transistor (TR) may be included in the page buffer circuit (PB) shown in fig. 3. The Transistor (TR) may be used to read out data from the Cell String (CST), or may be used to program the Cell String (CST). Each Transistor (TR) may be coupled between a bitline connection node (BLN) and another bitline connection node (BLCM).

The line of the bit line connection node (BLN) may be coupled to the bit line contact region (BLOFC) through the line (HV) of the high voltage page buffer. In addition, a line of the bit line connection node (BLCM) may be coupled to a Line (LV) of the low voltage page buffer. The Transistor (TR) may be coupled to the lower wire (i.e., the connection pattern 123). The connection pattern 123 may be electrically coupled to a Bit Line Contact Pad (BLCP) included in the bit line contact region (BLOFC).

In the stacked semiconductor device, the Transistor (TR) included in the Page Buffer (PB) may be formed below the memory cell array 30 based on the Third Direction (TD). The connection pattern 123 (i.e., the line HV) of the Transistor (TR) may be electrically coupled to a Bit Line (BL) of the memory cell array 30 formed at an upper portion of the stacked semiconductor devices.

Fig. 7 is a plan view illustrating a layout structure of the bit line contact pad in fig. 6 according to an embodiment of the present disclosure.

Referring to fig. 7, the gate electrode (G) may correspond to the gate electrode of each Transistor (TR) shown in fig. 6. The gate electrode (G) may be disposed over the active region (ACT). Each gate electrode (G) may extend in the Second Direction (SD). The gate electrodes (G) may be spaced apart from each other by a predetermined distance in the First Direction (FD).

In the bit line contact region (BLOFC), the Bit Line Contact Pads (BLCP) may be spaced apart from each other by a predetermined distance in the First Direction (FD). The Bit Line Contact Pad (BLCP) may be coupled to the corresponding connection pattern.

The Bit Line Contact Pad (BLCP) may be electrically connected to the corresponding connection pattern 123 through the second conductive contact plug 125. The Bit Line Contact Pad (BLCP) may be electrically coupled to the lower connection pattern 131 through the third conductive contact plug 133. The Bit Line Contact Pad (BLCP) may be electrically coupled to the Bit Line (BL) through a Bit Line Contact (BLC).

For convenience of description, detailed descriptions of the connection pattern 123, the connection pattern 131, and the Bit Line Contact (BLC), which are substantially the same as those described in connection with fig. 4, will be omitted herein.

The Bit Line Contact Pad (BLCP) may be disposed to overlap some portions of the gate electrode (G). For example, four Bit Line Contact Pads (BLCP) are illustrated in fig. 3, and two Bit Line Contact Pads (BLCP) from among the four Bit Line Contact Pads (BLCP) may be disposed to overlap the adjacent gate electrode (G). Although three adjacent Bit Line Contact Pads (BLCP) among the four Bit Line Contact Pads (BLCP) are arranged in the form of one line in the First Direction (FD), only one Bit Line Contact Pad (BLCP) may be disposed to be offset from the remaining three Bit Line Contact Pads (BLCP) in the Second Direction (SD).

At least one of the connection patterns (e.g., the connection pattern 123) coupled to the four Bit Line Contact Pads (BLCP) may be disposed at least over the junction region (Jn1) of the Transistor (TR). That is, at least one of the four connection patterns 123 may be disposed in a space between the gate electrodes (G) adjacent to each other in the First Direction (FD). In other words, when viewed in the Third Direction (TD), the connection pattern 123 coupled to the Bit Line Contact Pad (BLCP) disposed in the bit line contact region (BLOFC) may be disposed above the junction (Jn1) of the lower Transistor (TR). When viewed along the Third Direction (TD), the upper line contact pad (BLCP) may be electrically coupled to the junction (Jn1) of the lower Transistor (TR) through the connection pattern 123.

In the above-described embodiments of the disclosed technology, the Bit Line Contact Pad (BLCP) may be formed over the bit line contact region (BLOFC), and each of the Bit Line Contact Pads (BLCP) may be formed in an island shape in which a line structure of the Bit Line Contact Pad (BLCP) is disconnected from other connection lines formed in the same layer. Therefore, the semiconductor device according to the embodiment of the disclosed technology can improve the degree of freedom of line connection of the conductive line (a) in the remaining region other than the bit line contact region (BLOFC).

Fig. 8 and 9 are plan views illustrating a layout structure of a Bit Line Contact Pad (BLCP) in fig. 6 according to an embodiment of the present disclosure.

Referring to fig. 8, the Bit Line Contact Pads (BLCP) in the bit line contact region (BLOFC) may be arranged in the same pattern. The patterns each including four Bit Line Contact Pads (BLCP) may be arranged in four columns in the Second Direction (SD). Two row patterns each including four Bit Line Contact Pads (BLCP) may be arranged in two stages within the bit line contact area (BLOFC) in the First Direction (FD).

Referring to fig. 9, the same pattern including four Bit Line Contact Pads (BLCP) per bit line contact area (BLOFC) may be arranged in four columns in the Second Direction (SD). The patterns each including four Bit Line Contact Pads (BLCP) may be arranged in a zigzag, or angled arrangement. In addition, patterns each including four Bit Line Contact Pads (BLCP) may be arranged in four stages within the bit line contact area (BLOFC) in the First Direction (FD).

The above-described embodiments have exemplarily disclosed that the patterns each including four Bit Line Contact Pads (BLCP) in the bit line contact regions (BLOFC) are arranged in two or four stages in the second direction (FD). However, the scope or spirit of the disclosed technology is not limited thereto, and in other embodiments, the number of Bit Line Contact Pads (BLCP) and the arrangement shape of the Bit Line Contact Pads (BLCP) may also be changed as needed.

As is apparent from the above description, a semiconductor device based on implementation of the disclosed technology can improve the degree of freedom of wire connection.

Those skilled in the art will appreciate that the embodiments may be carried out in other specific ways than those herein set forth without departing from the spirit and essential characteristics of the present disclosure. The above embodiments are therefore to be construed in all aspects as illustrative and not restrictive. The scope of the present disclosure should be determined by the appended claims and their legal equivalents, rather than by the foregoing description. Furthermore, all changes which come within the meaning and range of equivalency of the appended claims are intended to be embraced therein. In addition, those skilled in the art will understand that claims that are not explicitly cited in each other in the appended claims may be presented in combination as an embodiment or included as a new claim by amendment after the application is filed.

Although a number of exemplary embodiments have been described, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. In particular, many variations and modifications are possible in the component parts and/or arrangements within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Cross Reference to Related Applications

This patent document claims priority and benefit from korean patent application No.10-2020-0032053, filed on 16/3/2020, which is hereby incorporated by reference in its entirety.