1. A pulse peak hold circuit, comprising:

a first node;

a second node;

a first pulse peak hold branch comprising a gain amplification module, a first peak holder, a gain attenuation module, and a first gating cell;

the input end of the gain amplification module is connected with the first node, the output end of the gain amplification module is connected with the input end of the first peak value holder, the output end of the first peak value holder is connected with the input end of the gain attenuation module, the output end of the gain attenuation module is connected with the input end of the first gate control unit, and the output end of the first gate control unit is connected with the second node;

a second pulse peak hold branch including a second peak holder and a second gating unit;

an input end of the second peak value holder is connected with the first node, an output end of the second peak value holder is connected with an input end of the second gating unit, and an output end of the second gating unit is connected with the second node;

and the input end of the path selection module is connected with the output end of the gain amplification module, the output end of the path selection module is connected with the control end of the first gate control unit, and the output end of the path selection module is also connected with the control end of the second gate control unit.

2. The pulse peak hold circuit of claim 1, further comprising a pulse stretching module, an input of the pulse stretching module being used for inputting a high-speed pulse signal, and an output of the pulse stretching module being connected to the first node.

3. The pulse peak holding circuit according to claim 1, wherein the path selection module comprises a threshold voltage comparison unit and a path selection unit;

the input end of the threshold voltage comparison unit is connected with the output end of the gain amplification module, the output end of the threshold voltage comparison unit is connected with the input end of the path selection unit, the output end of the path selection unit is connected with the first gate control unit, and the output end of the path selection unit is also connected with the control end of the second gate control unit.

4. The pulse peak holding circuit according to claim 3, wherein the threshold voltage comparing unit comprises a comparator, a first resistor and a second resistor;

the in-phase input end of the comparator is connected with the output end of the gain amplification module, one end of the first resistor is connected with direct-current voltage, the other end of the first resistor is connected with one end of the second resistor, one end of the second resistor is further connected to the inverting input end of the comparator, and the other end of the second resistor is grounded.

5. The pulse peak hold circuit according to claim 4, wherein the path selection unit comprises a D flip-flop;

the clock input end of the D trigger is connected to the output end of the comparator U1, the data input end of the D trigger is connected to the direct-current voltage, the reset end of the D trigger is connected to a reset signal, the output end of the D trigger is connected to the control end of the first gate control unit, and the output end of the D trigger is further connected to the control end of the second gate control unit.

6. A pulse peak hold circuit according to claim 2, wherein the pulse stretching module comprises a plurality of cascaded integrators.

7. The pulse peak hold circuit according to any one of claims 1-6, wherein the first gate control unit employs a first transmission gate, and the second gate control unit employs a second transmission gate.

8. The pulse peak hold circuit of any one of claims 1-6, wherein the first pulse peak hold circuit comprises a first voltage follower connected in series between the first peak holder and the gain attenuation module;

the second pulse peak holding branch comprises a second voltage follower connected in series between the second peak holder and the second gate control unit.

9. The pulse peak hold circuit according to any one of claims 1-6, wherein the gain attenuation module comprises a first amplifier, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

one end of a fifth resistor is connected to the direct-current voltage, the other end of the fifth resistor is connected with one end of a sixth resistor, one end of the fifth resistor is further connected to the non-inverting input end of the first amplifier, the other end of the sixth resistor is grounded, the inverting input end of the first amplifier is connected with the output end of the first amplifier, the output end of the amplifier is further connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the input end of the first gate control unit, the other end of the fourth resistor is further connected with one end of a third resistor, and the other end of the third resistor is connected with the output end of the first voltage comparator.

10. A control method applied to a pulse peak hold circuit according to claim 1, comprising the steps of:

the path selection module outputs a control signal according to an output result of the gain amplification module, wherein the control signal is used for controlling the conduction of the first gate control unit or the second gate control unit.

Background

In order to achieve higher ranging accuracy, the pulse width of a transmitted laser pulse signal is usually only a few nanoseconds, and in order to obtain data such as surface reflectivity of a measured object, the amplitude of an echo signal of the laser pulse signal is indispensable to be measured. Accurate laser pulse echo signal amplitude can be obtained by sampling echo signals by using an ultra-high-speed analog-to-digital converter (ADC), however, an ADC chip meeting such requirements needs an extremely high sampling rate, and such an ADC is not only expensive, but also has huge power consumption. Therefore, for most pulse laser radars, a peak holding circuit is usually used to store the peak value of a laser pulse echo signal, and then a subsequent stage of ADC samples the laser pulse echo signal, so that the performance requirement of the ADC can be greatly reduced, and the power consumption and cost of the whole circuit can be effectively reduced.

However, in the pulse peak holding circuit including the diode in the prior art, since a certain voltage drop exists between two ends of the diode, the voltage stored on the capacitor always has a certain difference with the input voltage, which reduces the precision of the peak holding circuit, and since the amplitude of the input signal must be greater than the voltage drop of the diode to be held by the storage capacitor, the output dynamic range of the peak holding circuit is also limited. A common method to overcome the voltage drop of the diode is to introduce a transconductance amplifier (OTA) and a pair of current mirrors to charge the storage capacitor instead of the diode, and since the voltage drop introduced into the diode is avoided by using the current mirrors, the pulse peak hold circuit incorporating the OTA and the current mirrors has higher accuracy and larger dynamic range than the pulse peak hold circuit including the diode. However, the small signal precision of the pulse peak holding circuit with the OTA and the current mirror is limited by the response speed of the peak holding circuit and the offset voltage of the OTA, and if the accuracy of the small signal is further improved and the dynamic range of the small signal is enlarged, the transconductance value of the OTA needs to be further increased, but the excessive transconductance value can cause the static current of the OTA to be significantly increased and the output swing of the OTA to be reduced, so that the dynamic range of the large signal is reduced while the power consumption of the circuit is increased, and the purposes of improving the accuracy and increasing the dynamic range cannot be achieved. Therefore, both of the pulse peak holding circuits in the prior art cannot simultaneously achieve high accuracy and wide dynamic range peak detection for high-speed pulse signals.

Disclosure of Invention

In order to solve at least one technical problem existing in the prior art to a certain extent, the invention aims to: a pulse peak hold circuit and a control method are provided.

The technical scheme adopted by the invention is as follows:

a pulse peak hold circuit comprising:

a first node;

a second node;

a first pulse peak hold branch comprising a gain amplification module, a first peak holder, a gain attenuation module, and a first gating cell;

the input end of the gain amplification module is connected with the first node, the output end of the gain amplification module is connected with the input end of the first peak value holder, the output end of the first peak value holder is connected with the input end of the gain attenuation module, the output end of the gain attenuation module is connected with the input end of the first gate control unit, and the output end of the first gate control unit is connected with the second node;

a second pulse peak hold branch including a second peak holder and a second gating unit;

an input end of the second peak value holder is connected with the first node, an output end of the second peak value holder is connected with an input end of the second gating unit, and an output end of the second gating unit is connected with the second node;

and the input end of the path selection module is connected with the output end of the gain amplification module, the output end of the path selection module is connected with the control end of the first gate control unit, and the output end of the path selection module is also connected with the control end of the second gate control unit.

Further, the pulse peak holding circuit further comprises a pulse stretching module, an input end of the pulse stretching module is used for inputting a high-speed pulse signal, and an output end of the pulse stretching module is connected with the first node.

Further, the path selection module comprises a threshold voltage comparison unit and a path selection unit;

the input end of the threshold voltage comparison unit is connected with the output end of the gain amplification module, the output end of the threshold voltage comparison unit is connected with the input end of the path selection unit, the output end of the path selection unit is connected with the first gate control unit, and the output end of the path selection unit is also connected with the control end of the second gate control unit.

Further, the threshold voltage comparison unit includes a comparator, a first resistor and a second resistor;

the in-phase input end of the comparator is connected with the output end of the gain amplification module, one end of the first resistor is connected with direct-current voltage, the other end of the first resistor is connected with one end of the second resistor, one end of the second resistor is further connected to the inverting input end of the comparator, and the other end of the second resistor is grounded.

Further, the path selection unit includes a D flip-flop;

the clock input end of the D trigger is connected to the output end of the comparator, the data input end of the D trigger is connected to the direct-current voltage, the reset end of the D trigger is connected to a reset signal, the output end of the D trigger is connected to the control end of the first gate control unit, and the output end of the D trigger is further connected to the control end of the second gate control unit.

Further, the pulse stretching module comprises a plurality of cascaded integrators.

Further, the first gate control unit adopts a first transmission gate, and the second gate control unit adopts a second transmission gate.

Further, the first pulse peak hold circuit comprises a first voltage follower connected in series between the first peak holder and the gain attenuation module;

the second pulse peak holding branch comprises a second voltage follower connected in series between the second peak holder and the second gate control unit.

Further, the gain attenuation module comprises a first amplifier, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;

one end of a fifth resistor is connected to the direct-current voltage, the other end of the fifth resistor is connected with one end of a sixth resistor, one end of the fifth resistor is further connected to the non-inverting input end of the first amplifier, the other end of the sixth resistor is grounded, the inverting input end of the first amplifier is connected with the output end of the first amplifier, the output end of the amplifier is further connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the input end of the first gate control unit, the other end of the fourth resistor is further connected with one end of a third resistor, and the other end of the third resistor is connected with the output end of the first voltage comparator.

The other technical scheme adopted by the invention is as follows:

a control method applied to the above-mentioned pulse peak hold circuit includes the following steps:

the path selection module outputs a control signal according to an output result of the gain amplification module, wherein the control signal is used for controlling the conduction of the first gate control unit or the second gate control unit.

The invention has the beneficial effects that: the input high-speed pulse signal is subjected to peak holding processing through the first peak holding branch and the second peak holding branch, and the path selection module determines a first holding value of the first peak holding branch or a second holding value of the second peak holding branch as final output according to the input high-speed pulse signal, so that the dynamic range of the peak holding circuit is expanded.

Drawings

FIG. 1 is a circuit schematic of a prior art pulse peak hold circuit including a diode;

FIG. 2 is a circuit schematic of a prior art pulse peak hold circuit including an OTA and a current mirror;

FIG. 3 is a block diagram of a pulse peak hold circuit of an embodiment of the present invention;

FIG. 4 is a circuit schematic of a gain amplification module of an embodiment of the present invention;

FIG. 5 is a schematic circuit diagram of a pulse stretching module in an embodiment of the invention;

fig. 6 is a simulation of various pulse peak hold circuits in an embodiment of the invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.

Referring to fig. 1, the related art pulse peak holding circuit including a diode is composed of a fourth amplifier OPA4, a fifth amplifier OPA5, a diode D1, a storage capacitor C1, a resistor R, and a reset switch K1, wherein a non-inverting input terminal of the fourth amplifier OPA4 is connected to a high-speed pulse signal input terminal VI through the resistor R, and an output terminal of the fourth amplifier OPA4 is connected to an anode of the first diode D1. The fifth amplifier OPA5 is connected as a voltage buffer with unity gain, when the high-speed pulse signal enters the pulse peak holding circuit from the high-speed pulse input terminal signal VI, the storage capacitor C1 will be charged to a voltage approximately the same as the voltage of the input high-speed pulse signal through the first diode D1, and since the fifth amplifier OPA5 plays a role of voltage buffering, the voltage of the output terminal VO and the voltage of the storage capacitor C1 keep the same until the reset switch K1 is closed to release the charge in the storage capacitor C1, at which time, the voltage value of the output terminal VO is 0.

The pulse peak holding circuit including the diode has a certain voltage drop across the first diode D1, the voltage stored in the storage capacitor C1 is always different from the voltage of the input high-speed pulse signal, which reduces the accuracy of the peak holding circuit, and the output dynamic range of the peak holding circuit is limited because the amplitude of the input signal must be larger than the voltage drop of the first diode D1 to be held by the storage capacitor C1.

Referring to fig. 2, in order to solve the problem caused by the diode, a transconductance amplifier OTA is used in the prior art to replace the fourth amplifier OPA4 in fig. 1, and a pair of current mirrors (MP1 and MP2) is introduced at the output end of the transconductance amplifier OTA to replace the first diode D1 to charge the storage capacitor C1. The pulse peak hold circuit of fig. 2 has higher accuracy and larger dynamic range than the pulse peak hold circuit of fig. 1 because the voltage drop introduced into the first diode D1 is avoided by using a current mirror. However, the small-signal precision of the peak holding circuit in fig. 2 is limited by the response speed of the peak holding circuit and the offset voltage of the transconductance amplifier OTA, and if the accuracy under the small signal is further improved and the dynamic range is enlarged, the transconductance value of the transconductance amplifier OTA needs to be further increased to reduce the offset voltage while improving the bandwidth thereof, but the excessive transconductance value may cause the quiescent current of the transconductance amplifier OTA to be significantly increased and the output swing of the transconductance amplifier OTA to be reduced, so that the dynamic range of the large signal is also reduced while increasing the power consumption of the circuit, and the purposes of improving the accuracy and increasing the dynamic range cannot be achieved. Therefore, both peak hold circuits in the prior art cannot simultaneously achieve high accuracy and wide dynamic range peak detection for high-speed pulse signals.

In order to solve the above problem at least partially, as shown in fig. 3, the present embodiment provides a pulse peak hold circuit including:

a first node M;

a second node N;

the first pulse peak holding branch comprises a gain amplification module, a first peak holder, a gain attenuation module 2 and a first gating unit 3;

the input end of the gain amplification module is connected with the first node M, the output end of the gain amplification module is connected with the input end of the first peak value holder, the output end of the first peak value holder is connected with the input end of the gain attenuation module 2, the output end of the gain attenuation module 2 is connected with the input end of the first gate control unit 3, and the output end of the first gate control unit 3 is connected with the second node N;

a second pulse peak holding branch including a second peak holder and a second gating unit 4;

the input end of the second peak value holder is connected with the first node M, the output end of the second peak value holder is connected with the input end of the second gating unit 4, and the output end of the second gating unit 4 is connected with the second node N;

the input end of the path selection module 1 is connected with the output end of the gain amplification module, the output end of the path selection module 1 is connected with the control end of the first gate control unit 3, and the output end of the path selection module 1 is further connected with the control end of the second gate control unit 4.

Specifically, the first node M is used for introducing a high-speed pulse signal into the pulse peak hold circuit, and the first pulse peak hold branch and the second pulse peak hold branch are both connected to the first node M for performing peak hold processing on the high-speed pulse signal input by the first node M. The first pulse peak holding branch circuit obtains a first amplified pulse signal by amplifying the amplitude of the input high-speed pulse signal by Av times through the gain amplification module, the first amplified pulse signal is held in the first peak holder so as to obtain a first holding value, the first holding value is input to the gain attenuation module 2, the gain attenuation module 2 reduces the amplitude of the first holding value by Av times so as to obtain a first attenuated pulse signal, and the first attenuated pulse signal is output to a second node N under the condition that the first gate control unit 3 is switched on; the second peak holding branch uses the second peak holder to perform peak holding on the high-speed pulse signal introduced by the first node M to obtain a second holding value, and the second holding value is output to the second node N when the second gate control unit 4 is turned on.

It should be noted that the first peak holder in the present application may adopt any one of the peak holding circuits shown in fig. 1, fig. 2, and others, and similarly, the second peak holder may adopt any one of the peak holding circuits shown in fig. 1, fig. 2, and others.

In addition, referring to fig. 4, the gain amplifying module may be composed of a plurality of amplifiers, and in a specific embodiment, the gain amplifying module includes three amplifiers, and the sixth amplifier OPA6 is connected in the form of a unity gain buffer, and the output of the sixth amplifier OPA6 is connected to the seventh resistor R7 and the ninth resistor R9. The seventh resistor R7 and the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 form a feedback network to control the closed loop gain of the seventh amplifier OPA7 and the eighth amplifier OPA 8.

In addition, the input end of the path selection module 1 of the present application is connected to the output end of the gain amplification module, and the gain amplification module is used for amplitude amplification of the input high-speed pulse signal, so that the first amplified pulse signal, that is, the amplified high-speed pulse signal, may also enter the path selection module 1, the path selection module 1 compares the amplitude of the input first amplified pulse signal with the preset voltage amplitude, when the amplitude of the first amplified pulse signal is determined to be lower than the preset voltage amplitude, it indicates that the amplitude of the input high-speed pulse signal is smaller, and belongs to a small signal, the path selection module 1 selects the first peak hold circuit to perform peak hold on the input high-speed pulse signal, and conversely, when the amplitude of the first amplified pulse signal is determined to be greater than the preset voltage amplitude, it indicates that the amplitude of the input high-speed pulse signal is larger, the path selection module 1 selects the second peak holding circuit to carry out peak holding on the input high-speed pulse signal without amplitude amplification.

As can be seen from the above, in the present application, the first peak holding branch and the second peak holding branch are used to perform peak holding processing on the input high-speed pulse signal, and the path selection module 1 determines, according to the input high-speed pulse signal, the first holding value of the first peak holding branch or the second holding value of the second peak holding branch as the final output, so that the original dynamic range of the peak holding circuit is expanded by Av times.

As a further optional implementation manner, the pulse peak holding circuit further includes a pulse stretching module, an input end of the pulse stretching module is used for inputting the high-speed pulse signal, and an output end of the pulse stretching module is connected to the first node M.

Specifically, the front end of the first node M is further provided with a pulse stretching module, the pulse stretching module is used for stretching an input high-speed pulse signal, stretching the high-speed pulse signal into a low-speed pulse signal, and the introduction of the pulse stretching module greatly reduces the bandwidth requirements of the first peak value holder and the second peak value holder, so that the first peak value holder and the second peak value holder can achieve higher accuracy under the conditions of lower bandwidth and lower power consumption. The pulse stretching module includes a plurality of cascade integrators, and referring to fig. 5, the function of stretching the input high-speed pulse into a pulse signal with a lower speed is realized by integrating the input high-speed pulse through the plurality of cascade Gm-C integrators. The cascade stage number of the Gm-C integrator cascade, the R and C values can be adjusted according to requirements, and different cascade stage numbers and RC time constants have different broadening effects.

Further as an optional implementation, the path selection module 1 includes a threshold voltage comparison unit and a path selection unit;

the input end of the threshold voltage comparison unit is connected with the output end of the gain amplification module, the output end of the threshold voltage comparison unit is connected with the input end of the path selection unit, the output end of the path selection unit is connected with the first gate control unit 3, and the output end of the path selection unit is also connected with the control end of the second gate control unit.

Specifically, the present embodiment divides the path selection block 1 into two units.

The threshold voltage comparison unit is used for judging whether the input high-speed pulse signal is a large signal or a small signal according to the relation between the input first amplification pulse signal and the threshold voltage. In a specific embodiment, the threshold voltage comparing unit includes a comparator U1, a first resistor R1, and a second resistor R2;

the non-inverting input end of the comparator U1 is connected with the output end of the gain amplification module, one end of the first resistor R1 is connected with a direct-current voltage, the other end of the first resistor R1 is connected with one end of the second resistor R2, one end of the second resistor R2 is also connected with the inverting input end of the comparator U1, and the other end of the second resistor R2 is grounded.

Specifically, the inverting input terminal of the comparator U1 is connected between the first resistor R1 and the second resistor R2, and the comparator U1 outputs a comparison result of 0 or 1 according to the voltage value input to the non-inverting input terminal and the voltage value input to the inverting input terminal, where the voltage input to the inverting input terminal is a threshold voltage, and the comparison result can be adjusted by changing the resistance values of the first resistor R1 and the second resistor R2.

The path selection unit is used for controlling the first gating unit 3 or the second gating unit 4 to be conducted according to the result output by the threshold voltage comparison unit, so that the first holding value of the first peak holding branch or the second holding value of the second peak holding branch is used as the final holding value.

In a particular embodiment, the path selection unit includes a D flip-flop;

the clock input end of the D flip-flop is connected to the output end of the comparator U1, the data input end of the D flip-flop is connected to a direct-current voltage, the reset end of the D flip-flop is connected to a reset signal, the output end of the D flip-flop is connected to the control end of the first gate control unit 3, and the output end of the D flip-flop is further connected to the control end of the second gate control unit 4.

The process of controlling the opening of the first transmission gate or the second transmission gate by the D trigger is as follows:

if the output result of the comparator U1 is 0, the signal input to the clock input terminal of the D flip-flop is 0, the control signal output by the first output terminal Q of the D flip-flop is 0, the control signal output by the second output terminal Q is 1, the first transmission gate is opened under the action of the control signal output by the D flip-flop, the second transmission gate is closed under the action of the control signal, the first holding value of the first peak holding branch is output, and similarly, if the output result of the comparator U1 is 1, the signal input to the data input terminal of the D flip-flop is 1, the control signal output by the first output terminal Q of the D flip-flop is 1, the control signal output by the second output terminal Q is 0, the second transmission gate is opened under the action of the control signal, the first transmission gate is closed under the action of the control signal, the peak holding value of the second peak holding branch is output, thus, the function of path selection is realized. Referring to fig. 1, in a specific embodiment, the first gate control unit 3 uses a first transmission gate TG1, and the second gate control unit 4 uses a second transmission gate TG2, but other switching elements may be used as the gate control units, which is not described herein.

Further alternatively, the first pulse peak hold circuit comprises a first voltage follower OPA2, the first voltage follower OPA2 being connected in series between the first peak holder and the gain attenuation block 2;

the second pulse peak hold branch comprises a second voltage follower OPA3, the second voltage follower OPA3 being connected in series between the second peak holder and the second gate control unit 4.

Specifically, the first voltage follower OPA2 is further disposed at the output terminal of the first peak keeper in the first peak holding branch, and serves as an output buffer for the first held value output by the first peak keeper, and for the same reason, the second voltage follower OPA3 serves as an output buffer for the second held value output by the second peak keeper.

The gain attenuation module 2 further includes, as an alternative embodiment, a first amplifier OPA1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;

one end of a fifth resistor R5 is connected to the dc voltage, the other end of the fifth resistor R5 is connected to one end of a sixth resistor R6, one end of the fifth resistor R5 is further connected to the non-inverting input terminal of the first amplifier OPA1, the other end of the sixth resistor R6 is grounded, the inverting input terminal of the first amplifier OPA1 is connected to the output terminal of the first amplifier OPA1, the output terminal of the amplifier is further connected to one end of a fourth resistor R4, the other end of the fourth resistor R4 is connected to the input terminal of the first gate control unit 3, the other end of the fourth resistor R4 is further connected to one end of a third resistor R3, and the other end of the third resistor R3 is connected to the output terminal of the first voltage comparator U1.

Specifically, the gain attenuation module 2 is used for reducing the amplitude of the input signal. The non-inverting input terminal of the first amplifier OPA1 is connected between the fifth resistor R5 and the sixth resistor R6, and the third resistor R3, the fourth resistor R4, and the first amplifier OPA1 form a voltage scaling circuit.

Finally, referring to fig. 6, the present application further provides a simulation diagram of a pulse peak holding circuit including a diode, a pulse peak holding circuit including a transconductance amplifier and a current mirror, and a high-speed pulse peak pulse holding circuit of the present application, a left diagram portion of fig. 6 is an input-output relationship diagram in the whole input range, a right diagram is an input-output relationship diagram when the input pulse amplitude is small, a horizontal axis is the input high-speed pulse peak voltage, and a vertical axis is the voltage held and output by the pulse peak holding circuit. The pulse peak holding circuit including the diode can hold the pulse peak well only in the interval of 0.1V-0.3V. The pulse peak value holding circuit comprising the transconductance amplifier and the current mirror can well hold the peak value of the pulse only when the amplitude of the input pulse is larger, but a larger error exists when the amplitude of the input pulse is smaller. The high-speed pulse peak value holding circuit can well hold the peak value within the range of the input pulse amplitude from a few millivolts to 0.6V.

The invention also provides a control method, which is applied to the pulse peak holding circuit and comprises the following steps:

s1: the path selection module outputs a control signal according to the output result of the gain amplification module, and the control signal is used for controlling the conduction of the first gate control unit or the second gate control unit.

Specifically, the input end of the path selection module is connected to the output end of the gain amplification module, and the gain amplification module is used for performing amplitude amplification on the input high-speed pulse signal, so that the first amplified pulse signal, that is, the amplified high-speed pulse signal, also enters the path selection module, the path selection module compares the amplitude of the input first amplified pulse signal with a preset voltage amplitude, when the amplitude of the first amplified pulse signal is judged to be lower than the preset voltage amplitude, the amplitude of the input high-speed pulse signal is smaller and belongs to a small signal, the path selection module selects the first peak holding circuit to perform peak holding on the input high-speed pulse signal, and conversely, when the amplitude of the first amplified pulse signal is judged to be greater than the preset voltage amplitude, the amplitude of the input high-speed pulse signal is larger, the path selection module selects the second peak holding circuit to carry out peak holding on the input high-speed pulse signal without amplitude amplification. By distinguishing large signals from small signals, the dynamic range of the pulse peak holding circuit is expanded.

In this embodiment, the path selection module may adopt a combination of the comparator U1 and the D flip-flop, or may also adopt a controller to implement, and a circuit structure having functions of comparing voltage and outputting a control signal may be used as the path selection module, which is not described herein in a limiting manner.

In summary, the pulse peak holding circuit and the control method thereof of the present application have the following advantages:

1. the pulse stretching module is used for carrying out pulse width stretching on the input high-speed pulse signal, so that the bandwidth requirement of the peak holding circuit is greatly reduced, and the peak holding circuit can realize higher accuracy under the condition of lower bandwidth and power consumption.

2. The input high-speed pulse signal is divided into two paths to be processed, a large signal and a small signal are distinguished, and a proper path output holding value is selected through a path selection module to be used as final output, so that the original dynamic range of the pulse peak holding circuit is expanded.

3. Since the narrow pulse signal is widened before being input into the peak holding circuit, the bandwidth and power consumption requirements of the peak holding circuit are effectively reduced, and therefore, the power consumption generated by using two signal processing paths and two peak holding circuits in the scheme is not higher than that of the traditional single peak holding circuit.

It will be understood that all or some of the steps, systems of methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.