1. A transmission gate based radio frequency signal generating system, comprising:

the radio frequency interference source generator is manufactured on the same chip with the circuit to be tested and is used for generating interference signals to the circuit to be tested;

the radio frequency interference source generator comprises a plurality of transmission gates;

and the control module is used for controlling the conduction condition of the transmission gate so as to control the frequency and the waveform of the interference signal.

2. The transmission-gate based radio frequency signal generation system according to claim 1, wherein n of the transmission gates form a transmission gate group, and the radio frequency interference source generator comprises m of the transmission gate groups;

the control ends of all the transmission gates are connected with the control module;

the input ends of all transmission gates in the same transmission gate group are interconnected to be used as the input end of the transmission gate group, and the output ends of all transmission gates in the same transmission gate group are interconnected to be used as the output end of the transmission gate group;

the input voltages of the transmission gates in the same transmission gate group are the same, and the input voltages of the transmission gates in different transmission gate groups are different;

and the output ends of the transmission gate groups are interconnected and connected with a circuit to be tested.

3. The transmission-gate-based radio-frequency signal generation system according to claim 2, wherein the control module controls the radio-frequency interference source generator to generate the interference signal with any one of a sine wave, a triangular wave or a square wave by controlling the conduction condition of the transmission gate.

4. The transmission-gate based radio frequency signal generation system according to claim 2, wherein n is greater than or equal to 3, and m is greater than or equal to 3.

5. The transmission-gate based radio frequency signal generating system as claimed in claim 1, wherein said transmission gate comprises an NMOS and a PMOS;

the drain electrode of the NMOS is connected with the drain electrode of the PMOS and is used as the input end of the transmission gate;

the source electrode of the NMOS is connected with the source electrode of the PMOS and is used as the output end of the transmission gate;

the grid of NMOS and the grid of PMOS are as the control end of transmission gate, and control module is connected with the control end of transmission gate for the condition of switching on of control transmission gate, and when the transmission gate switches on, input voltage is transmitted to the output of transmission gate from the input of transmission gate.

6. The transmission-gate based radio frequency signal generation system as claimed in claim 1, wherein the radio frequency interference source generator comprises two transmission gates, and the control module controls the two transmission gates to generate a square wave.

7. The transmission gate based radio frequency signal generation system according to claim 1, wherein the control module is an FPGA control circuit.

8. The method for controlling a transmission gate based radio frequency signal generating system according to any one of claims 1 to 7, comprising the steps of:

controlling the size of an input signal according to the power of an interference signal;

according to the frequency of the interference signal, the control module controls the conducting frequency of the transmission gate;

according to the waveform of the interference signal, the control module controls the conducting quantity of the transmission gates.

Background

According to the standard IEC62132 of electromagnetic immunity of integrated circuits, a common method for measuring the immunity of a chip includes: TEM cell and broadband TEM cell methods, heavy current injection methods, direct radio frequency power injection (DPI) methods, and bench faraday cage methods. A typical DPI test structure is shown in fig. 4, wherein a radio frequency signal generated by a radio frequency signal generator is amplified by a power amplifier, transmitted to a chip injection end to interfere with a voltage at a pin of a chip to be tested (DUT), and a directional coupler is used to observe an injected radio frequency power value. And sweeping the frequency of the radio frequency interference signal, and recording the critical failure power of the chip to be tested at each frequency point to obtain an immunity curve of the chip to be tested.

When the DPI method is used for noise immunity test, when the interference frequency is increased, the interference power actually injected into the chip is greatly attenuated due to the low-pass filtering effect of the packaging pin of the chip to be tested and the impedance mismatch of the injection interference path, and if the injection interference power is tried to be increased to cause the chip to be tested to be invalid, the required power is very high, and potential safety hazards such as breakdown of external circuit elements can be caused.

The rf power amplifier is often prone to power amplifier failure due to environmental reasons or improper operation, and the failure reasons include: 1) electrostatic breakdown caused by transportation and contact; 2) input power level out of safe range; 3) load mismatching, for example, the load is open or short-circuited, so that radio frequency energy cannot be effectively transmitted to cause heat accumulation, and the power amplifier is burnt; 4) too high ambient temperature or poor heat dissipation. In summary, the external direct power injection method has a great limitation in the high frequency range.

Disclosure of Invention

To at least solve one of the technical problems in the prior art to some extent, an object of the present invention is to provide a system and a method for generating a radio frequency signal based on a transmission gate.

The technical scheme adopted by the invention is as follows:

a transmission gate based radio frequency signal generating system comprising:

the radio frequency interference source generator is manufactured on the same chip with the circuit to be tested and is used for generating interference signals to the circuit to be tested;

the radio frequency interference source generator comprises a plurality of transmission gates;

and the control module is used for controlling the conduction condition of the transmission gate so as to control the frequency and the waveform of the interference signal.

Further, n transmission gates form a transmission gate group, and the radio frequency interference source generator comprises m transmission gate groups;

the control ends of all the transmission gates are connected with the control module;

the input ends of all transmission gates in the same transmission gate group are interconnected to be used as the input end of the transmission gate group, and the output ends of all transmission gates in the same transmission gate group are interconnected to be used as the output end of the transmission gate group;

the input voltages of the transmission gates in the same transmission gate group are the same, and the input voltages of the transmission gates in different transmission gate groups are different;

and the output ends of the transmission gate groups are interconnected and connected with a circuit to be tested.

Further, the control module controls the radio frequency interference source generator to generate an interference signal with any waveform of a sine wave, a triangular wave or a square wave by controlling the conduction condition of the transmission gate.

Further, n is greater than or equal to 3, and m is greater than or equal to 3.

Further, the transmission gate comprises an NMOS and a PMOS;

the drain electrode of the NMOS is connected with the drain electrode of the PMOS and is used as the input end of the transmission gate;

the source electrode of the NMOS is connected with the source electrode of the PMOS and is used as the output end of the transmission gate;

the grid of NMOS and the grid of PMOS are as the control end of transmission gate, and control module is connected with the control end of transmission gate for the condition of switching on of control transmission gate, and when the transmission gate switches on, input voltage is transmitted to the output of transmission gate from the input of transmission gate.

Further, the radio frequency interference source generator comprises two transmission gates, and the control module controls the two transmission gates to generate square waves.

Further, the control module is an FPGA control circuit.

The other technical scheme adopted by the invention is as follows:

the control method of the radio frequency signal generation system based on the transmission gate comprises the following steps:

controlling the size of an input signal according to the power of an interference signal;

according to the frequency of the interference signal, the control module controls the conducting frequency of the transmission gate;

according to the waveform of the interference signal, the control module controls the conducting quantity of the transmission gates.

The invention has the beneficial effects that: the invention solves the defects of the existing injection method and also avoids the problem of instrument damage caused by improper operation by generating the radio frequency interference signal with any frequency, any amplitude and any waveform in the chip.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made on the drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a transmission gate based RF signal generation system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a transmission gate according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a set of transmission gates in an embodiment of the invention;

FIG. 4 is a schematic diagram of a test structure of the direct RF power injection method in an embodiment of the present invention;

FIG. 5 is a schematic diagram of an RF signal generating system according to an embodiment of the present invention;

FIG. 6 is an equivalent circuit diagram of the output voltage in the embodiment of the present invention;

FIG. 7 is a diagram illustrating the relationship between the output node voltage amplitude and the transmission gate number according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating transmission gate control signals according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of an output sinusoidal signal according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a square wave generator of an on-chip RF interference source according to an embodiment of the present invention;

FIG. 11 is a waveform diagram of the output when the frequency of the input square wave Vin is 500MHz according to the embodiment of the present invention;

fig. 12 is a waveform diagram of the output when the frequency of the input square wave Vin is 250MHz in the embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.

As shown in fig. 1, in order to solve the problem of the conventional rf source technology in the chip immunity test process, the present embodiment provides a rf signal generating system based on a transmission gate, which can generate an interference power signal superimposed with an rf waveform.

The structure of the transmission gate is shown in fig. 2 and is formed by connecting a P-channel and an N-channel enhancement type MOSFET in parallel, wherein a P-transistor substrate is connected with a high level, an N-transistor substrate is connected with a low level, and a gate is used as a control signal to determine the conduction of the MOS transistor. When the gate of the NMOS is connected to high level and the gate of the PMOS is connected to low level, the pass gate is turned on, and VI is Vo. When the NMOS grid is connected with low level and the PMOS grid is connected with high level, the transmission gate is cut off.

The input/output ends of a plurality of transmission gates are supposed to be connected in parallel to form a unit (namely a transmission gate group), three groups of the structure with the same number of transmission gates share the output end, the output amplitude is controlled by utilizing the input voltage of each group, and an external FPGA generates a control signal to determine the opening number of each group of transmission gates, so that the output waveform changes along with the time period. The FPGA control signal waveform is regulated and controlled to obtain any output waveform, such as sine, triangular wave, square wave and the like. The structure of the transmission gate group is shown in figure 3, and the structure of the on-chip radio frequency interference source generator is shown in figure 1.

The operation of the on-chip rf interferer generator described above is explained in detail below with reference to fig. 5-9.

As shown in FIG. 5, it is assumed that each set of transmission gate is formed by connecting three transmission gate inputs/outputs in parallel, and the three sets of transmission gate have a common output to be connected to a standby circuit, and the inputs of the three sets of transmission gate are V₀+A、V₀、V₀And A, controlling a transmission gate conducting signal to change the output voltage by using the FPGA.

Any transmission gate structure of the circuit structure is consistent, and the resistance value is set to be R when the circuit structure is conducted. The conducting number of each group of transmission gates is marked as N_A、N_B、N_C. Considering A, B two sets of transmission gates are conductive and C is not, the circuit can be simply equivalent to R_A、R_BIn series connection, the voltages of the nodes at the two ends are respectively V₀+A、V₀Such asAs shown in fig. 6. The output terminal voltage is:

similarly, when considering B, C that there are two sets of transmission gates conducting and set A is not conducting, the output voltage is expressed as:

the magnitude of the output voltage variation can be related to the number of transmission gates according to the above equation, as shown in fig. 7.

Assuming that the output waveform is a sine wave, the amplitude of the output voltage should be from 0 → A → 0 → -A → 0. There are various paths that can be implemented according to fig. 7, with the most sampling points and the most accurate waveform when varying periodically along the arrow. To achieve the amplitude jump of the selected path, the FPGA should generate the control signal waveform shown in fig. 8 for controlling the number of the transmission gates in each group. The resulting stepped waveform of fig. 9 is approximately sinusoidal. If the number of sampling points is fixed, the time interval can be changed to change the frequency of the output signal. In order to improve the precision of output waveform, the sampling time interval can be reduced, and the number of transmission gates is increased to increase the sampling points. Referring to fig. 8 and 9, the same transmission gate group includes a plurality of transmission gates, and the equivalent resistance of the transmission gates can be controlled by controlling the number of transmission gates in the transmission gate group, so as to control V_OUT。

If other waveforms need to be output, a suitable voltage amplitude change path can be selected according to the table listed in fig. 7, and transmission gate control signals generated by the FPGA can be drawn, so that triangular waves, square waves and the like can be realized.

If only the generation of square wave signals is considered, the original circuit structure can be simplified, only two transmission gates are needed, and an on-chip radio frequency interference source structure capable of outputting approximate square waves of waveforms can be obtained. Setting a square wave signal IN and its inverse signalAnd controlling the transmission gates to be opened to realize that only one transmission gate is conducted when the signal IN is at a high/low level. The input voltages of the two transmission gates respectively determine the high level and the low level of the voltage of the output node, so that a power supply signal with the frequency determined by the input square wave IN and the amplitude determined by the input voltage of the transmission gate is generated, and the power supply signal is equivalent to the power supply signal after the interference of the radio frequency signal.

A simplified version of the on-chip interferer-only circuit structure that generates square waves is shown in FIG. 10, where injection of square waves at Vin determines the output signal frequency f_RFIAnd the input ends UP and DW of the transmission gate input the direct current power supply to determine the amplitude of the output signal. The working principle is as follows: input frequency of f_RFIThe square wave signal Vin is used for controlling the conduction of the transmission gates A and B, when Vin is at low level, the transmission gate A is conducted, and the output voltage is V_UP(ii) a When Vin is at high level, transmission gate B is turned on and output voltage is V_DW. The output terminal can obtain a frequency f_RFIPeak value of V_UPA trough value of V_DWThe signal source of (2) is equivalent to a direct current source signal after interference of a radio frequency source. In FIG. 10, UP and DW correspond to V in the above-described structure, respectively₀+ A and V₀And A, externally connecting a direct current power supply.

The circuit structure of fig. 10 is subjected to simulation test based on Hspice, and the results are shown in fig. 11 and 12:

when Vin inputs a square wave with a voltage value of 2V and a frequency of 500MHz, nodes UP and DW at two ends of the transmission gate A, B respectively input amplitude-modulated voltages, so that the output voltage Vout periodically fluctuates with a certain amplitude value AMP around the center voltage of 1V. As shown in fig. 11, the output waveform is adjusted to 0.8V (i.e., V) from top to bottom, respectively_UP＝1.8V，V_DW0.2V), AMP 0.2V (i.e., V)_UP＝1.2V，V_DW0.8V). The frequency of the input square wave Vin is changed to 250MHz, the other conditions are kept unchanged, and the output waveforms are as shown in fig. 12, and the adjustment amplitudes AMP is 0.8V and AMP is 0.2V from top to bottom respectively. It can be observed that the output waveform of the circuit structure has a frequency, V, determined by the signal Vin_UPDetermining the peak value, V_DWDetermining the valley value, approximating a square wave, can better obtain a power signal fluctuating with arbitrary amplitude around a certain voltage value, and the frequency thereof can be adjustedAnd the modulation is equivalent to a power supply signal after the interference of the radio frequency signal.

In summary, in the present embodiment, by changing the input signal of the transmission gate and the control signal of the FPGA, the power signal with any frequency and amplitude after being interfered by the radio frequency signal is generated in the chip without depending on any external radio frequency signal generating device (including the radio frequency signal generator and the power amplifier). Therefore, the defects of the existing injection method are overcome, and the problem of instrument damage caused by improper operation is also solved.

In alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flow charts of the present invention are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are performed independently.

Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the described functions and/or features may be integrated in a single physical device and/or software module, or one or more functions and/or features may be implemented in a separate physical device or software module. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary for an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be understood within the ordinary skill of an engineer, given the nature, function, and internal relationship of the modules. Accordingly, those skilled in the art can, using ordinary skill, practice the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative of and not intended to limit the scope of the invention, which is defined by the appended claims and their full scope of equivalents.

In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.