1. A FLASH memory erasure interrupt recovery test method is used for carrying out interrupt recovery test on NOR FLASH, and is characterized by comprising the following steps:

s1, writing first data information into a non-operation area in the flash memory, and setting the bus clock frequency as the limit frequency of the flash memory;

s2, writing second data information into the operation area in the flash memory;

s3, circularly executing the circular operation of erasing, checking null, programming and checking in sequence by the sector of the selected operation area, interrupting the erasing operation and recovering the erasing operation according to the set interval time in the erasing process, and detecting and recording whether the first data information of the non-operation area changes at intervals in the circular operation process of the sector;

and S4, when the selected sector cycle execution operation reaches the set cycle number, ending the cycle.

2. The method of claim 1, further comprising the step of executing before step S1:

and S0, testing the performance of the flash memory chip, and ensuring that the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.

3. The method of claim 2, further comprising the step after step S4 of:

s5, checking the performance of the flash memory chip, and analyzing whether the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.

4. The flash memory erase interruption recovery test method of claim 1, wherein the first data information comprises data 0 and data 1.

5. The method of claim 1, wherein the step S3 is performed by interrupting the erase operation at a predetermined interval, and the predetermined interval for resuming the erase operation includes an interruption interval for starting the interrupted erase operation and a resumption interval for delaying the resumption of the erase operation after the interrupted erase operation.

6. The method of claim 1, wherein an interval threshold is set in step S3, and when the sector performs the loop operation for each threshold number of times, it is detected and recorded whether the first data information in the non-operation area changes.

7. The method of claim 1, wherein the sectors in step S3 are one or more sectors randomly selected from an operation area.

8. A FLASH memory erase interrupt recovery test apparatus for performing an interrupt recovery test on NOR FLASH, comprising:

the writing module is used for respectively writing first data information and second data information into a non-operation area and an operation area in the flash memory;

the selection module is used for selecting the sector in the operation area;

the cyclic operation module is used for circularly executing erasing-blank checking-programming-verifying operation on the sector selected by the selection module;

the interrupt recovery module can send out an interrupt erasing operation instruction and a recovery erasing operation instruction at intervals; the detection module is used for detecting and recording whether the first data information of the non-operation area changes or not;

the interruption recovery module can send out an interruption erasing operation instruction and an erasing operation recovery instruction at intervals when the circulation module carries out erasing operation; the detection module may intermittently detect and record whether the first data information of the non-operation area changes during the loop operation of the loop operation module on the selected sector.

9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-7.

10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-7.

Background

Nor Flash generally has two functions: storing program code and storing data. Nor Flash mainly includes three types of data operations: data read, data program, and data erase. The XIP (execution in chip) operation of the CPU on Flash is realized by sending a read command to Flash to read a code stored in Flash. The process of storing data to Flash by the CPU is as follows: firstly, an erasing instruction is sent to clear a certain block of Flash, then a programming instruction is sent to write user data to a certain page of the block, and finally a reading instruction is sent to read and verify the data. The erase and program operations typically require a certain amount of time during which Flash is generally not able to respond to other commands than to interrupt commands and status register read commands. Nor Flash can only perform one operation at the same time, namely when one operation is in progress, Flash does not respond to other operations, such as erasing and programming processes, and does not respond to a read instruction.

When the CPU reads an instruction from the Flash, if the Flash is carrying out erasing or programming operation, the CPU needs to send an interrupt instruction to interrupt the programming or erasing operation of the Flash, and the state inside the Flash can be stored; after the instruction is taken, the CPU needs to send an erasing or programming recovery instruction to the Flash, the state of the inside of the Flash can be recovered, and the erasing or programming operation is continuously completed.

Since the erase operation is the most complex algorithm in Flash, the erase operation includes a complex state machine and switching of a voltage up to plus or minus 10V, the erase operation affects not only the operating region but also the non-operating region. When the chip is designed, the interruption and recovery flow of Flash erasure need to be tested, if the interruption and recovery flow of Flash erasure are processed incompletely by the chip design, the internal data of Flash will jump, if the data or the data in a code area are overturned, if the data or the data in the code area are overturned, the Flash device is permanently damaged. The existing method for testing the interruption and recovery flow of Flash erasure has the following defects:

1. the erase operation is generally interrupted randomly, the interruption time point cannot ensure that all time segments of the erase algorithm are covered, and the risk of incomplete verification exists, namely the influence of the erase interruption and recovery operation on the chip cannot be reflected comprehensively and effectively;

2. the influence of the erasure interruption and the recovery operation on the data of the non-operation area is not detected;

3. actually, the erase interruption recovery operation may affect the establishment and maintenance of the internal voltage of Flash, but the conventional method generally adopts a lower frequency to perform the test, and the problem that the Flash memory chip is difficult to measure at the low frequency, that is, the influence of the erase interruption and recovery operation on the chip cannot be fully reflected.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide a flash memory erase interruption recovery test method, apparatus, electronic device and storage medium, so as to comprehensively, effectively and fully reflect the influence of erase interruption and recovery operations on a chip.

In a first aspect, an embodiment of the present application provides a FLASH memory erase interrupt recovery test method, which is used for performing an interrupt recovery test on a NOR FLASH memory, and the method includes the following steps:

s1, writing first data information into a non-operation area in the flash memory, and setting the bus clock frequency as the limit frequency of the flash memory;

s2, writing second data information into the operation area in the flash memory;

s3, circularly executing the circular operation of erasing, checking null, programming and checking in sequence by the sector of the selected operation area, interrupting the erasing operation and recovering the erasing operation according to the set interval time in the erasing process, and detecting and recording whether the first data information of the non-operation area changes at intervals in the circular operation process of the sector;

and S4, when the selected sector cycle execution operation reaches the set cycle number, ending the cycle.

The method for testing recovery from flash memory erase interruption further includes the following steps before step S1:

and S0, testing the performance of the flash memory chip, and ensuring that the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.

The method for testing recovery from flash memory erase interruption further includes the following steps after step S4:

s5, checking the performance of the flash memory chip, and analyzing whether the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.

The flash memory erasure interruption recovery testing method comprises the following steps that first data information comprises data 0 and data 1.

In the method for testing recovery from an erase interruption of a flash memory, in step S3, the set interval of "interrupting the erase operation and recovering the erase operation according to the set interval" includes an interruption interval for starting the interrupted erase operation and a recovery interval for delaying starting of recovering the erase operation after the interrupted erase operation.

In the method for testing recovery from flash erase interruption, in step S3, an interval threshold may be set, and when the sector performs the interval threshold times of the loop operation, it is detected and recorded whether the first data information in the non-operation area changes.

In the method for testing recovery from flash memory erasure interruption, in step S3, the sectors are one or more sectors randomly selected from the operation area.

In a second aspect, an embodiment of the present application further provides a FLASH memory erase interrupt recovery testing apparatus, configured to perform an interrupt recovery test on a NOR FLASH, where the apparatus includes:

the writing module is used for respectively writing first data information and second data information into a non-operation area and an operation area in the flash memory;

the selection module is used for selecting the sector in the operation area;

the cyclic operation module is used for circularly executing erasing-blank checking-programming-verifying operation on the sector selected by the selection module;

the interrupt recovery module can send out an interrupt erasing operation instruction and a recovery erasing operation instruction at intervals;

the detection module is used for detecting and recording whether the first data information of the non-operation area changes or not;

the interruption recovery module can send out an interruption erasing operation instruction and an erasing operation recovery instruction at intervals when the circulation module carries out erasing operation; the detection module may intermittently detect and record whether the first data information of the non-operation area changes during the loop operation of the loop operation module on the selected sector.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.

In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program runs the steps in the method provided in the first aspect when executed by a processor.

As can be seen from the above, the flash memory erasure interruption recovery test method, the flash memory erasure interruption recovery test device, the electronic device and the storage medium provided in the embodiments of the present application are provided, wherein the method performs a circular operation on a selected sector, and repeatedly performs interruption and recovery operations at an erasure stage in the circular operation, so that the flash memory chip performs a circular test for a plurality of times, and the interruption and recovery operations cover the entire erasure process, so that test data is representative, and the performance of the flash memory chip can be accurately and effectively reflected, and meanwhile, the change condition of the first data information of the non-operation area is intermittently detected, so that the influence of the accumulation of the erasure interruption and recovery operations on the data of the non-operation area can be effectively and clearly reflected; in addition, the bus clock frequency is set to be the limit frequency of the flash memory, so that the flash memory is in the state of most easily causing problems, and the chip performance can be tested more fully.

Drawings

Fig. 1 is a flowchart of a flash memory erase interruption recovery testing method according to an embodiment of the present disclosure.

Fig. 2 is a logic diagram of a flash memory erase interruption recovery test method according to embodiment 1 of the present application.

Fig. 3 is a schematic structural diagram of a flash memory erase interruption recovery testing apparatus according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

In a first aspect, please refer to fig. 1-2, fig. 1-2 are a FLASH memory erase interrupt recovery testing method in some embodiments of the present application, for performing an interrupt recovery test on a NOR FLASH, the method including the following steps:

s1, writing first data information into a non-operation area in the flash memory, and setting the bus clock frequency as the limit frequency of the flash memory;

the non-operation area refers to a memory cell area which does not need to be subjected to direct erase interruption recovery operation, and first data information is written into memory cells of the area so as to be used for verifying the influence of the erase interruption recovery operation on the non-operation area.

Specifically, the problem revealed during the flash memory chip test process can be more easily detected by setting the limit frequency.

S2, writing second data information into the operation area in the flash memory;

the operation area refers to a selectable memory cell area for performing erase interruption recovery operation, in actual operation, in order to reduce test time and not necessarily perform test operation of the whole operation area, part of the area is generally selected in the operation area to perform test operation so as to save test time and reduce the overall erase writing frequency in the test process of the flash memory chip, the area for selecting test operation generally takes a block or a sector as a test unit, but second data information is written into the whole operation area no matter which part of the operation area is subjected to test operation, and a next step starts to operate the test unit of the operation area from the erase step after the second data information is written;

s3, circularly executing the circular operation of erasing, checking null, programming and checking in sequence by the sector of the selected operation area, interrupting the erasing operation and recovering the erasing operation according to the set interval time in the erasing process, and detecting and recording whether the first data information of the non-operation area changes at intervals in the circular operation executing process of the sector;

specifically, in the embodiment of the present application, a sector (sector) is used as a test unit of an operation area, and after the sector is selected, the following operations are sequentially performed on the sector in each cycle operation: erasing all the data of the storage units in the sector to enable the data of all the storage units to be 1, performing blank checking on the data of the storage units, detecting the erasing condition of the storage units, then performing data programming on the storage units in the sector, and finally reading and verifying the data of the storage units.

Specifically, the programming data of the memory cells in the selected sector are the second data information, so that the data information of the memory cells in the sector at the beginning and the end of each cycle operation is ensured to be the same, and the stability of the data of the flash memory chip after undergoing the erase interruption recovery operation can be better reflected as the data reference.

Specifically, over-erase detection and repair are required after the erase operation is completed, so that the over-erase condition does not exist after the memory cell is erased.

More specifically, in each erasing operation in the cyclic operation, the erasing operation is interrupted and recovered according to the interval time, and the whole erasing operation process can be covered, namely, the erasing interruption can be ensured to cover all time slices of the erasing algorithm, so that the erasing interruption and recovery mode can effectively reflect the chip performance.

More specifically, after a certain number of loop operations are executed, whether the first data information of the non-operation area changes or not is detected and recorded, and the influence of the accumulated occurrence number of times of the erasing interruption and the recovery operation on the data of the non-operation area can be effectively and clearly reflected.

More specifically, whether the first data information of the non-operation area changes or not is detected and recorded, and meanwhile, the change condition of the first data information can be recorded, so that the influence of the erasure interruption and the accumulated occurrence number of the recovery operation on the data of the non-operation area can be reflected more clearly.

And S4, when the selected sector cycle execution operation reaches the set cycle number, ending the cycle.

Specifically, the cycle operation is set to have enough cycle times, so that the test method of the embodiment of the application is more representative, and the performance of the flash memory chip can be tested more accurately.

In some preferred embodiments, the number of cycles of the cyclic operation is 50 to 150K times, and in this embodiment, 100K times is preferred.

According to the flash memory erasure interruption recovery test method, the selected sector of the operation area is repeatedly erased, checked to be blank, programmed and checked in a circulating operation mode, multiple times of interruption and recovery operation are carried out in the erasing process, so that the flash memory chip circularly carries out multiple times of test, the interruption and recovery operation covers the whole erasing process, the test data is representative, the performance of the flash memory chip can be accurately and effectively reflected, meanwhile, the change condition of the first data information of the non-operation area is intermittently detected, and the influence of the erasure interruption and the accumulation of the recovery operation on the data of the non-operation area can be effectively and clearly reflected; in addition, the bus clock frequency is set to be the limit frequency of the flash memory, so that the flash memory is in the state of most easily causing problems, and the chip performance can be tested more fully.

In some preferred embodiments, the method further comprises the step performed before step S1 of:

and S0, testing the performance of the flash memory chip, and ensuring that the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.

Specifically, it is ensured through step S0 that the chip functions normally before the chip test, that is, the standby current, the deep sleep current, and the read/write speed of the flash memory chip are normal, so as to prepare for checking the influence of the frequent erase interruption recovery on the device after the test.

In the existing test method, only the functions of erasing interruption and recovery are generally verified, the influence of frequent erasing interruption and recovery on a Flash device is not tested after the test, and the circuit structure of the Flash determines that any operation related to high-voltage switching can influence the reliability of the device, so that a Flash memory chip can be damaged or destroyed after the test operation.

Therefore, in some preferred embodiments, the method further comprises the step performed after step S4 of:

s5, checking the performance of the flash memory chip, and analyzing whether the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.

Specifically, since step S0 is executed, it is known that the basic function of the tested flash memory chip is in a normal state before the test, and step S5 is used to know the performance variation of the tested flash memory chip, that is, whether the corresponding basic function is changed and the variation range.

More specifically, whether the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal or not is analyzed, and whether the flash memory chip has electric leakage or not in the test and whether the read-write speed is attenuated or not can be known.

In some preferred embodiments, the first data information includes data 0 and data 1.

Specifically, since the first data information includes data 0 and data 1, when step S3 detects whether the first data information changes, it may test whether the first data information has an erase disturbance and an over-erase (affected area data 0 changes to 1) or a program disturbance (affected area data 1 changes to 0), so that it may be more clearly tested whether the operation area of the flash memory chip has an influence on the non-operation area due to the erase interruption recovery operation.

More specifically, in the embodiment of the present application, the first data information is 5A data or checkerboard data, and the like, and these data each include data 0 and data 1.

More specifically, the second data information is a5 data, which is distinguishable from the first data information.

In some preferred embodiments, the set interval of "interrupt erase operation, resume erase operation at set interval" in step S3 includes an interrupt interval time for starting the interrupt erase operation and a resume interval time for delaying starting the resume erase operation after interrupting the erase operation.

Specifically, after the erasing operation of the storage unit is started, an erasing interruption instruction is sent to the flash memory chip after an interruption interval time to interrupt the erasing operation, then after the erasing interruption instruction is sent to delay the recovery interval time, a recovery erasing instruction is sent to the flash memory chip to continue the erasing operation, then after the interruption interval time, an erasing interruption instruction is sent to the flash memory chip to interrupt the erasing operation, and the erasing interruption and the recovery operation are continued in the same way until the erasing operation in the round of circulating operation is completed; the interruption interval time and the recovery interval time are set to continuously carry out the erasing interruption and recovery operation, so that the erasing interruption and recovery operation covers the whole erasing process, the influence of the interruption and recovery operation on the data of the flash memory chip at different stages of the erasing operation can be more effectively and comprehensively reflected, and the data retention capacity of the flash memory chip is reflected.

In some preferred embodiments, an interval threshold may be set in step S3, and when the sector performs the loop operation for each interval threshold number of times, it is detected and recorded whether the first data information of the non-operation area changes.

Specifically, the influence of different stages in the cyclic operation cycle process on the non-operation area can be orderly and clearly reflected by setting the interval threshold value to detect the change of the first data information.

In some preferred embodiments, the interval threshold is generally 1/500-1/50, preferably 1/100 in this embodiment, and is 1000 if the number of the loop operations is 100K.

In some preferred embodiments, the sector in step S3 is one or more sectors randomly selected from the operation area.

Specifically, the sector selection adopts a random selection mode to ensure that the test unit has randomness, and the randomly selected sector can more effectively reflect the performance of the flash memory chip.

According to the flash memory erasing interruption recovery testing method provided by the embodiment of the application, the selected sector is subjected to the circulating operation, and the interruption and recovery operation are repeatedly performed at the erasing stage in the circulating operation, so that the flash memory chip is circularly tested for multiple times, and the interruption and recovery operation covers the whole erasing process, the test data is representative, the performance of the flash memory chip can be accurately and effectively reflected, meanwhile, the change condition of the first data information of the non-operation area is intermittently detected, and the influence of the erasing interruption and the recovery operation accumulation on the data of the non-operation area can be effectively and clearly reflected.

Example 1

Referring to fig. 2, before testing, an Automatic Test Equipment (ATE) is used to test the standby current, deep sleep current, and read/write speed of the chip, so as to ensure that the chip before testing is normal in basic function, and to prepare for checking the influence of frequent erase interruption recovery on the device after testing.

Writing 5A data into a non-operation area in the whole flash memory chip; and setting the bus clock frequency as the limit frequency of Flash (the test board card adopts equal-length wiring to ensure the maximum frequency of the frequency to be run).

Writing A5 data into an operating area of a flash memory chip, randomly selecting a sector (sector) in the operating area, and performing 'erasing-checking null-programming-verifying' cyclic operation on the sector for 100K times; during the erasing process, an erasing interruption command is sent every tSUS (such as 40us) to interrupt the erasing operation, then tRS (such as 30us) is delayed to resume the erasing operation, and the process is repeated until the polling status register checks that the erasing operation of the current round is completed, and the process can ensure that the erasing interruption can cover all time slices of the erasing algorithm.

In the test process, the data of the non-operation area is checked every 1000 times of circulating operation, and whether the non-operation area is influenced by over erasure or erasure disturbance of the operation area is checked; since the non-operation area of the test flow writes 5A data, including data 0 and data 1, the test process can test both erase disturbance and over-erase (affected area data 0 changes to 1) and program disturbance (affected area data 1 changes to 0).

After the test is finished, the Automatic Test Equipment (ATE) is used again to check the standby current, the deep sleep current and the chip read-write speed of the chip, and whether the chip has electric leakage and whether the read-write speed is attenuated or not is checked.

In a second aspect, please refer to fig. 3, fig. 3 is a FLASH memory erase interrupt recovery testing apparatus for performing an interrupt recovery test on a NOR FLASH memory according to some embodiments of the present application, including:

the writing module is used for respectively writing first data information and second data information into a non-operation area and an operation area in the flash memory;

the selection module is used for selecting the sector in the operation area;

the cyclic operation module is used for circularly executing erasing-blank checking-programming-verifying operation on the sector selected by the selection module;

the interrupt recovery module can send out an interrupt erasing operation instruction and a recovery erasing operation instruction at intervals;

the detection module is used for detecting and recording whether the first data information of the non-operation area changes or not;

the interruption recovery module can send out an interruption erasing operation instruction and a recovery erasing operation instruction at intervals when the circulation module carries out erasing operation; the detection module may intermittently detect and record whether the first data information of the non-operation area is changed during the loop operation of the loop operation module on the selected sector.

According to the testing device for the flash memory erasing interruption recovery, the first data information and the second data information are respectively written into the non-operation area and the operation area of the flash memory chip to be tested through the writing module, then the sector in the operation area is selected through the selection module, and the erasing-blank checking-programming-checking operation is executed by the sector of the circulation operation module in a circulation mode, wherein in the erasing process, the interruption recovery module sends an interruption erasing operation instruction and an erasure recovery operation instruction to the circulation module at intervals, so that the whole erasing operation process is interrupted and recovered at intervals in the whole erasing operation process, the selected area of the flash memory chip is tested for multiple times in a circulation mode, the interruption and recovery operation covers the whole erasing process, the test data is representative, the performance of the flash memory chip can be accurately and effectively reflected, and meanwhile, the first data information of the non-operation area is detected at intervals in the circulation operation process through the detection module The influence of the occurrence of the erasure interruption and the accumulation of the recovery operation on the data of the non-operation area can be effectively and clearly reflected by the change situation.

In some preferred embodiments, the flash memory chip further comprises a performance testing module, and the performance testing module is used for detecting the performance of the flash memory chip before and after testing.

Specifically, the performance test module can detect the standby current, the deep sleep current and the read-write speed of the flash memory chip.

More specifically, the performance test module detects the performance of the chip before starting the test, ensures that the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal, and prepares for checking the influence of frequent erasing interruption recovery on the device after the test.

More specifically, the performance testing module detects the performance of the chip after the test is finished, and can acquire the change condition of the performance of the flash memory chip after the test, namely whether the corresponding basic function changes and the change amplitude, so as to acquire whether the flash memory chip has the problems of electric leakage during the test and whether the read-write speed has attenuation.

In a third aspect, referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.

In a fourth aspect, the present application provides a storage medium, and when being executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.