1. A semiconductor device, comprising:

a selection input circuit configured to generate selection data, a selection parity check bit, and a selection data control signal from data, a parity check bit, and a data control signal during a write operation, and configured to set the selection data, the selection parity check bit, and the selection data control signal to a predetermined logic level during a mode write operation; and

a core data generation circuit configured to receive the drive data, the drive parity bit, and the drive data control signal driven by the selection data, the selection parity bit, and the selection data control signal to generate core data stored into the memory core according to whether an error correction operation and a data inversion operation are performed.

2. The semiconductor device of claim 1, wherein the selection input circuit is configured to receive a write command signal during the write operation and to receive a first mode control flag and a second mode control flag during the mode write operation.

3. The semiconductor device according to claim 2, further comprising a command decoder configured to generate the write command signal, the first mode control flag, and the second mode control flag by decoding a control signal.

4. The semiconductor device of claim 2, further comprising a command decoder configured to generate the first mode control flag to set the selection data to a first logic level and to generate the second mode control flag to set the selection data to a second logic level.

5. The semiconductor device as set forth in claim 1,

wherein the selection parity bit is generated from the parity bit when the write operation is performed, the parity bit being set according to an error check matrix used in the error correction operation; and

wherein the select parity bit is set to have the predetermined logic level to prevent an influence on the error correction operation when the mode write operation is performed.

6. The semiconductor device as set forth in claim 1,

wherein the selection data control signal is generated from the data control signal for controlling the data inversion operation and the data masking operation when the write operation is performed; and

wherein the select data control signal is set to have the predetermined logic level to block an influence on the data inversion operation and the data masking operation when the mode write operation is performed.

7. The semiconductor device as set forth in claim 1,

wherein the core data generation circuit is configured to output the driving data as first internal data when the error correction operation is not performed; and

wherein the core data generation circuit is configured to output correction data generated by correcting an error included in the drive data as the first internal data when the error correction operation is performed.

8. The semiconductor device as set forth in claim 7,

wherein the core data generation circuit is configured to output the first internal data as second internal data when the data inversion operation is not performed;

wherein the core data generation circuit is configured to, when the data inversion operation is performed, invert-buffer the first internal data to output inverted-buffered data of the first internal data as the second internal data; and

wherein the core data generation circuit is configured to drive the core data based on the second internal data.

9. The semiconductor device according to claim 1, further comprising a data mask control circuit configured to generate a data mask signal for controlling a data mask operation according to whether the data inversion operation is performed.

10. The semiconductor device as set forth in claim 9,

wherein the data masking control circuit is configured to generate the data masking signal from the driving data control signal when the data inversion operation is not performed; and

wherein the data masking control circuit is configured to generate the data masking signal to prevent the data masking operation from being performed when the data inversion operation is performed.

11. The semiconductor device as set forth in claim 1,

wherein the selection data comprises first selection data and second selection data; and

wherein logic levels of the first selection data and the second selection data are set according to a burst length.

12. A semiconductor device, comprising:

a selection data generation circuit configured to generate selection data from data during a write operation and configured to set the selection data based on a mode control flag during a mode write operation;

a select parity bit generation circuit configured to generate a select parity bit from parity bits during the write operation and configured to set the select parity bit to a first logic level during the mode write operation;

a select flag generation circuit configured to generate a select data control signal from a data control signal during the write operation and configured to set the select data control signal to a second logic level during the mode write operation; and

a core data generation circuit configured to receive the drive data, the drive parity bit, and the drive data control signal driven by the selection data, the selection parity bit, and the selection data control signal to generate core data stored into the memory core according to whether an error correction operation and a data inversion operation are performed.

13. The semiconductor device as set forth in claim 12,

wherein the mode control flag comprises a first mode control flag and a second mode control flag; and

wherein a logic level of the selection data is set based on the first mode control flag and the second mode control flag.

14. The semiconductor device as set forth in claim 12,

wherein the selection parity bit is generated from a parity bit set according to an error check matrix used in the error correction operation when the write operation is performed; and

wherein the select parity bit is set to have the first logic level to prevent an impact on the error correction operation when the mode write operation is performed.

15. The semiconductor device as set forth in claim 12,

wherein the select data control signal is generated from the data control signal for controlling the data inversion operation and the data masking operation when the write operation is performed; and

wherein the select data control signal is set to have the second logic level to block an influence on the data inversion operation and the data masking operation when the mode write operation is performed.

16. The semiconductor device as set forth in claim 12,

wherein the core data generation circuit is configured to output the driving data as first internal data when the error correction operation is not performed; and

wherein the core data generation circuit is configured to output correction data generated by correcting an error included in the drive data as the first internal data when the error correction operation is performed.

17. The semiconductor device as set forth in claim 16,

wherein the core data generation circuit is configured to output the first internal data as second internal data when the data inversion operation is not performed;

wherein the core data generation circuit is configured to, when the data inversion operation is performed, invert-buffer the first internal data to output inverted-buffered data of the first internal data as the second internal data; and

wherein the core data generation circuit is configured to drive the core data based on the second internal data.

18. The semiconductor device according to claim 12, further comprising a data mask control circuit configured to generate a data mask signal for controlling a data mask operation according to whether the data inversion operation is performed.

19. The semiconductor device as set forth in claim 18,

wherein the data masking control circuit is configured to generate the data masking signal from the driving data control signal when the data inversion operation is not performed; and

wherein the data masking control circuit is configured to generate the data masking signal to prevent the data masking operation from being performed when the data inversion operation is performed.

20. The semiconductor device as set forth in claim 12,

wherein the selection data comprises first selection data and second selection data; and

wherein logic levels of the first selection data and the second selection data are set according to a burst length.

Background

A semiconductor device such as a Dynamic Random Access Memory (DRAM) device performs a write operation and a read operation. A write operation is performed to store data to a bank (bank) including a cell array accessed using an address, and a read operation is performed to output data stored in the cell array included in the bank.

Disclosure of Invention

According to one embodiment, a semiconductor device includes a selection input circuit and a core data generation circuit. The select input circuit is configured to generate select data, select parity bits, and select data control signals from the data, parity bits, and data control signals during a write operation. Further, the selection input circuit is configured to set the selection data, the selection parity bit, and the selection data control signal to predetermined logic levels during the mode write operation. The core data generation circuit is configured to receive the drive data, the drive parity bit, and the drive data control signal driven by the select data, the select parity bit, and the select data control signal to generate core data stored into the memory core according to whether an error correction operation and a data inversion operation are performed.

According to another embodiment, a semiconductor device includes a selection data generation circuit, a selection parity bit generation circuit, a selection flag generation circuit, and a core data generation circuit. The selection data generation circuit is configured to generate selection data from the data during a write operation and configured to set the selection data based on the mode control flag during a mode write operation. The select parity bit generation circuit is configured to generate a select parity bit from the parity bits during a write operation and is configured to set the select parity bit to a first logic level during a mode write operation. The select flag generation circuit is configured to generate a select data control signal from the data control signal during a write operation and is configured to set the select data control signal to a second logic level during a mode write operation. The core data generation circuit is configured to receive the drive data, the drive parity bit, and the drive data control signal driven by the select data, the select parity bit, and the select data control signal to generate core data stored into the memory core according to whether an error correction operation and a data inversion operation are performed.

Drawings

Fig. 1 is a block diagram illustrating a configuration of a semiconductor system according to one embodiment of the present disclosure.

Fig. 2 is a block diagram illustrating a configuration of a semiconductor device included in the semiconductor system illustrated in fig. 1.

Fig. 3 is a table showing conditions for generating a mode write command, a first mode control flag, and a second mode control flag for a mode write operation.

Fig. 4 shows a configuration of a write operation circuit included in the semiconductor device shown in fig. 2.

Fig. 5 is a table showing the configuration of an error check matrix for generating a syndrome (syndrome) in the syndrome generating circuit included in the write operation circuit shown in fig. 4.

Fig. 6 is a block diagram illustrating a configuration of a semiconductor device included in the semiconductor system illustrated in fig. 1.

Fig. 7 shows a configuration of a write operation circuit included in the semiconductor device shown in fig. 6.

Fig. 8 is a table showing logic level combinations of data input to the write operation circuit shown in fig. 7.

Detailed Description

In the description of the embodiments below, when a parameter is referred to as being "predetermined," it is intended to mean that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The parameter values may be set at the beginning of a process or algorithm or may be set during a period of time during which the process or algorithm is executed.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and do not suggest an order or numbering of the elements. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present disclosure.

In addition, it will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Logic "high" levels and logic "low" levels may be used to describe the logic levels of an electrical signal. A signal having a logic "high" level may be distinguished from a signal having a logic "low" level. For example, when a signal having a first voltage corresponds to a signal having a logic "high" level, a signal having a second voltage corresponds to a signal having a logic "low" level. In one embodiment, the logic "high" level may be set to a voltage level higher than the voltage level of the logic "low" level. In addition, the logic levels of the signals may be set differently or otherwise according to different implementations. For example, a particular signal having a logic "high" level in one embodiment may be set to have a logic "low" level in another embodiment.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

Fig. 1 is a block diagram illustrating a configuration of a semiconductor system 100 according to one embodiment of the present disclosure. As shown in fig. 1, the semiconductor system 100 may include a host 110, a controller 130, and a semiconductor device 150.

The host 110 may manage and control the overall function and operation of the host 110 using an Operating System (OS), and may control interaction between the controller 130 and the semiconductor device 150. Operating systems can be divided into general-purpose operating systems and mobile operating systems. Common operating systems can be divided into personal operating systems and enterprise operating systems. The personal operating system is a system dedicated to support service providing functions for general users and may include Windows and Chrome. Enterprise operating systems are systems dedicated to guaranteeing and supporting high performance and may include Windows servers, Linux, Unix, and the like. The mobile operating system is a system dedicated to support a mobile service providing function for a user and a power saving function of the system and may include Android, iOS, Windows mobile, and the like. The host 110 may run an operating system to control operations between the controller 130 and the semiconductor device 150 according to a user request.

The controller 130 may include a host interface unit 171, a processor 173, an Error Correction Code (ECC) unit 175, and a memory interface unit 177.

The host interface unit 171 may process commands and data output from the host 110 and may be set to communicate with the host 110 using at least one of various interface protocols such as: universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-E), serial attached SCSI (sas), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), and Mobile Industrial Processor Interface (MIPI).

The processor 173 may control the overall operation of the controller 130 for controlling the semiconductor device 150 according to a request of the host 110. For example, when a write request or a read request is output from the host 110, the processor 173 may control a write operation or a read operation with respect to the semiconductor device 150. The processor 173 may be implemented using a microprocessor or a Central Processing Unit (CPU).

The ECC unit 175 may correct an erroneous bit of data processed by the semiconductor device 150 and may include an ECC encoder and an ECC decoder. The ECC encoder may generate the parity bits PRT by performing an error correction encoding operation on the data DQ applied to the semiconductor device 150. The ECC decoder may detect and correct errors of the data DQ received from the semiconductor device 150. The ECC unit 175 may correct errors using coding modulation such as Low Density Parity Check (LDPC) code, Bose-Chaudhri-hocquenghem (bch) code, turbo code, Reed-Solomon code, convolutional code, Recursive Systematic Code (RSC), Trellis Coded Modulation (TCM), or Block Coded Modulation (BCM) according to an embodiment, but is not limited thereto.

In order for the controller 130 to control the semiconductor device 150 in response to a request of the host 110, the memory interface unit 177 may apply a control signal CA, a chip select signal CS, a clock signal CLK, data DQ, parity bits PRT, and a data control signal DMI to the semiconductor device 150 and may receive data DQ from the semiconductor device 150.

The semiconductor device 150 may receive a control signal CA, a chip select signal CS, a clock signal CLK, data DQ, a parity bit PRT, and a data control signal DMI to perform an error correction operation, a write operation including a data masking operation and a data inversion operation, and a mode write operation.

Fig. 2 is a block diagram showing a configuration of a semiconductor device 150a corresponding to the semiconductor device 150 shown in fig. 1. As shown in fig. 2, the semiconductor device 150a may include a command decoder 210 and a write operation circuit 230.

The command decoder 210 may generate the write command signal WT, the mode write command signal WRX, the first mode control flag WXSA, and the second mode control flag WXSB based on the control signal CA, the chip select signal CS, and the clock signal CLK. The command decoder 210 may selectively generate one of the write command signal WT, the mode write command signal WRX, the first mode control flag WXSA, and the second mode control flag WXSB according to a logic level combination of bits included in the control signal CA input to the command decoder 210 based on the chip selection signal CS and the clock signal CLK. The write command signal WT may be generated to perform a write operation for storing core data (CDQ of fig. 4) generated based on the data DQ into a memory core (39 of fig. 4). The mode write command signal WRX may be generated to perform a mode write operation for storing core data CDQ having a predetermined logic level into the memory core 39 regardless of the data DQ. The first mode control flag WXSA may be generated to store core data CDQ having a first logic level into the memory core 39 during a mode write operation. The second mode control flag WXSB may be generated to store the core data CDQ having the second logic level into the memory core 39 during the mode write operation. In this embodiment, the first logic level may be set to a logic "low" level, and the second logic level may be set to a logic "high" level. However, the present disclosure is not limited thereto. The logic level combinations of the bits included in the control signal CA for generating the write command signal WT, the mode write command signal WRX, the first mode control flag WXSA, and the second mode control flag WXSB may be set to be different according to the embodiment.

The write operation circuit 230 may receive the data DQ, the parity bit PRT, the data control signal DMI, the power supply voltage VDD, and the ground voltage VSS to perform an error correction operation, a write operation including a data masking operation and a data inversion operation, and a mode write operation based on the write command signal WT, the mode write command signal WRX, the first mode control flag WXSA, and the second mode control flag WXSB. When the write command signal WT is generated to perform a write operation, the write operation circuit 230 may store core data CDQ generated based on the data DQ into the memory core 39. When the mode write command signal WRX is generated to perform the mode write operation, the write operation circuit 230 may store the core data CDQ having the logic level set by the first and second mode control flags WXSA and WXSB into the memory core 39.

Fig. 3 is a table showing conditions for generating the pattern write command signal WRX, the first pattern control flag WXSA, and the second pattern control flag WXSB for the pattern write operation. As shown in fig. 3, in the case where the chip select signal CS is set to "H" (hereinafter, logic "high" level), the first and second bits CA <1:2> of the control signal CA are set to "L" (hereinafter, logic "low" level) in synchronization with the rising edge of the clock signal CLK, and the third and fourth bits CA <3:4> of the control signal CA are set to logic "high" level in synchronization with the rising edge of the clock signal CLK, the mode write command signal WRX may be generated from the fifth bit CA <5> of the control signal CA in synchronization with the falling edge of the clock signal CLK. In a case where the chip selection signal CS is set to have a logic "high" level, the first and second bits CA <1:2> of the control signal CA are set to have a logic "low" level in synchronization with the rising edge of the clock signal CLK, and the third and fourth bits CA <3:4> of the control signal CA are set to have a logic "high" level in synchronization with the rising edge of the clock signal CLK, the first mode control flag WXSA may be generated from the sixth bit CA <6> of the control signal CA in synchronization with the falling edge of the clock signal CLK. In a case where the chip selection signal CS is set to have a logic "high" level, the first and second bits CA <1:2> of the control signal CA are set to have a logic "low" level in synchronization with the rising edge of the clock signal CLK, and the third and fourth bits CA <3:4> of the control signal CA are set to have a logic "high" level in synchronization with the rising edge of the clock signal CLK, the second mode control flag WXSB may be generated from the seventh bit CA <7> of the control signal CA in synchronization with the falling edge of the clock signal CLK.

Fig. 4 shows a configuration of the write operation circuit 230 according to an embodiment. As shown in fig. 4, the write operation circuit 230 may include a selection input circuit 31, an input drive circuit 33, a core data generation circuit 35, a data mask control circuit 37, and a memory core 39.

During a write operation, the selection input circuit 31 may generate selection data SDQ from the data DQ, may generate selection parity bits SPRT from the parity bits PRT, and may generate a selection data control signal SDMI from the data control signal DMI. The selection input circuit 31 may set the selection data SDQ to the power supply voltage VDD or the ground voltage VSS during the mode write operation. During the mode write operation, the selection input circuit 31 may set the selection parity bit SPRT and the selection data control signal SDMI to the ground voltage VSS. The selection input circuit 31 may include a selection data generation circuit 311, a selection parity bit generation circuit 313, and a selection flag generation circuit 315.

The selection data generation circuit 311 may generate the selection data SDQ based on the data DQ, the power supply voltage VDD, the ground voltage VSS, the write command signal WT, the first mode control flag WXSA, and the second mode control flag WXSB. When a write operation is performed based on the write command signal WT, the selection data generation circuit 311 may output the data DQ as the selection data SDQ. When the first mode control flag WXSA is generated during the mode write operation, the selection data generation circuit 311 may output the ground voltage VSS as the selection data SDQ. When the second mode control flag WXSB is generated during the mode write operation, the selection data generation circuit 311 may output the power supply voltage VDD as the selection data SDQ.

The selection parity bit generation circuit 313 may generate the selection parity bit SPRT based on the parity bit PRT, the ground voltage VSS, the write command signal WT, the first mode control flag WXSA, and the second mode control flag WXSB. When the write command signal WT is generated to perform a write operation, the selection parity bit generation circuit 313 may output the parity bit PRT as the selection parity bit SPRT. When the first mode control flag WXSA or the second mode control flag WXSB is generated during the mode write operation, the selection parity generation circuit 313 may output the ground voltage VSS as the selection parity bit SPRT. In the present embodiment, the selection parity bit SPRT may be driven to the ground voltage VSS to prevent the error correction operation from being performed during the mode write operation, but according to an embodiment, the selection parity bit SPRT may also be driven to a logic level different from that of the ground voltage VSS.

The selection flag generation circuit 315 may generate the selection data control signal SDMI based on the data control signal DMI, the ground voltage VSS, the write command signal WT, the first mode control flag WXSA, and the second mode control flag WXSB. When the write command signal WT is generated to perform a write operation, the selection flag generation circuit 315 may output the data control signal DMI as the selection data control signal SDMI. When the first mode control flag WXSA or the second mode control flag WXSB is generated during the mode write operation, the selection flag generation circuit 315 may output the ground voltage VSS as the selection data control signal SDMI. In the present embodiment, the selection data control signal SDMI may be driven to the ground voltage VSS to prevent the data inversion operation and the data masking operation from being performed during the mode write operation, but the selection data control signal SDMI may also be driven to a logic level different from that of the ground voltage VSS according to an embodiment.

When a write operation or a mode write operation is performed, the input drive circuit 33 may generate the drive data DQ _ DRV, the drive parity PRT _ DRV, and the drive data control signal DMI based on the selection data SDQ, the selection parity SPRT, and the selection data control signal SDMI. The input driving circuit 33 may include a first input driver 331, a second input driver 333, and a third input driver 335.

The first input driver 331 may generate the driving data DQ _ DRV based on the data input pulse DINP and the selection data SDQ. When a write operation or a pattern write operation is performed, the data input pulse DINP may be generated. The data input pulse DINP may be generated at a time point after a predetermined input delay period has elapsed from a time point at which the write command signal WT or the pattern write command signal WRX is generated. The predetermined input delay period may be set to be different according to embodiments. When a write operation or a pattern write operation is performed to generate the data input pulse DINP, the first input driver 331 may drive the driving data DQ _ DRV to the same logic level as the selection data SDQ.

The second input driver 333 may generate the driving parity bit PRT _ DRV based on the data input pulse DINP and the selection parity bit SPRT. When a write operation or a mode write operation is performed to generate the data input pulse DINP, the second input driver 333 may drive the driving parity bits PRT _ DRV to the same logic level as the selection parity bits SPRT.

The third input driver 335 may generate the driving data control signal DMI _ DRV based on the data input pulse DINP and the selection data control signal SDMI. When a write operation or a mode write operation is performed to generate the data input pulse DINP, the third input driver 335 may drive the driving data control signal DMI _ DRV to the same logic level as the selection data control signal SDMI.

The core data generation circuit 35 may generate the core data CDQ based on the drive data DQ _ DRV, the drive parity PRT _ DRV, the error correction activation signal ECCEN, the drive data control signal DMI _ DRV, and the write input pulse win. The error correction enable signal ECCEN may be generated to have a logic "high" level when the error correction operation is performed. The core data generation circuit 35 may generate the first internal data IDQ1 from the drive data DQ _ DRV when the error correction operation is not performed, and may generate the first internal data IDQ1 from the correction data CD generated by correcting an error included in the drive data DQ _ DRV when the error correction operation is performed. The core data generation circuit 35 may generate the second internal data IDQ2 from the first internal data IDQ1 when the data inversion operation is not performed, and may generate the second internal data IDQ2 by inverting-buffering the first internal data IDQ1 when the data inversion operation is performed. The write input pulse win may be generated at a time point after a predetermined write input delay period has elapsed from a time point at which the write command signal WT or the pattern write command signal WRX is generated. For some embodiments, the predetermined write input delay period is set to be longer than the predetermined input delay period. When the write input pulse win is generated, the core data generation circuit 35 may drive the core data CDQ based on the second internal data IDQ 2.

The core data generation circuit 35 may include a syndrome generation circuit 351, an error correction circuit 353, a first internal data selection circuit 355, an inverter IV31, a second internal data generation circuit 357, and a first core driver 359 electrically connected in this order. The syndrome generation circuit 351 may generate the syndrome SYN based on the driving data DQ _ DRV and the driving parity PRT _ DRV. The syndrome generation circuit 351 may generate the syndrome SYN by performing a logical arithmetic operation on bits selected from bits included in the drive data DQ _ DRV and the drive parity PRT _ DRV according to an error check matrix used in the error correction code ECC. The syndrome SYN may include information on at least one error bit among bits included in the driving data DQ _ DRV. The error correction circuit 353 may generate the correction data CD by correcting at least one erroneous bit among the bits included in the drive data DQ _ DRV based on the syndrome SYN. The first internal data selection circuit 355 may output the driving data DQ _ DRV or the correction data CD as the first internal data IDQ1 based on the error correction enable signal ECCEN. When the error correction enable signal ECCEN is not generated because an error correction operation is not performed, the first internal data selection circuit 355 may output the driving data DQ _ DRV as the first internal data IDQ 1. When the error correction operation is performed to generate the error correction enable signal ECCEN, the first internal data selection circuit 355 may output the correction data CD as the first internal data IDQ 1. The inverter IV31 may invert the buffered first internal data IDQ1 to output the inverted buffered data of the first internal data IDQ 1. The second internal data generation circuit 357 may output the output signal of the inverter IV31 or the first internal data IDQ1 as the second internal data IDQ2 based on the driving data control signal DMI _ DRV. When the data inversion operation is performed, the second internal data generation circuit 357 may output the output signal of the inverter IV31 as the second internal data IDQ2 based on the driving data control signal DMI _ DRV. When the data inversion operation is not performed, the second internal data generation circuit 357 may output the first internal data IDQ1 as the second internal data IDQ2 based on the driving data control signal DMI _ DRV. The first core driver 359 may generate the core data CDQ based on the write input pulse win and the second internal data IDQ 2. When a write operation or a pattern write operation is performed to generate the write input pulse win, the first core driver 359 may drive the core data CDQ to have the same logic level as the second internal data IDQ 2.

The data masking control circuit 37 may generate the data masking signal CDM based on the driving data control signal DMI _ DRV, the data inversion activation signal DBI _ EN, and the write input pulse win. When the data inversion operation is performed, the data inversion activation signal DBI _ EN may be generated to have a logic "high" level. Whether the data inversion operation is performed may be determined according to a logic level of a bit included in the data DQ. For example, when the number of bits having a logic "high" level among the bits included in the data DQ is larger than the number of bits having a logic "low" level among the bits included in the data DQ, the data inversion operation may be set to be performed. When the data inversion operation is performed, the data mask control circuit 37 may transfer the driving data control signal DMI _ DRV to the core data generation circuit 35, so that the second internal data IDQ2 is generated from the inverted buffer data of the first internal data IDQ 1. When the data inversion operation is performed, the data mask control circuit 37 may set the internal data mask signal IDM to the ground voltage VSS to prevent the data mask operation from being performed. When the data inversion operation is not performed, the data mask control circuit 37 may transmit the driving data control signal DMI _ DRV as the internal data mask signal IDM. When the write input pulse win is generated, the data mask control circuit 37 may generate the data mask signal CDM from the internal data mask signal IDM.

The data mask control circuit 37 may include a data mask selection circuit 371 and a second core driver 373. The data mask selection circuit 371 may output the driving data control signal DMI _ DRV or the ground voltage VSS as the internal data mask signal IDM based on the data inversion activation signal DBI _ EN. When the data inversion activation signal DBI _ EN has a logic "low" level due to the data inversion operation not being performed, the data mask selection circuit 371 may output the driving data control signal DMI _ DRV as the internal data mask signal IDM. When the data inversion activation signal DBI _ EN has a logic "high" level due to the data inversion operation being performed, the data mask selection circuit 371 may output the ground voltage VSS as the internal data mask signal IDM. When a write operation or a pattern write operation is performed to generate the write input pulse win, the second core driver 373 may drive the data masking signal CDM to have the same logic level as the internal data masking signal IDM.

The memory core 39 may include a plurality of memory cell arrays (not shown) storing core data CDQ based on the data mask signal CDM. When the masking operation is performed during the write operation, the memory core 39 may block bits selected according to the data masking signal CDM among bits included in the storage core data CDQ.

Fig. 5 is a table showing an error check matrix for generating the syndrome SYN in the syndrome generating circuit 351. Referring to fig. 5, the first through ninth bits S1 through S9 of the syndrome SYN are generated by the first through eighth bits DQ <1:8> of the data DQ and the first through ninth bits C1 through C2 of the check bit (check bit) for each Burst Length (BL). In the present embodiment, the first to eighth bits DQ <1:8> may correspond to data DQ input to respective ones of the first to eighth data pins (not shown), the first to ninth bits C1 to C9 included in the syndrome bits may correspond to first to ninth bits PRT <1:9> of the parity bits PRT, and the syndrome generated by the syndrome generation circuit 351 may include first to ninth bits S1 to S9. For example, when the burst length is 2(BL ═ 2 "), the third bit S3 of the syndrome may be generated by performing an exclusive-or operation on the fifth bit DQ <5> of the data, the sixth bit DQ <6> of the data, the seventh bit DQ <7> of the data, the eighth bit DQ <8> of the data, and the third bit C3 of the check bit. For each burst length, an error bit among the first through eighth bits DQ <1:8> of the data may be confirmed through the first through eighth bits S1 through S8 of the syndrome generated by the syndrome generation circuit 351. For example, if the first bit S1 to the eighth bit S8 of the syndrome have data of "11011011000" when the burst length BL is "1", it means that the fourth bit DQ <4> of the data has an error. When the first through eighth bits S1 through S8 of the syndrome all have a logic "low" level, it means that there is no error in the first through eighth bits DQ <1:8> of the data. When the ninth bit S9 of the syndrome has a logic "low" level, it means that two bits among the first to eighth bits DQ <1:8> of the data are error bits.

The semiconductor device 150a having the foregoing configuration can set the selection data SDQ to the power supply voltage VDD or the ground voltage VSS to use the syndrome generating circuit 351 and the error correcting circuit 353 which are set to perform the error correcting operation without any design change of the syndrome generating circuit 351 and the error correcting circuit 353 even for the mode writing operation. Therefore, the layout area and power consumption of the semiconductor device 150a can be reduced. Further, the semiconductor device 150a may set the selection parity bit SPRT and the selection data control signal SDMI to the ground voltage VSS to use the second internal data generation circuit 357 set to perform the data inversion operation and the data mask selection circuit 371 set to perform the data mask operation, without any design change of the second internal data generation circuit 357 and the data mask selection circuit 371 even for the mode write operation. Therefore, the layout area and power consumption of the semiconductor device 150a can also be reduced.

Fig. 6 is a block diagram showing a configuration of a semiconductor device 150b corresponding to the semiconductor device 150 shown in fig. 1. As shown in fig. 6, the semiconductor device 150b may include a command decoder 410 and a write operation circuit 430.

The command decoder 410 may generate the write command signal WT, the mode write command signal WRX, the first mode control flag WXSA, and the second mode control flag WXSB based on the control signal CA, the chip select signal CS, and the clock signal CLK. The command decoder 410 may selectively generate one of the write command signal WT, the mode write command signal WRX, the first mode control flag WXSA, and the second mode control flag WXSB according to a logic level combination of a chip select signal CS and a logic level of a bit included in a control signal CA input in synchronization with the clock signal CLK. The write command signal WT may be generated to perform a write operation for storing core data (CDQ of fig. 7) generated based on the data DQ into the memory core (59 of fig. 7). The mode write command signal WRX may be generated to perform a mode write operation for storing core data CDQ having a predetermined logic level into the memory core 59 regardless of the data DQ. The first mode control flag WXSA may be generated to store core data CDQ having a first logic level into the memory core 59 during a mode write operation. The second mode control flag WXSB may be generated to store the core data CDQ having the second logic level into the memory core 59 during the mode write operation. In the present embodiment, the first logic level may be set to a logic "low" level and the second logic level may be set to a logic "high" level, but the present disclosure is not limited thereto. The logic level combinations of the bits included in the control signal CA for generating the write command signal WT, the mode write command signal WRX, the first mode control flag WXSA, and the second mode control flag WXSB may be set to be different according to the embodiment.

The write operation circuit 430 may receive the data DQ, the parity bit PRT, the data control signal DMI, the power supply voltage VDD, and the ground voltage VSS to perform an error correction operation, a write operation including a data masking operation and a data inversion operation, and a mode write operation based on the write command signal WT, the mode write command signal WRX, the first mode control flag WXSA, the second mode control flag WXSB, and the burst control flag BLEOF. When the write command signal WT is generated to perform a write operation, the write operation circuit 430 may store core data CDQ generated from data DQ input based on the burst control flag BLEOF into the memory core 59. The burst control flag BLEOF may be set to have a first logic level when the burst length BL is odd, and may be set to have a second logic level when the burst length BL is even. When the mode write command signal WRX is generated to perform the mode write operation, the write operation circuit 430 may store the core data CDQ having the logic level set by the first and second mode control flags WXSA and WXSB into the memory core 59.

Fig. 7 shows a configuration of the write operation circuit 430. As shown in fig. 7, the write operation circuit 430 may include a selection input circuit 51, an input drive circuit 53, a core data generation circuit 55, a data mask control circuit 57, and a memory core 59.

During a write operation, the selection input circuit 51 may generate first selection data SDQ1 and second selection data SDQ2 from the data DQ, may generate selection parity bits SPRT from the parity bits PRT, and may generate a selection data control signal SDMI from the data control signal DMI. The selection input circuit 51 may set the first selection data SDQ1 and the second selection data SDQ2 to the power supply voltage VDD or the ground voltage VSS during the mode write operation. The selection input circuit 51 may set the selection parity bit SPRT and the selection data control signal SDMI to the ground voltage VSS during the mode write operation. The selection input circuit 51 may include a first selection data generation circuit 511, a second selection data generation circuit 513, a selection parity bit generation circuit 515, and a selection flag generation circuit 517.

The first selection data generation circuit 511 may generate the first selection data SDQ1 based on the data DQ, the power supply voltage VDD, the ground voltage VSS, the write command signal WT, the first mode control flag WXSA, the second mode control flag WXSB, and the burst control flag BLEOF. When the write operation is performed in a case where the burst control flag BLEOF has the first logic level and the write command signal WT is generated such that the burst length BL has an odd number, the first selection data generation circuit 511 may output the data DQ as the first selection data SDQ 1. When the first mode control flag WXSA is generated during the mode write operation, the first selection data generation circuit 511 may output the ground voltage VSS as the first selection data SDQ 1. When the second mode control flag WXSB is generated during the mode write operation, the first selection data generation circuit 511 may output the power supply voltage VDD as the first selection data SDQ 1.

The second selection data generation circuit 513 may generate the second selection data SDQ2 based on the data DQ, the power supply voltage VDD, the ground voltage VSS, the write command signal WT, the first mode control flag WXSA, the second mode control flag WXSB, and the burst control flag BLEOF. When the write operation is performed in a case where the burst control flag BLEOF has the second logic level and the write command signal WT is generated such that the burst length BL has an even number, the second selection data generation circuit 513 may output the data DQ as the second selection data SDQ 2. When the first mode control flag WXSA is generated during the mode write operation, the second selection data generation circuit 513 may output the ground voltage VSS as the second selection data SDQ 2. When the second mode control flag WXSB is generated during the mode write operation, the second selection data generation circuit 513 may output the power supply voltage VDD as the second selection data SDQ 2.

The selection parity bit generation circuit 515 may generate the selection parity bit SPRT based on the parity bit PRT, the ground voltage VSS, the write command signal WT, the first mode control flag WXSA, and the second mode control flag WXSB. When the write command signal WT is generated to perform a write operation, the selection parity bit generation circuit 515 may output the parity bit PRT as the selection parity bit SPRT. When the first mode control flag WXSA or the second mode control flag WXSB is generated during the mode write operation, the selection parity bit generation circuit 515 may output the ground voltage VSS as the selection parity bit SPRT. In the present embodiment, the selection parity bit SPRT may be driven to have the ground voltage VSS to prevent the error correction operation from being performed during the mode write operation, but according to an embodiment, the selection parity bit SPRT may also be driven to a logic level having a logic level different from the ground voltage VSS.

The selection flag generation circuit 517 may generate the selection data control signal SDMI based on the data control signal DMI, the ground voltage VSS, the write command signal WT, the first mode control flag WXSA, and the second mode control flag WXSB. When the write command signal WT is generated to perform a write operation, the selection flag generation circuit 517 may output the data control signal DMI as the selection data control signal SDMI. When the first mode control flag WXSA or the second mode control flag WXSB is generated during the mode write operation, the selection flag generation circuit 517 may output the ground voltage VSS as the selection data control signal SDMI. In the present embodiment, the selection data control signal SDMI may be driven to have the ground voltage VSS to prevent the data inversion operation and the data masking operation from being performed during the mode write operation, but the selection data control signal SDMI may also be driven to have a logic level different from the ground voltage VSS according to an embodiment.

When a write operation or a mode write operation is performed, the input drive circuit 53 may generate the drive data DQ _ DRV, the drive parity PRT _ DRV, and the drive data control signal DMI based on the first selection data SDQ1, the second selection data SDQ2, the selection parity SPRT, and the selection data control signal SDMI. The input driving circuit 53 may include a first input driver 531, a second input driver 533, a third input driver 535, and a fourth input driver 537.

The first input driver 531 may generate the driving data DQ _ DRV based on the data input pulse DINP and the first selection data SDQ 1. When a write operation or a pattern write operation is performed to generate the data input pulse DINP, the first input driver 531 may drive the driving data DQ _ DRV to have the same logic level as the first selection data SDQ 1.

The second input driver 533 may generate the driving data DQ _ DRV based on the data input pulse DINP and the second selection data SDQ 2. When a write operation or a pattern write operation is performed to generate the data input pulse DINP, the second input driver 533 may drive the driving data DQ _ DRV to have the same logic level as the second selection data SDQ 2.

The third input driver 535 may generate the driving parity bit PRT _ DRV based on the data input pulse DINP and the selection parity bit SPRT. When a write operation or a mode write operation is performed to generate the data input pulse DINP, the third input driver 535 may drive the driving parity bits PRT _ DRV to have the same logic level as the selection parity bits SPRT.

The fourth input driver 537 may generate the driving data control signal DMI _ DRV based on the data input pulse DINP and the selection data control signal SDMI. When a write operation or a mode write operation is performed to generate the data input pulse DINP, the fourth input driver 537 may drive the driving data control signal DMI _ DRV to have the same logic level as the selection data control signal SDMI.

The core data generation circuit 55 may generate the core data CDQ based on the drive data DQ _ DRV, the drive parity PRT _ DRV, the error correction activation signal ECCEN, the drive data control signal DMI _ DRV, and the write input pulse win. The error correction enable signal ECCEN may be generated to have a logic "high" level when the error correction operation is performed. The core data generation circuit 55 may generate the first internal data IDQ1 from the drive data DQ _ DRV when the error correction operation is not performed, and may generate the first internal data IDQ1 from the correction data CD generated by correcting an error included in the drive data DQ _ DRV when the error correction operation is performed. The core data generation circuit 55 may generate the second internal data IDQ2 from the first internal data IDQ1 when the data inversion operation is not performed, and may generate the second internal data IDQ2 by inverting-buffering the first internal data IDQ1 when the data inversion operation is performed. The write input pulse win may be generated at a time point when a predetermined write input delay period elapses from a time point at which the write command signal WT or the pattern write command signal WRX is generated. For some embodiments, the predetermined write input delay period is set to be longer than the input delay period. When the write input pulse win is generated, the core data generation circuit 55 may drive the core data CDQ based on the second internal data IDQ 2.

The core data generation circuit 55 may include a syndrome generation circuit 551, an error correction circuit 553, a first internal data selection circuit 555, an inverter IV51, a second internal data generation circuit 557, and a first core driver 559, which are electrically connected in sequence. The syndrome generation circuit 551 may generate the syndrome SYN based on the driving data DQ _ DRV and the driving parity PRT _ DRV. The syndrome generation circuit 551 may generate the syndrome SYN by performing a logical arithmetic operation on bits selected from bits included in the drive data DQ _ DRV and the drive parity PRT _ DRV according to an error check matrix used in the error correction code ECC. The syndrome SYN may include information on an error bit among bits included in the driving data DQ _ DRV. The error correction circuit 553 may generate the correction data CD by correcting at least one error bit among the bits included in the driving data DQ _ DRV based on the syndrome SYN. The first internal data selection circuit 555 may output the driving data DQ _ DRV or the correction data CD as the first internal data IDQ1 based on the error correction enable signal ECCEN. When the error correction enable signal ECCEN is not generated because an error correction operation is not performed, the first internal data selection circuit 555 may output the driving data DQ _ DRV as the first internal data IDQ 1. When the error correction operation is performed to generate the error correction activation signal ECCEN, the first internal data selection circuit 555 may output the correction data CD as the first internal data IDQ 1. The inverter IV51 may invert the buffered first internal data IDQ1 to output the inverted buffered data of the first internal data IDQ 1. The second internal data generation circuit 557 may output the output signal of the inverter IV51 or the first internal data IDQ1 as the second internal data IDQ2 based on the driving data control signal DMI _ DRV. When the data inversion operation is performed, the second internal data generation circuit 557 may output the output signal of the inverter IV51 as the second internal data IDQ2 based on the driving data control signal DMI _ DRV. When the data inversion operation is not performed, the second internal data generation circuit 557 may output the first internal data IDQ1 as the second internal data IDQ2 based on the driving data control signal DMI _ DRV. The first core driver 559 may generate the core data CDQ based on the write input pulse win and the second internal data IDQ 2. When a write operation or a pattern write operation is performed to generate the write input pulse win, the first core driver 559 may drive the core data CDQ to have the same logic level as the second internal data IDQ 2.

The data mask control circuit 57 may generate the data mask signal CDM based on the driving data control signal DMI _ DRV, the data inversion activation signal DBI _ EN, and the write input pulse win. When the data inversion operation is performed, the data inversion activation signal DBI _ EN may be generated to have a logic "high" level. When the data inversion operation is performed, the data mask control circuit 57 may transfer the driving data control signal DMI _ DRV to the core data generation circuit 55, so that the second internal data IDQ2 is generated from a signal obtained by inverting the buffered first internal data IDQ 1. When the data inversion operation is performed, the data mask control circuit 57 may set the internal data mask signal IDM to the ground voltage VSS to prevent the data mask operation from being performed. When the data inversion operation is not performed, the data mask control circuit 57 may output the driving data control signal DMI _ DRV as the internal data mask signal IDM. When the write input pulse win is generated, the data mask control circuit 57 may generate the data mask signal CDM from the internal data mask signal IDM.

The data mask control circuit 57 may include a data mask selection circuit 571 and a second core driver 573. The data mask selection circuit 571 may output the driving data control signal DMI _ DRV or the ground voltage VSS as the internal data mask signal IDM based on the data inversion activation signal DBI _ EN. When the data inversion activation signal DBI _ EN has a logic "low" level due to the data inversion operation not being performed, the data mask selection circuit 571 may output the driving data control signal DMI _ DRV as the internal data mask signal IDM. When the data inversion activation signal DBI _ EN has a logic "high" level due to the data inversion operation being performed, the data mask selection circuit 571 may output the ground voltage VSS as the internal data mask signal IDM. When a write operation or a pattern write operation is performed to generate the write input pulse win, the second core driver 573 may drive the data masking signal CDM to have the same logic level as the internal data masking signal IDM.

The memory core 59 may include a plurality of memory cell arrays (not shown) that store core data CDQ based on the data masking signal CDM. When the masking operation is performed during the write operation, the memory core 59 may block bits selected based on the data masking signal CDM among bits included in the storage core data CDQ.

Referring to fig. 8, data DQ input to the data pin is listed according to the burst length BL. When the burst length BL is "1", the first to eighth bits DQ <1:8> of the data input to the first to eighth data pins may all be set to have a logic "high" level, when the burst length BL is "2", the first to eighth bits DQ <1:8> of the data input to the first to eighth data pins may all be set to have a logic "low" level, when the burst length BL is '15', the first to eighth bits DQ <1:8> of the data input to the first to eighth data pins may all be set to have a logic 'high' level, and when the burst length BL is '16', the first to eighth bits DQ <1:8> of the data input to the first to eighth data pins may all be set to have a logic 'low' level. When the burst length BL is an odd number and the first to eighth bits DQ <1:8> of the data are all set to have a logic "high" level, all bits included in the first selection data SDQ1 may be set to have a logic "high" level during a write operation. When the burst length BL is an even number and the first to eighth bits DQ <1:8> of the data are all set to have a logic "low" level, all bits included in the second selection data SDQ2 may be set to have a logic "low" level during a write operation.

The semiconductor device 150b having the foregoing configuration can set the first selection data SDQ1 or the second selection data SDQ2 to the power supply voltage VDD or the ground voltage VSS to use the syndrome generating circuit 551 and the error correcting circuit 553 which are set to perform the error correcting operation, without any design change of the syndrome generating circuit 551 and the error correcting circuit 553 even for the mode writing operation. Therefore, the layout area and power consumption of the semiconductor device 150b can be reduced. Further, the semiconductor device 150b may set the selection parity bit SPRT and the selection data control signal SDMI to the ground voltage VSS to use the second internal data generation circuit 557 set to perform a data inversion operation and the data mask selection circuit 571 set to perform a data mask operation, without any design change of the second internal data generation circuit 557 and the data mask selection circuit 571 even for a mode write operation. Therefore, the layout area and power consumption of the semiconductor device 150b can also be reduced.

According to the present disclosure, by setting selection data and selection parity bits generated from data and parity bits during a write operation to predetermined logic levels during a mode write operation, a circuit configured to perform an error correction operation during a write operation can also be used for a mode write operation without any design change. Therefore, the layout area and power consumption of the semiconductor device can be reduced.

Further, according to the present disclosure, by setting the selection data control signal generated by the data control signal during the write operation to a predetermined logic level during the mode write operation, the circuit set to perform the data inversion operation and the data masking operation during the write operation can also be used for the mode write operation without any design change. Therefore, the layout area and power consumption of the semiconductor device can be reduced.

Further, according to the present disclosure, by setting the selection data and the selection parity to predetermined logic levels according to the burst flag during the mode write operation, the circuit configured to perform the error correction operation during the write operation can also be used for the mode write operation without any design change. Therefore, the layout area and power consumption of the semiconductor device can be reduced.

Further, according to the present disclosure, by setting the selection data control signal to a predetermined logic level according to the burst flag during the mode write operation, the circuit set to perform the data inversion operation and the data masking operation during the write operation can also be used for the mode write operation without any design change. Therefore, the layout area and power consumption of the semiconductor device can be reduced.