1. A memory device, comprising:

a plurality of data input pads and at least one test data input pad;

a plurality of data input circuits corresponding to the plurality of channels, respectively, the plurality of data input circuits being adapted to transmit respective data received through the data input pads to the corresponding channels; and

a test control circuit adapted to select at least one data input circuit among the plurality of data input circuits based on the test mode information during a test operation, and to control the selected data input circuit to transmit the setting data to the corresponding channel.

2. The memory device of claim 1, wherein during the test operation, other ones of the plurality of data input circuits except the selected data input circuit are adapted to transmit test data received through the at least one test data input pad to a corresponding channel in response to a control signal generated by the test control circuit.

3. The memory device according to claim 2, wherein the test control circuit is adapted to generate a first control signal and a plurality of second control signals as the control signals based on the test mode information in response to a test enable signal activated during the test operation.

4. The memory device according to claim 3, wherein the test control circuit is adapted to generate the first control signal by inverting the test enable signal, and to select at least one second control signal among the plurality of second control signals based on the test mode information to generate the selected second control signal, the selected second control signal having a different logic level from the other second control signals.

5. The memory device of claim 3, wherein each data input circuit of the plurality of data input circuits comprises:

a first transmitter adapted to transmit data received through a corresponding data input pad among the plurality of data input pads to a first node in response to the first control signal;

a first driver adapted to drive the first node with a supply voltage level in response to the first control signal;

a second transmitter adapted to transmit the test data received through the at least one test data input pad to a second node in response to a corresponding second control signal among the plurality of second control signals; and

a second driver adapted to drive the second node with the supply voltage level in response to the corresponding second control signal among the plurality of second control signals.

6. The memory device of claim 5, wherein each data input circuit of the plurality of data input circuits further comprises:

a logic gate adapted to perform a logic operation on signals of the first and second nodes to generate a result signal, and to output the result signal to a corresponding channel.

7. The memory device of claim 1, further comprising:

a base die comprising the plurality of data input pads and the at least one test data input pad; and

a plurality of core dies stacked over the base die to receive data through the channels.

8. The memory device of claim 7, wherein the plurality of data input pads comprise micro bump pads, and wherein the at least one test data input pad comprises a direct access pad.

9. A memory device, comprising:

at least one test data input pad;

a test control circuit adapted to generate a first control signal and a plurality of second control signals based on the test mode information in response to a test enable signal activated during a test operation; and

a plurality of data input circuits corresponding to the plurality of channels, respectively, the plurality of data input circuits being adapted to transmit setting data or test data received through the at least one test data input pad to the corresponding channels, respectively, in response to the first control signal and the plurality of second control signals.

10. The memory device according to claim 9, wherein the test control circuit is adapted to generate the first control signal by inverting the test enable signal, and to select at least one second control signal among the plurality of second control signals based on the test mode information to generate the selected second control signal, the selected second control signal having a different logic level from the other second control signals.

11. The memory device of claim 10, wherein at least one of the plurality of data input circuits is adapted to transmit the setting data to a corresponding channel in response to the selected second control signal.

12. The memory device of claim 11, wherein other ones of the plurality of data input circuits than the at least one data input circuit are adapted to transmit the test data received through the at least one test data input pad to a corresponding channel in response to the other second control signals.

13. The memory device of claim 9, further comprising:

a plurality of data input pads;

wherein the plurality of data input circuits transmit respective data received through the data input pads to corresponding channels.

14. The memory device of claim 13, wherein each data input circuit of the plurality of data input circuits comprises:

a first transmitter adapted to transmit data received through a corresponding data input pad among the plurality of data input pads to a first node in response to the first control signal;

a first driver adapted to drive the first node with a supply voltage level in response to the first control signal;

a second transmitter adapted to transmit the test data received through the at least one test data input pad to a second node in response to a corresponding second control signal among the plurality of second control signals; and

a second driver adapted to drive the second node with the supply voltage level in response to the corresponding second control signal among the plurality of second control signals.

15. A memory device, comprising:

a base die; and

a plurality of core dies stacked over the base die;

wherein the base die comprises:

at least one test data input pad;

a plurality of data input circuits adapted to copy test data received through the at least one test data input pad during a test operation and to transmit the copied test data to the core die; and

a test control circuit adapted to select at least one data input circuit among the plurality of data input circuits based on test mode information during the test operation, and to control the selected data input circuit to transmit setting data to the core die.

16. The memory device of claim 15, wherein the base die further comprises:

a plurality of data input pads;

wherein the data input circuits are adapted to transmit respective data received through the data input pads to the core die during normal operation.

17. The memory device of claim 16, wherein the test control circuit is adapted to generate a first control signal and a plurality of second control signals based on the test mode information in response to a test enable signal being activated during the test operation.

18. The memory device of claim 17, wherein the test control circuit is adapted to generate the first control signal by inverting the test enable signal, and to select at least one second control signal among the plurality of second control signals based on the test mode information to generate the selected second control signal, the selected second control signal having a different logic level from the other second control signals.

19. The memory device of claim 17, wherein each of the data input circuits comprises:

a first transmitter adapted to transmit data received through a corresponding data input pad among the plurality of data input pads to a first node in response to the first control signal;

a first driver adapted to drive the first node with a supply voltage level in response to the first control signal;

a second transmitter adapted to transmit the test data received through the at least one test data input pad to a second node in response to a corresponding second control signal among the plurality of second control signals; and

a second driver adapted to drive the second node with the supply voltage level in response to the corresponding second control signal among the plurality of second control signals.

Background

With the rapid development of semiconductor memory technology, a high level of integration and performance is required in packaging semiconductor memory devices. To meet such demands, researchers and industries are developing various technologies related to a three-dimensional structure in which a plurality of semiconductor memory chips are vertically stacked, rather than a two-dimensional structure in which semiconductor memory chips are planarly disposed on a Printed Circuit Board (PCB) using wires or bumps.

In addition, as the operating speed of semiconductor memory devices increases, semiconductor memory systems in the form of System In Package (SIP) in which a memory controller such as a Central Processing Unit (CPU) or a Graphic Processing Unit (GPU) and the semiconductor memory devices are integrated into one package are widely used. Since the pad of the semiconductor memory device of the stack structure or the SIP structure is not exposed to the outside of the semiconductor memory device, it is difficult to perform a direct test by using the pin of the test equipment.

Accordingly, the semiconductor memory device may be provided with an additional pad for testing. Inevitably, the number of test pads of the integrated and miniaturized semiconductor memory device may be limited, resulting in a need to develop a technology capable of testing the semiconductor memory device with a limited number of test pads.

Disclosure of Invention

Some embodiments of the present teachings are directed to a data input circuit capable of setting and copying input data in various modes, and a memory device including the data input circuit.

According to one embodiment of the present disclosure, a memory device includes a plurality of data input pads and at least one test data input pad. The memory device further includes a plurality of data input circuits corresponding to the plurality of channels, respectively, the plurality of data input circuits being adapted to transmit respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit adapted to select at least one data input circuit among the plurality of data input circuits based on the test mode information during a test operation, and to control the selected data input circuit to transmit the setting data to the corresponding channel.

According to another embodiment of the present disclosure, a memory device includes at least one test data input pad. The memory device further includes a test control circuit adapted to generate a first control signal and a plurality of second control signals based on the test mode information in response to a test enable signal activated during a test operation. The memory device further includes a plurality of data input circuits corresponding to the plurality of channels, respectively, the plurality of data input circuits being adapted to transmit the setting data or the test data received through the at least one test data input pad to the corresponding channels, respectively, in response to the first control signal and the plurality of second control signals.

According to yet another embodiment of the present disclosure, a memory device includes a base die and a plurality of core dies stacked over the base die. The base die includes at least one test data input pad. The base die further includes a plurality of data input circuits adapted to copy test data received through the at least one test data input pad during a test operation and to transmit the copied test data to the core die. The base die further includes a test control circuit adapted to select at least one data input circuit among the plurality of data input circuits based on the test mode information during a test operation, and to control the selected data input circuit to transmit the setting data to the core die.

Drawings

Fig. 1 is a plan view illustrating a memory system according to one embodiment of the present disclosure.

Fig. 2 is a cross-sectional view illustrating the memory system shown in fig. 1.

Fig. 3 is a block diagram illustrating the memory device shown in fig. 1.

FIG. 4 is a block diagram illustrating a memory device according to one embodiment of the present disclosure.

Fig. 5 is a block diagram illustrating the data input circuit shown in fig. 4.

Fig. 6 is a signal waveform diagram illustrating an operation of a memory device according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present teachings will be described in detail below with reference to the attached drawings. The present teachings may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that those skilled in the art will be able to practice the disclosure. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present teachings.

Fig. 1 is a plan view illustrating a memory system 100 according to one embodiment of the present disclosure.

Referring to fig. 1, the memory system 100 may have a System In Package (SIP) structure. Memory system 100 may include a controller 110 and a plurality of memory devices 120, 121, 122, 123, 124, and 125.

The controller 110 may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), an Application Processor (AP), a memory controller chip, and the like. Various types of processing units may be included in the controller 110 in the form of a system on a chip (SoC). In other words, the controller 110 may represent one chip in which various systems are integrated.

Each of memory devices 120 through 125 may include a plurality of integrated circuit chips. Integrated circuit chips may be stacked on top of each other and electrically connected using through-silicon vias (TSVs). In other words, the memory devices 120 to 125 may be formed of a High Bandwidth Memory (HBM) in which a bandwidth is increased by increasing the number of input/output units.

However, the present teachings are not limited thereto, and the memory devices 120 to 125 are not only volatile memory devices using memories such as Dynamic Random Access Memories (DRAMs), but also nonvolatile memory devices such as flash memory devices, phase change random access memory devices (PCRAMs) and resistive random access memory devices (rerams), ferroelectric memory devices (ferams), magnetic random access memory devices (MRAMs), spin transfer torque random access memory devices (STTRAMs), and the like. Alternatively, memory devices 120 through 125 may be formed as a combination of two or more of volatile memory devices and non-volatile memory devices.

Controller 110 and memory devices 120 through 125 may be stacked on an interposer. The controller 110 and the memory devices 120 through 125 may communicate with each other through signal paths formed in an interposer. To communicate with controller 110, memory devices 120-125 may include PHY interfaces PHY0, PHY1, PHY2, PHY3, PHY4, and PHY5 coupled to an interposer by microbumps. However, since the physical size of the microbumps is very small and the number of microbumps is greater than about 1000, it may be difficult to test the memory devices 120-125 through the PHY interfaces PHY 0-PHY 5.

Thus, memory devices 120-125 may include Direct Access (DA) interfaces DA0, DA1, DA2, DA3, DA4, and DA5 for directly accessing and testing memory devices 120-125 from outside memory devices 120-125, respectively. The DA interfaces DA 0-DA 5 may be interfaced through a relatively larger and smaller number of direct access pads than the physical size of the micro-bumps and may be used for testing.

Fig. 2 is a cross-sectional view illustrating the memory system 100 shown in fig. 1.

Fig. 2 shows a structure in which the controller 110 and the first memory device 120 among the memory devices 120 to 125 are stacked. Although not illustrated in fig. 2, the second to sixth memory devices 121 to 125 may also have a similar stack structure to the first memory device 120.

The memory system 100 may further include a package substrate 210 and an interposer 220 stacked over the package substrate 210. The interposer 220 may be stacked over the package substrate 210 or coupled to the package substrate 210 by electrical connection means (such as bump balls, ball grid arrays, etc.). The controller 110 and the first memory device 120 may also be stacked on top of the interposer 220 and electrically connected to the interposer 220 through micro-bumps.

The first memory device 120 may include a plurality of integrated circuit chips 230 and 240 stacked on each other. The integrated circuit chips 230 and 240 may be electrically connected to each other through micro bumps and Through Silicon Vias (TSVs) formed to vertically penetrate the inside of the integrated circuits 230 and 240 to transmit and receive signals.

The integrated circuit chips 230 and 240 may include a base die 230 and a plurality of core dies 240. The core die 240 may be provided with data storage space, such as memory cell arrays and memory registers for storing data. On the other hand, circuitry for transmitting signals between the core die 240 and the controller 110 may be provided in the base die 230.

As described above, the first memory device 120 may communicate with the controller 110 through the PHY interface 250 coupled with the microbumps. Also, the first memory device 120 may be directly accessed and tested from outside the first memory device 120 through the DA interface 260 formed by the direct access pad. The direct access pads may be provided in a relatively larger size and smaller number than the micro bumps.

Fig. 3 is a block diagram illustrating the memory device 300 shown in fig. 1.

Fig. 3 shows the base die of memory device 300 and shows the portions related to the DA interface and the PHY interface. The memory device 300 may include a plurality of data input pads 310 to 317, at least one test data input pad 320, and a plurality of data input circuits 330 to 337. The data input pads 310 to 317 may include micro bump pads as PHY interfaces. In normal operation, data PHY _ DQ <0:31> may be input from the host through data input pads 310-317.

The at least one test data input pad 320 may include a direct access pad as a DA interface. During a test operation, test data DA _ DQ <0:3> may be input from outside the memory device 300 through the at least one test data input pad 320.

The data input circuits 330 to 337 may correspond to the plurality of channels CH0 to CH7, respectively. In normal operation, the data input circuits 330 to 337 may transfer the data PHY _ DQ <0:31> received by the data input pads 310 to 317, respectively, to the corresponding lanes.

Meanwhile, during a test operation, the data input circuits 330 to 337 may transfer test data DA _ DQ <0:3> received by at least one test data input pad 320 to a corresponding channel in response to a test enable signal EN. When the test enable signal EN is activated during a test operation, the data input circuits 330 to 337 may transmit test data DA _ DQ <0:3> received by at least one test data input pad 320 to the channels CH0 to CH7 instead of data PHY _ DQ <0:31> received by the data input pads 310 to 317.

As described above, the at least one test data input pad 320 may be relatively large in size and small in number as compared to the data input pads 310 to 317. Accordingly, during a test operation, the data input circuits 330 to 337 may copy the test data DA _ DQ <0:3> received through the at least one test data input pad 320 and transmit the same to the channels CH0 to CH 7.

In a test operation, memory device 300 may transfer test data DA _ DQ <0:3> to the core die through channels CH 0-CH 7. The data transferred to the core die may be stored in memory cells included in the core die. Herein, the memory device 300 may perform an Error Correction Code (ECC) operation to detect and correct errors occurring in data stored in the memory cells.

For example, the memory device 300 may generate parity data by performing an ECC encoding operation on the test data DA _ DQ <0:3>, and store a codeword formed of the test data DA _ DQ <0:3> and the parity data in the memory cells. The memory device 300 may perform an ECC decoding operation on data read from the memory cells and detect and correct errors occurring in the data stored in the memory cells based on the parity data.

During the test operation, the memory device 300 may also be tested for ECC operations. The memory device 300 may check whether the ECC operation is normally performed based on the logic level of the parity data generated by the ECC operation. However, when the same pattern of data is used by copying the test data DA _ DQ <0:3>, the parity data may also be generated in a uniform pattern. Thus, it may be difficult to accurately test the ECC operation of the memory device 300.

FIG. 4 is a block diagram illustrating a memory device 400 according to one embodiment of the present disclosure.

Fig. 4 shows the base die of the memory device 400, and fig. 4 shows the portions related to the DA interface and the PHY interface. The memory device 400 may include a test control circuit 410, a plurality of data input pads 420 to 427, at least one test data input pad 430, and a plurality of data input circuits 440 to 447.

The data input pads 420 to 427 may include micro bump pads as PHY interfaces. In normal operation, data PHY _ DQ <0:31> may be input from the host through data input pads 420 through 427.

The at least one test data input pad 430 may include a direct access pad as a DA interface. During a test operation, test data DA _ DQ <0:3> may be input from outside the memory device 400 through the at least one test data input pad 430.

The data input circuits 440 to 447 may correspond to the channels CH0 to CH7, respectively. In normal operation, the data input circuits 440 to 447 may transfer the data PHY _ DQ <0:31> received by the data input pads 420 to 427 to the corresponding lanes, respectively.

In a test operation, the test control circuit 410 may generate a first control signal based on the test mode information TM in response to the test enable signal ENAnd a plurality of second control signals TM<0:7>. Herein, the test enable signal EN may represent a signal that is activated during a test operation. The test mode information TM may be stored as a predetermined value in a mode register set or the like, or the test mode information TM may beTo be generated by combining addresses input from the outside of the memory device 400 during the test operation.

Specifically, the test control circuit 410 may generate the first control signal by inverting the test enable signal ENWhen the test enable signal EN is activated, the test control circuit 410 may control the second control signal TM according to a code value of the test mode information TM<0:7>Selects at least one signal and generates a first control signalTo have a different logic level than that of the other signals. For example, the test control circuit 410 may be in the state of applying the second control signal TM<0:7>At least one selected signal is deactivated while the other signals are activated. At the second control signal TM<0:7>While at least one selected signal of the same may be activated, other signals may be deactivated, which may be implemented differently according to one embodiment of the present teachings.

During test operation, the data input circuits 440 to 447 may be responsive to a first control signalAnd a second control signal TM<0:7>Setting data or test data DA _ DQ received through at least one test data input pad 430<0:3>Respectively transmitted to the corresponding channels. In other words, the second control signal TM is inputted to and outputted from the data input circuits 440 to 447<0:7>The data input circuit corresponding to the selected signal may transmit the setting data to the corresponding channel. On the other hand, the second control signal TM is asserted among the data input circuits 440 to 447<0:7>May test the data DA _ DQ<0:3>To the corresponding channel.

Accordingly, during a test operation, the test control circuit 410 may control the test by using the first control signalAnd a second control signal TM<0:7>At least one data input circuit is selected among the data input circuits 440 to 447, and the selected data input circuit is controlled to transmit the setting data to the corresponding channel. The test control circuit 410 may control the other data input circuits except the selected data input circuit among the data input circuits 440 to 447 to input test data DA _ DQ<0:3>To the corresponding channel.

Fig. 5 is a block diagram illustrating the data input circuit 440 shown in fig. 4.

The data input circuit 440 may include a first transmitter 510, a second transmitter 520, a first driver 530, a second driver 540, and a signal combining unit 550. Although fig. 5 illustrates one of the data input circuits 440 to 447 shown in fig. 4, all of the data input circuits 440 to 447 of fig. 4 may have a similar structure except that their input and output signals are different.

The first transmitter 510 may be responsive to a first control signalAnd transfers the data PHY _ DQ received by the corresponding data input pad 420 among the data input pads 420 to 427 to the first node ND1<0:3>. The first transmitter 510 may include a first inverter IV1 and a first transmission gate TG 1. The first inverter IV1 may output the first control signalInverted and output, and the first transmission gate TG1 may be responsive to a first control signalAnd an output signal of the first inverter IV1 to convert data PHY _ DQ<0:3>To the first node ND 1.

The second transmitter 520 may transmit the test data DA _ DQ <0:3> received through the at least one test data input pad 430 to the second node ND2 in response to a corresponding second control signal TM <0> among the second control signals TM <0:7 >. The second transmitter 520 may include a second inverter IV2 and a second transmission gate TG 2. The second inverter IV2 may invert and output the corresponding second control signal TM <0>, and the second transmission gate TG2 may output the test data DA _ DQ <0:3> to the second node ND2 in response to the corresponding second control signal TM <0> and the output signal of the second inverter IV 2.

The first driver 530 may be responsive to a first control signalThe first node ND1 is driven with the power supply voltage VDD level. The first driver 530 may include a first PMOS transistor PM1, the first PMOS transistor PM1 being coupled between the power supply voltage VDD terminal and the first node ND1 to receive the first control signal through the gate

The second driver 540 may drive the second node ND2 with the power supply voltage VDD level in response to a corresponding second control signal TM <0> among the second control signals TM <0:7 >. The second driver 540 may include a second PMOS transistor PM2, the second PMOS transistor PM2 being coupled between the power supply voltage VDD terminal and the second node ND2 to receive a corresponding second control signal TM <0> through the gate.

The signal combining unit 550 may combine the signals of the first node ND1 and the second node ND2 to generate a combined signal, and output the combined signal to the corresponding channel CH 0. The signal combining unit 550 may include a NAND gate that receives signals from the first node ND1 and the second node ND2 and performs a logical operation.

When the test enable signal EN is deactivated during normal operation, the test control circuit 410 may assert all of the second control signals TM<0:7>Deactivating while generating a first control signal of logic high levelFirst control signal responding to logic high levelThe first transmitter 510 may transmit data PHY _ DQ<0:3>To the first node ND1, and the first driver 530 may be turned off. On the other hand, the second control signal TM<0:7>May be disabled and the second transmitter 520 may block the test data DA _ DQ<0:3>And the second driver 540 may drive the second node ND2 with the power supply voltage VDD level. Accordingly, the signal of the second node ND2 may have a logic high level, and the signal combining unit 550 may combine the data PHY _ DQ of the first node ND1<0:3>To the corresponding channel CH 0.

During a test operation, when the test enable signal EN is activated, the test control circuit 410 may generate the first control signal of a logic low levelFirst control signal responsive to logic low levelThe first transmitter 510 may block the data PHY _ DQ<0:3>And the first driver 530 may drive the first node ND1 with the power supply voltage VDD level.

Herein, when the test control circuit 410 selects and deactivates the corresponding second control signal TM <0> among the second control signals TM <0:7>, the second transmitter 520 may block the transfer of the test data DA _ DQ <0:3>, and the second driver 540 may drive the second node ND2 with the power supply voltage VDD level. Accordingly, the signals of the first node ND1 and the second node ND2 may each have a logic high level, and the signal combining unit 550 may transfer the data set to the logic low level to the corresponding channel CH 0.

Meanwhile, when the test control circuit 410 selects another second control signal among the second control signals TM <0:7> and activates the corresponding second control signal TM <0>, the second transmitter 520 may transmit the test data DA _ DQ <0:3> to the second node ND2, and the second driver 540 may be turned off. Accordingly, the signal of the first node ND1 may have a logic high level, and the signal combination unit 550 may transfer the test data DA _ DQ <0:3> of the second node ND2 to the corresponding channel CH 0.

Fig. 6 is a signal waveform diagram illustrating an operation of the memory device 400 according to an embodiment of the present disclosure.

The test enable signal EN may be activated when the memory device 400 enters a test mode. Subsequently, after a write latency WL according to a write command WR directing a write operation, the memory device 400 may be synchronized with a data strobe signal WDQS to receive test data DA _ DQ <0:3> through the test data input pad 430.

The test control circuit 410 may invert the first control signal by inverting the activated test enable signal ENAnd (6) deactivating. Accordingly, the first transmitter of each of the data input circuits 440 to 447 may block the data PHY _ DQ<0:31>And the first driver of each of the data input circuits 440 to 447 may drive the first node with the power supply voltage VDD level.

Herein, as shown in an example in fig. 6, the test control circuit 410 may select and deactivate the second signal among the second control signals TM <0:7> according to the test mode information TM. Accordingly, among the data input circuits 440 to 447, the second transmitter of the second data input circuit may block the transfer of the test data A, B, C and D, and the second driver of the second data input circuit may drive the second node with the power supply voltage VDD level. As a result, the second data input circuit among the data input circuits 440 to 447 can transmit data set to a logic low level 0 to the corresponding channel CH 1.

Meanwhile, the test control circuit 410 may activate other second control signals except for the selected second control signal among the second control signals TM <0:7 >. Accordingly, in the data input circuits other than the second data input circuit among the data input circuits 440 to 447, the second transmitter may transmit the test data A, B, C and D to the second node, and the second driver may be turned off. As a result, the other data input circuits than the second data input circuit among the data input circuits 440 to 447 can transmit the test data A, B, C and D to the corresponding channels CH0 and CH2 to CH 7.

The memory device 400 according to an embodiment of the present disclosure may be able to mask some data and transmit setting data based on the test mode information TM by copying data received by the test input pad 430 and transmitting the copied data to the channels CH0 to CH 7. The memory device 400 may be capable of transferring data of a mode set according to a test operation to the channels CH0 through CH 7. Accordingly, the result data according to various operations of the memory device 400 may be predicted, and the coverage of operations that may be tested may be increased.

According to an embodiment of the present disclosure, a memory device may be tested by copying data received through a limited number of test input pads, thereby minimizing the number of test input pads and increasing the efficiency of a test operation. Further, when the received data is copied, the copied data may be set in various modes to test various operations of the memory device.

For example, a plurality of data input circuits that receive and copy data may be selectively disabled according to the test pattern information. In other words, some of the data copied by the data input circuit may be selectively masked. Accordingly, data patterns generated by various operations of the memory device, such as Error Correction Code (ECC) operations, etc., may also be predicted by using data of a desired pattern, thereby increasing the coverage of test operations.

Although the present teachings have been described with respect to particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.