1. An organic light emitting diode display, the organic light emitting diode display comprising:

an organic light emitting diode formed in the display region;

a pixel defining layer including a first portion disposed in the display area and a second portion disposed in a non-display area surrounding the display area;

a planarization layer disposed under the pixel defining layer;

an insulating layer disposed under the planarization layer;

a first passivation layer covering at least the second portion of the pixel defining layer;

a second passivation layer disposed in the non-display region;

a filler covering the first passivation layer and the second passivation layer; and

a sealant disposed in the non-display region and overlapping the insulating layer in a plan view,

wherein the second passivation layer contacts a portion of the first passivation layer, and

wherein the second passivation layer includes a first portion contacting the first passivation layer and a second portion overlapping the filler.

2. The organic light-emitting diode display defined in claim 1 wherein the second portion of the second passivation layer is disposed between the planarization layer and the filler.

3. The organic light-emitting diode display defined in claim 2 wherein, in plan view, ends of the pixel-defining layer are disposed between edges of the display area and edges of the filler.

4. The organic light-emitting diode display defined in claim 2 wherein each of the pixel-defining layer and the planarization layer is formed from a silicon-based polymer.

5. The organic light emitting diode display defined in claim 2 wherein the planarization layer forms an opening to expose an interlayer insulating layer formed below the planarization layer and wherein the second passivation layer covers the exposed interlayer insulating layer.

6. The organic light emitting diode display defined in claim 1 wherein the organic light emitting diode comprises a pixel electrode, an emissive layer, and a common electrode.

7. The organic light emitting diode display defined in claim 6 wherein the first passivation layer contacts the common electrode and is formed of the same material as the common electrode and wherein the second passivation layer contacts the first passivation layer and is formed of the same material as the pixel electrode.

8. The organic light emitting diode display defined in claim 6 wherein the organic light emitting diode is covered by a cover layer, the first passivation layer contacting the cover layer and being formed of the same material as the cover layer, and wherein the second passivation layer contacts the first passivation layer and being formed of the same material as the pixel electrode.

9. The organic light emitting diode display defined in claim 7 or claim 8 wherein the second passivation layer is formed from a multilayer of a first transparent layer, a thin metal layer and a second transparent layer.

10. The organic light-emitting diode display defined in claim 1 wherein the first and second passivation layers are formed on different layers.

Background

An Organic Light Emitting Diode (OLED) display does not require a separate light source, and thus the OLED display may have a reduced thickness and weight. In addition, the OLED display has good characteristics such as low power consumption, high luminance, and high response speed.

A typical OLED display includes a substrate, a driving circuit unit and an OLED formed on the substrate, a pixel defining layer defining an emission region of the OLED, and an encapsulation substrate formed opposite to the substrate. The substrate and the encapsulation substrate are integrally bonded to each other by a sealant, and a space between the substrate and the encapsulation substrate may be filled with a filler. The filler is used to increase the stiffness of the OLED display in order to enhance durability.

The above information disclosed in this background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Disclosure of Invention

One inventive aspect relates to an OLED display that can prevent defects such as pixel shrinkage due to a filler.

Another aspect is an OLED display that can suppress the occurrence of defects such as pixel shrinkage by preventing various impurities, oxygen, and the like included in the filler from permeating into the OLED through the pixel defining layer and the planarizing layer.

Another aspect is an OLED display comprising: a substrate including a display region in which the OLED is formed and a non-display region outside the display region; a pixel defining layer formed on the substrate and including an opening defining an emission region of the OLED; a first passivation layer covering a surface of a portion of the pixel defining layer formed in the non-display region; a second passivation layer formed outside the pixel defining layer in the non-display region; an encapsulation substrate formed opposite to the substrate; and a filler filling a space between the substrate and the encapsulation substrate and contacting the first passivation layer and the second passivation layer.

In plan, the ends of the pixel defining layer may be located between the edges of the display area and the edges of the filler. The second passivation layer may contact the first passivation layer.

The OLED display may further include a planarization layer formed under the pixel defining layer and the second passivation layer. The second passivation layer may cover the entire surface of the planarization layer outside the pixel defining layer. The pixel defining layer and the planarization layer may include a silicon-based polymer.

The planarization layer may form an opening to expose the interlayer insulating layer under the planarization layer, and the second passivation layer may cover the exposed interlayer insulating layer.

The OLED may include a pixel electrode, an emission layer, and a common electrode, and may be covered by a cover layer. The first passivation layer may contact the common electrode and may be made of the same material as the common electrode. The second passivation layer may contact the first passivation layer and may be made of the same material as the pixel electrode.

The first passivation layer may contact the capping layer and may be made of the same material as the capping layer. The second passivation layer may contact the first passivation layer and may be made of the same material as the pixel electrode. The second passivation layer may be formed of a plurality of layers of the first transparent layer, the thin metal layer, and the second transparent layer.

The first passivation layer may contact the capping layer and may be made of the same material as the capping layer, and the second passivation layer may contact the first passivation layer and may be made of the same material as the capping layer.

Another aspect is an Organic Light Emitting Diode (OLED) display, including: a substrate including a display region in which the OLED is formed and a non-display region around the display region; a pixel defining layer formed on the substrate and having an opening defining an emission region of the OLED; a first passivation layer covering a portion of the pixel defining layer formed in the non-display region; a second passivation layer formed in the non-display region, wherein a portion of the second passivation layer does not overlap the first passivation layer in a depth dimension of the OLED display; an encapsulation substrate formed opposite to the substrate; and a filler filling a space between the substrate and the encapsulation substrate and contacting the first passivation layer and the second passivation layer.

In the above OLED display, the ends of the pixel defining layer are located between the edges of the display area and the edges of the filler on a plane. In the above OLED display, the second passivation layer contacts the first passivation layer. The above OLED display further includes: and a planarization layer formed under the pixel defining layer and the second passivation layer, wherein the second passivation layer covers substantially the entire surface of the planarization layer outside the pixel defining layer. In the above OLED display, each of the pixel defining layer and the planarizing layer is formed of a silicon-based polymer. In the above OLED display, the planarization layer forms an opening to expose the interlayer insulating layer formed under the planarization layer, wherein the second passivation layer covers the exposed interlayer insulating layer.

In the above OLED display, the OLED includes a pixel electrode, an emission layer, and a common electrode, and may be covered by a cover layer. In the above OLED display, the first passivation layer contacts the common electrode and is made of the same material as the common electrode. In the above OLED display, the second passivation layer contacts the first passivation layer and is formed of the same material as the pixel electrode. In the above OLED display, the first passivation layer contacts the capping layer and is formed of the same material as the capping layer. In the above OLED display, the second passivation layer contacts the first passivation layer and is formed of the same material as the pixel electrode. In the above OLED display, the second passivation layer is formed of a plurality of layers of the first transparent layer, the thin metal layer, and the second transparent layer.

In the above OLED display, the second passivation layer is formed of a plurality of layers of the first transparent layer, the thin metal layer, and the second transparent layer. In the above OLED display, the first passivation layer contacts the cover layer and is formed of the same material as the cover layer, and wherein the second passivation layer contacts the first passivation layer and is formed of the same material as the cover layer. In the above OLED display, the first passivation layer and the second passivation layer are formed on different layers. In the above OLED display, the first passivation layer is formed over the second passivation layer.

Another aspect is an Organic Light Emitting Diode (OLED) display, comprising: an OLED formed in the display region; a pixel defining layer including a first portion formed in the display area and a second portion formed in a non-display area surrounding the display area; a first passivation layer covering at least a second portion of the pixel defining layer; a second passivation layer formed in the non-display region, wherein the second passivation layer contacts a portion of the first passivation layer and a portion of the second portion of the pixel defining layer; and a filler covering the first passivation layer and the second passivation layer.

In the above OLED display, the second passivation layer includes a portion that does not overlap the first passivation layer in a depth dimension of the OLED display. In the above OLED display, the first passivation layer includes a non-linear portion, wherein the second passivation layer is substantially linear. In the above OLED display, the first passivation layer and the second passivation layer are formed on different layers.

According to at least one of the disclosed embodiments, by allowing the first passivation layer and the second passivation layer to block the contact between the pixel defining layer and the planarization layer and the filler, various impurities, oxygen, and the like included in the filler may be prevented from being diffused into the pixel defining layer and the planarization layer. Defects such as deterioration and pixel shrinkage in the OLED due to the filler can be suppressed.

Drawings

Fig. 1 is a perspective view of an OLED display according to a first exemplary embodiment.

Fig. 2 is a partially enlarged cross-sectional view of the OLED display taken along line II-II of fig. 1.

Fig. 3 is a partially enlarged cross-sectional view of the OLED display taken along line III-III of fig. 1.

Fig. 4 is an enlarged cross-sectional view of an OLED display according to a second exemplary embodiment.

Fig. 5 is an enlarged cross-sectional view of an OLED display according to a third exemplary embodiment.

Detailed Description

The present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

Throughout this specification, it will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Further, in this specification, the word "on … …" means above or below the target portion, and does not necessarily mean on the upper side of the target portion based on the direction of gravity.

Additionally, unless explicitly described to the contrary, the word "comprise", and variations such as "comprises" or "comprising", will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. Further, the size and thickness of each configuration shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present disclosure is not limited thereto. In the present disclosure, the term "substantially" includes meaning to the extent that it is completely, almost completely, or in certain applications to any significant degree to those skilled in the art. The term "connected" may include electrical connections.

Fig. 1 is a perspective view of an OLED display 100 according to a first exemplary embodiment, and fig. 2 is a partially enlarged sectional view of the OLED display taken along line II-II of fig. 1.

Referring to fig. 1, the OLED display 100 includes: a substrate 110 including a display area DA and a non-display area NDA; a plurality of pixels PX formed in the display area DA on the substrate 110; an encapsulation substrate 120 formed opposite to the substrate 110; and a filler 130 filling a space between the substrate 110 and the encapsulation substrate 120. The substrate 110 and the encapsulation substrate 120 are bonded to each other to be integrally sealed with the sealant 140.

In the display area DA, an image is displayed by combining the light emitted from the pixels PX. Each pixel PX includes a driving circuit unit or driving circuit and an OLED. The driving circuit unit includes at least two thin film transistors and at least one capacitor. A pixel defining layer 115 defining an emission region of the OLED is formed on the substrate 110. The pixel defining layer 115 may be larger than the display area DA.

The OLED display 100 includes: a first passivation layer 161 covering a surface of the pixel defining layer 115 in the non-display area NDA; and a second passivation layer 162 contacting the first passivation layer 161 and formed at an outer side of the pixel defining layer 115. In the non-display area NDA, the filler 130 contacts the first passivation layer 161 and the second passivation layer 162.

The first and second passivation layers 161 and 162 prevent the pixel defining layer 115 and the planarization layer 114 from contacting the filler 130 to prevent various impurities or oxygen included in the filler 130 from diffusing into the pixel defining layer 115 and the planarization layer 114. Accordingly, defects due to the filler 130, such as deterioration and pixel shrinkage (pixel connection) in the OLED, may be suppressed.

Hereinafter, the cross-sectional structure of the OLED display 100 will be described in more detail.

The buffer layer 111 is formed on the substrate 110. The substrate 110 may be formed of glass, quartz, ceramic, polymer film, etc. and may have optical transparency. The buffer layer 111 may have a layer of silicon nitride (SiN)_X) Made of a single layer or of silicon nitride (SiN)_X) And silicon oxide (SiO)₂) And (4) forming a double layer. The buffer layer 111 serves to planarize a surface while preventing impurities from penetrating through the substrate 110.

The semiconductor layer 151 may be formed on the buffer layer 111. The semiconductor layer 151 may be made of polysilicon or an oxide semiconductor, and the semiconductor layer 151 made of an oxide semiconductor may be covered with a separate passivation layer. The semiconductor layer 151 includes a channel region undoped with impurities and source and drain regions located at both sides of the channel region and doped with impurities.

The gate insulating layer 112 is formed on the semiconductor layer 151. The gate insulating layer 112 may be made of silicon nitride (SiN)_X) Or silicon oxide (SiO)₂) Or a stack thereof. The gate electrode 152 is formed on the gate insulating layer 112. The gate electrode 152 overlaps a channel region of the semiconductor layer 151 and may include Au, Ag, Cu, Ni, Pt, Pd, Al, Mo, etc.

An interlayer insulating layer 113 is formed on the gate electrode 152. The interlayer insulating layer 113 may be made of silicon nitride (SiN)_X) Or silicon oxide (SiO)₂) Or a stack thereof.

A source electrode 153 and a drain electrode 154 are formed on the interlayer insulating layer 113. The source electrode 153 and the drain electrode 154 are connected to a source region and a drain region of the semiconductor layer 151 through via holes formed in the interlayer insulating layer 113 and the gate insulating layer 112, respectively. The source electrode 153 and the drain electrode 154 may be formed of a metal multilayer film such as Mo/Al/Mo and Ti/Al/Ti.

Fig. 2 shows a driving Thin Film Transistor (TFT) of, for example, a top gate type, but the structure of the driving Thin Film Transistor (TFT) is not limited to the illustrated example. The driving circuit unit includes a switching thin film transistor, a driving thin film transistor, and a storage capacitor, and fig. 2 shows only the driving Thin Film Transistor (TFT) for convenience.

A driving Thin Film Transistor (TFT) is covered by the planarization layer 114 and connected to the OLED to drive the OLED. The pixel electrode 155 is formed on the planarization layer 114. Pixel electrodes 155 are formed in each pixel one-to-one and connected to the drain electrode 154 of a driving Thin Film Transistor (TFT) through a via hole formed in the planarization layer 114.

The pixel defining layer 115 is formed on the planarization layer 114 and the pixel electrode 155. The pixel defining layer 115 forms an opening OP to expose a central portion of the pixel electrode 155, and the emission layer 156 will be positioned on the exposed central portion of the pixel electrode 155. That is, the opening OP is used to define an emission region of the OLED.

The pixel defining layer 115 may be made of a relatively inexpensive silicon-based polymer instead of expensive photosensitive polyimide. Further, the planarization layer 114 may also be made of the same silicon-based polymer as the pixel defining layer 115. This reduces the cost of materials, thereby helping to reduce the cost of the OLED display 100.

An emission layer 156 is formed on the pixel electrode 155, and a common electrode 157 is formed on the emission layer 156 and the pixel defining layer 115. The common electrode 157 is formed in the entire Display Area (DA), and is not distinguished for each pixel. Either one of the pixel electrode 155 and the common electrode 157 injects holes into the emission layer 156, and the other one thereof injects electrons into the emission layer 156.

The emission layer 156 includes an organic emission layer and includes at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. When the pixel electrode 155 is an anode injecting holes, a hole injection layer, a hole transport layer, an organic emission layer, an electron transport layer, and an electron injection layer may be sequentially stacked on the pixel electrode 155. Other layers than the organic emission layer may be formed on the entire display area DA.

When the OLED display 100 is a bottom emission type, the pixel electrode 155 is formed of a transparent layer or a semitransparent layer, and the common electrode 157 is formed of a reflective layer. The light emitted from the emission layer 156 is reflected from the common electrode 157 and transmitted through the pixel electrode 155 and the substrate 110 to be emitted to the outside. When the pixel electrode 155 is formed of a semi-transparent layer, a portion of light reflected from the common electrode 157 is reflected again from the pixel electrode 155, and the pixel electrode 155 and the common electrode 157 form a resonance structure to increase light extraction efficiency.

When the OLED display 100 is a top emission type, the pixel electrode 155 is formed of a reflective layer, and the common electrode 157 is formed of a transparent layer or a semi-transparent layer.

The reflective layer may include Au, Ag, Mg, Al, Pt, Pd, Ni, Nd, Ir, Cr, and the like. The transparent layer may include Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), ZnO, In₂O₃And the like. The translucent layer may be formed of a thin metal layer including Li, Ca, LiF/Al, Ag, Mg, etc., and the translucent layer may be formed of a stacked layer of the thin metal layer and the transparent layer. For example, the translucent layer may be formed of a multilayer of ITO/Ag/ITO.

The substrate 110 and the encapsulation substrate 120 are bonded to each other by the sealant 140. The sealant 140 is formed at the edges of the substrate 110 and the encapsulation substrate 120, and may include an inorganic material such as a frit or an organic material such as an epoxy. The inside of the sealant may be formed with a getter 145. The getter 145 serves to absorb moisture or oxygen penetrating the sealant 140, and may include CaO, BaO, MgO, etc. having excellent reactivity to moisture or oxygen.

The space between the substrate 110 inside the getter 145 and the encapsulation substrate 120 is filled with the filler 130. The filler 130 fills the empty space between the substrate 110 and the encapsulation substrate 120 for increasing the rigidity of the OLED display 100. That is, the OLED display 100 including the filler 130 has improved durability against external impacts (e.g., dropping). The filler 130 may be a transparent isotropic material and may include a transparent silicon-based polymer.

The buffer layer 111, the gate insulating layer 112, and the interlayer insulating layer 113 may be formed to have the same size as the substrate 110, and the planarization layer 114 may be formed to be smaller than the interlayer insulating layer 113 such that an edge of the planarization layer overlaps the getter 145 on a plane. Further, in a plane, an end portion of the pixel defining layer 115 may be located between an edge of the display area DA and an edge of the filler 130. The edge of the pixel defining layer 115 is spaced apart from the getter 145 by a predetermined distance.

In the pixel defining layer 115, a surface of a portion formed in the display area DA is covered with the common electrode 157, and a surface of a portion formed in the non-display area NDA is covered with the first passivation layer 161. The first passivation layer 161 covers both the upper surface and the side surfaces of the pixel defining layer 115. In addition, the second passivation layer 162 contacts the first passivation layer 161 and is formed outside the pixel defining layer 115.

Both the first passivation layer 161 and the second passivation layer 162 are formed in the non-display area NDA, and may include a metal, an inorganic material, or an organic material into which the material of the filler 130 does not diffuse.

The first passivation layer 161 may be made of the same material as the common electrode 157. The first passivation layer 161 may be integrally formed with the common electrode 157 while contacting the common electrode 157. For example, the common electrode 157 and the first passivation layer 161 may be simultaneously formed by enlarging an opening size of an opening mask used when depositing the common electrode 157.

The second passivation layer 162 is formed between the planarization layer 114 and the filler 130, outside the pixel defining layer 115. Both end portions of the second passivation layer 162 may overlap the pixel defining layer 115 and the getter 145. That is, the second passivation layer 162 may include one end portion overlapping the pixel defining layer 115, a central portion overlapping the filler 130, and the other end portion overlapping the getter 145.

The second passivation layer 162 may be made of the same material as the pixel electrode 155 and may be formed simultaneously with the pixel electrode 155. For example, the pixel electrode 155 and the second passivation layer 162 may be simultaneously formed by increasing the opening size of a deposition mask used when depositing the pixel electrode 155. Accordingly, a separate deposition mask for forming the second passivation layer 162 is not required, and a manufacturing process for forming the second passivation layer 162 is not increased.

When the pixel electrode 155 is formed of the translucent layer, the second passivation layer 162 may be formed of a plurality of layers of the first transparent layer 1621, the metal thin layer 1622, and the second transparent layer 1623, for example, a plurality of layers of ITO/Ag/ITO. The first transparent layer 1621 has excellent adhesion with the planarization layer 114, and the second transparent layer 1623 has excellent adhesion with the filler 130. Accordingly, the second passivation layer 162 may be firmly formed between the planarization layer 114 and the filler 130 without defects such as lift-off and delamination.

With the above configuration, the filler 130 contacts the first and second passivation layers 161 and 162 in the non-display area NDA, without contacting the pixel defining layer 115 and the planarization layer 114. The pixel defining layer 115, the planarization layer 114, and the filler 130 may all be made of a silicon-based polymer, and when the filler 130 contacts the pixel defining layer 115 and the planarization layer 114 including the same type of polymer, the materials are easily diffused.

For example, if it is assumed that the pixel defining layer 115 is formed wider than the filler 130 to contact the getter 145, the surface of the pixel defining layer 115, which is not covered by the common electrode 157, contacts the filler 130 in the non-display area NDA. In addition, if it is assumed that the second passivation layer 162 is not present in the structure of fig. 2, the filler 130 contacts the planarization layer 114.

In this case, various impurities, oxygen, and the like included in the filler 130 easily diffuse into the pixel defining layer 115 and the planarizing layer 114. In addition, impurities or oxygen diffused into the pixel defining layer 115 and the planarizing layer 114 infiltrate into the OLED, thereby causing deterioration in the OLED and defects such as pixel shrinkage.

However, according to some embodiments, the pixel defining layer 115 and the planarization layer 114 do not contact the filler 130 through the first and second passivation layers 161 and 162, and thus, the material may be prevented from being diffused from the filler 130 into the pixel defining layer 115 and the planarization layer 114. Therefore, according to the OLED display 100 according to the first exemplary embodiment, defects due to the filler 130, such as deterioration in the OLED and pixel shrinkage, may be suppressed.

Meanwhile, a wiring 170 for supplying an electric signal to the pixel PX may be located in the non-display area NDA. The wiring 170 may include a first metal layer 171 formed on the gate insulating layer 112 and a second metal layer 172 contacting the first metal layer 171 through an opening formed in the interlayer insulating layer 113. The first metal layer 171 may be made of the same material as the gate electrode 152, and the second metal layer 172 may be made of the same material as the source electrode 153 and the drain electrode 154.

The second metal layer 172 may include an end portion 172a protruding from the interlayer insulating layer 113 in a region overlapping the getter 145.

A third passivation layer 163 may be formed on an edge of the planarization layer 114 and into the getter 145. The third passivation layer 163 prevents defects such as lifting or delamination of the second metal layer 172 and the planarization layer 114 due to the protruding end portion 172a of the second metal layer 172. The third passivation layer 163 may be made of the same material as the pixel defining layer 115, and may be formed simultaneously with the pixel defining layer 115.

Fig. 3 is a partially enlarged cross-sectional view of the OLED display taken along line III-III of fig. 1.

Referring to fig. 3, if necessary, an opening 114a may be formed in the planarization layer 114 at a portion of the non-display area NDA that is not overlapped with the wiring. A surface of the interlayer insulating layer 113 is exposed by the opening 114a of the planarization layer 114, and a second passivation layer 162 is formed on the sidewall of the planarization layer 114 surrounding the opening 114a and on the exposed interlayer insulating layer 113.

The second passivation layer 162 made of the same material as the pixel electrode 155 has excellent adhesion to the interlayer insulating layer 113 and the filler 130. Accordingly, defects such as lift-off or delamination of the interlayer insulating layer 113 exposed by the opening 114a of the planarization layer 114 can be suppressed.

Fig. 4 is an enlarged cross-sectional view of an OLED display 200 according to a second exemplary embodiment.

Referring to fig. 4, the OLED display 200 includes a capping layer 158 formed on the common electrode 157, and the capping layer 158 may be made of the same material as the first passivation layer 161 a. The first passivation layer 161a may be integrally formed with the capping layer 158 while contacting the capping layer 158.

The capping layer 158 protects the OLED display and serves to optimize light efficiency through refractive index matching when the OLED display 200 is a top emission type. The capping layer 158 may include an organic material such as Alq3 (tris- (8-hydroxyquinoline) aluminum), α -NPD (N, N '-di- (naphthalene-1-yl) -N, N' -di (phenyl) benzidine), NPB (N, N '-di- (1-naphthyl) -N, N' -diphenyl-1, 1 '-biphenyl-4-4' -diamine), or CuPc (copper phthalocyanine).

The other components except the capping layer 158 and the first passivation layer 161a are the same as those of the first exemplary embodiment described above.

Fig. 5 is an enlarged cross-sectional view of an OLED display 300 according to a third exemplary embodiment.

Referring to fig. 5, the OLED display 300 includes a capping layer 158 formed on the common electrode 157, and a first passivation layer 161b and a second passivation layer 162b are made of the same material as the capping layer 158. The first passivation layer 161b may be integrally formed with the capping layer 158 while contacting the capping layer 158, and the second passivation layer 162b may be integrally formed with the first passivation layer 161b while contacting the first passivation layer 161 b. That is, the capping layer 158, the first passivation layer 161b, and the second passivation layer 162b may be formed of a single layer.

The other components except for the capping layer 158, the first passivation layer 161b, and the second passivation layer 162b are the same as those of the first exemplary embodiment described above.

While the present technology has been described in connection with exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.