1. A data driver, comprising:

a digital-to-analog converter configured to convert the image signal data into a plurality of data voltages; and

an output buffer unit including a plurality of channels for outputting the plurality of data voltages,

wherein the output buffer unit includes a plurality of output blocks,

wherein each of the plurality of output blocks includes at least one channel,

wherein a first data voltage output from a first output block of the plurality of output blocks is delayed to have a first time difference, an

Wherein a second data voltage output from a second output block of the plurality of output blocks is delayed to have a second time difference different from the first time difference.

2. The data driver of claim 1, further comprising a delay clock generation unit configured to receive a first reference clock and a second reference clock, the first reference clock determining a point in time when the first output block outputs the first data voltage, the second reference clock determining a point in time when the second output block outputs the second data voltage.

3. The data driver of claim 2, wherein the delay clock generation unit outputs a first delay clock signal by reflecting the delay information of the first output block to the first reference clock, and outputs a second delay clock signal by reflecting the delay information of the second output block to the second reference clock.

4. The data driver of claim 3, wherein two of the first delayed clock signals adjacent to each other have a first phase difference,

wherein two of the second delayed clock signals adjacent to each other have a second phase difference, an

Wherein the first phase difference is different from the second phase difference.

5. The data driver of claim 4, wherein the first output block outputs the first data voltage having the first time difference based on the first delayed clock signal, the first time difference corresponding to the first phase difference, an

Wherein the second output block outputs the second data voltage having the second time difference corresponding to the second phase difference based on the second delayed clock signal.

6. The data driver of claim 1, wherein the data voltages output from at least one of the plurality of output blocks have equal delay values.

7. A display device, comprising:

a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines;

a gate driver configured to generate a plurality of gate signals and apply the plurality of gate signals to the plurality of gate lines;

at least one data integrated circuit configured to generate a plurality of data voltages based on image signal data and apply the plurality of data voltages to the plurality of data lines; and

a signal controller configured to control the gate driver and the data integrated circuit and generate the image signal data based on image data,

wherein the data integrated circuit includes a plurality of output blocks connected to the plurality of data lines, and each of the plurality of output blocks includes at least one channel,

wherein a first data voltage output from a first output block of the plurality of output blocks is delayed to have a first time difference, an

Wherein a second data voltage output from a second output block of the plurality of output blocks is delayed to have a second time difference different from the first time difference.

8. The display device of claim 7, wherein the data integrated circuit comprises:

a digital-to-analog converter configured to convert the image signal data into the plurality of data voltages; and

an output buffer unit outputting the plurality of data voltages,

wherein the output buffer unit includes the plurality of output blocks.

9. The display device according to claim 8, wherein the data integrated circuit further comprises a delay clock generation unit configured to receive a first reference clock and a second reference clock, the first reference clock determining a point in time at which the first output block outputs the first data voltage, the second reference clock determining a point in time at which the second output block outputs the second data voltage.

10. The display device according to claim 9, wherein the delayed clock generation unit outputs a first delayed clock signal by reflecting delay information of the first output block to the first reference clock, and outputs a second delayed clock signal by reflecting delay information of the second output block to the second reference clock.

11. The display device according to claim 10, wherein two of the first delayed clock signals adjacent to each other have a first phase difference,

wherein two of the second delayed clock signals adjacent to each other have a second phase difference, an

Wherein the first phase difference is different from the second phase difference.

12. The display device according to claim 11, wherein the first output block outputs the first data voltage having the first time difference based on the first delayed clock signal, the first time difference corresponding to the first phase difference, and

wherein the second output block outputs the second data voltage having the second time difference corresponding to the second phase difference based on the second delayed clock signal.

13. The display device according to claim 9, wherein the signal controller comprises a reference clock generating unit configured to generate the first reference clock and the second reference clock and supply the generated first reference clock and the generated second reference clock to the delay clock generating unit.

14. The display device according to claim 7, further comprising a plurality of fanout lines connecting the plurality of data lines to the data integrated circuit,

the fan-out lines have equal line resistance.

15. The display device of claim 14, wherein the data voltages output from at least one of the plurality of output blocks have equal delay values.

16. The display device according to claim 7, wherein the gate driver comprises:

a first gate driving circuit connected to first ends of the plurality of gate lines; and

and a second gate driving circuit connected to second ends of the plurality of gate lines.

Background

The display device includes a display panel for displaying an image, and a data driver and a gate driver for driving the display panel. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels.

The data driver outputs a data driving signal to the data lines, and the gate driver outputs a gate driving signal for driving the gate lines. After the gate signal is applied to the pixel connected to the gate line, the display device may display an image using a data voltage corresponding to the display image.

Recently, with an increase in the size of display panels and adoption of high-speed driving methods, signal delay may occur on a transfer path of a gate signal output from a gate driver. In this case, the charging rate of the pixels positioned far from the gate driver may be lower than that of the pixels positioned near the gate driver. Therefore, there is a need to develop a new device and method for improving charging capability.

Disclosure of Invention

The present disclosure provides a data driver capable of improving a charging failure due to a signal delay.

The present disclosure also provides a display device having the above data driver.

An embodiment of the present disclosure provides a data driver including: a digital-to-analog converter configured to convert the image signal data into a plurality of data voltages; and an output buffer unit including a plurality of channels for outputting a plurality of data voltages. The output buffer unit includes a plurality of output blocks, and each of the plurality of output blocks includes at least one channel.

In an embodiment, a first data voltage output from a first output block of the plurality of output blocks is delayed to have a first time difference, and a second data voltage output from a second output block of the plurality of output blocks is delayed to have a second time difference, the second time difference being different from the first time difference.

In an embodiment of the present disclosure, a display device includes: a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines; a gate driver configured to generate and apply a plurality of gate signals to a plurality of gate lines; at least one data integrated circuit configured to generate a plurality of data voltages based on the image signal data and apply the plurality of data voltages to the plurality of data lines; and a signal controller configured to control the gate driver and the data integrated circuit, and generate image signal data based on the image data.

In an embodiment, the data integrated circuit includes a plurality of output blocks connected to the data lines, and each of the plurality of output blocks includes at least one channel.

In an embodiment, a first data voltage output from a first output block of the plurality of output blocks is delayed to have a first time difference, and a second data voltage output from a second output block of the plurality of output blocks is delayed to have a second time difference, the second time difference being different from the first time difference.

In an embodiment of the present disclosure, a display device includes: a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines; a gate driver configured to generate and apply a plurality of gate signals to a plurality of gate lines; and a plurality of data integrated circuits configured to generate a plurality of data voltages based on the image signal data and apply the plurality of data voltages to the plurality of data lines.

In an embodiment, each of the plurality of data integrated circuits includes a plurality of output blocks connected to the plurality of data lines, and the first data voltages output from at least one first output block of a first data integrated circuit among the plurality of data integrated circuits have equal first delay values.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

fig. 1 is a block diagram of a display device according to an embodiment of the present disclosure;

fig. 2 is a plan view of a display device according to an embodiment of the present disclosure;

fig. 3 is an enlarged plan view of the first data integrated circuit and the display panel of part a1 in fig. 2;

FIG. 4 is an internal block diagram of the first data integrated circuit shown in FIG. 3;

fig. 5 is a block diagram specifically illustrating a delay clock generating unit and an output buffer unit shown in fig. 4;

fig. 6A is a waveform diagram illustrating the first, second, third, and fourth reference clocks and the first, second, third, and fourth delayed clock blocks shown in fig. 5;

fig. 6B is a waveform diagram illustrating output time points of data voltages of the first, second, third, and fourth blocks shown in fig. 5;

fig. 6C is a waveform diagram illustrating output time points of data voltages of first, second, third, and fourth blocks according to another embodiment;

fig. 7 is a plan view of a display device according to an embodiment of the present disclosure;

fig. 8 is an enlarged plan view of the first data integrated circuit and the display panel of part a2 in fig. 7;

fig. 9 is a waveform diagram showing output time points of data voltages of the first block, the second block, the third block, and the fourth block applied to the data lines of the first block, the second block, the third block, and the fourth block shown in fig. 8;

fig. 10 is an enlarged plan view of a fourth data integrated circuit and a display panel of part a3 in fig. 7;

fig. 11 is a waveform diagram showing output time points of data voltages of the first block, the second block, the third block, and the fourth block applied to the data lines of the first block, the second block, the third block, and the fourth block shown in fig. 10;

fig. 12 is a plan view of a display device according to an embodiment of the present disclosure;

fig. 13 is an enlarged plan view of the second data integrated circuit, the third data integrated circuit, and the fourth data integrated circuit and the display panel of part a4 in fig. 12;

fig. 14 is a waveform diagram illustrating output time points of data voltages applied to data lines disposed in the first, second, and third driving regions illustrated in fig. 13;

fig. 15 is an enlarged plan view of a first data integrated circuit and a display panel according to another embodiment of part a1 in fig. 2; and

fig. 16 is a waveform diagram showing output time points of data voltages of the first block, the second block, the third block, the fourth block, the fifth block, the sixth block, the seventh block, and the eighth block, which are applied to the data lines of the first block, the second block, the third block, the fourth block, the fifth block, the sixth block, the seventh block, and the eighth block shown in fig. 15.

Detailed Description

In this specification, when an element (or a region, layer, portion, etc.) is referred to as being "on," "connected to," or "combined with" another element, it means that the element may be directly on, connected to, or combined with the other element or that a third element may be present therebetween.

Like reference numerals refer to like elements. In addition, the thickness, scale and size of the components are exaggerated in the drawings for effective description.

"and/or" includes all of the one or more combinations defined by the associated elements.

It will be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The above terms are only used to distinguish one element from another. For example, a first component could be termed a second component, and a second component could be termed a first component, without departing from the scope of the present disclosure. Unless otherwise indicated, terms in the singular may include the plural.

Further, terms such as "below", "lower", "upper", and "upper" are used to describe the relationship of the configurations shown in the drawings. These terms are described as relative concepts based on the directions shown in the drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In general, terms defined in dictionaries should be considered to have the same meaning as in the context of the relevant art, and should not be interpreted abnormally or should not be interpreted to have an excessively formal meaning unless explicitly defined herein.

In various embodiments of the present disclosure, the terms "comprises," "comprising," "includes" or "including" specify the presence of stated features, regions, quantities, steps, processes, elements, and/or components, but do not preclude the presence or addition of other features, regions, quantities, steps, processes, elements, and/or components.

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

Fig. 1 is a block diagram of a display device according to an embodiment of the present disclosure.

Referring to fig. 1, the display device 1000 includes a signal controller 100, a gate driver 200, a data driver 400, and a display panel 500.

The display panel 500 includes a plurality of pixels PX connected to a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn, and displays an image based on output image data R 'G' B '(also referred to as image data signals R' G 'B'). The plurality of gate lines GL1 to GLm extend in a first direction DR1, and the plurality of data lines DL1 to DLn extend in a second direction DR2 intersecting the first direction DR 1. The plurality of pixels PX are arranged in a matrix form, and each of the plurality of pixels PX may be electrically connected to one of the plurality of gate lines GL1 to GLm and one of the plurality of data lines DL1 to DLn.

The signal controller 100 controls the operations of the gate driver 200 and the data driver 400. The signal controller 100 receives input image data RGB and input control signals CONT from an external device (e.g., a host). The input image data RGB may include red gray data R, green gray data G, and blue gray data B for each of the pixels PX. The input control signals CONT may include a main clock signal, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal.

The signal controller 100 generates an image data signal R ' G ' B ', a gate control signal GCS, and a data control signal DCS based on the input image data RGB and the input control signal CONT.

Specifically, the signal controller 100 may generate an image data signal R 'G' B 'based on the input image data RGB and supply the generated image data signal R' G 'B' to the data driver 400. The image data signal R ' G ' B ' may be corrected image data generated by correcting the input image data RGB. According to an embodiment, the signal controller 100 may perform image quality correction, spot correction, color characteristic compensation, and/or active capacitance compensation on the input image data RGB.

Further, the signal controller 100 may generate a gate control signal GCS for controlling the operation of the gate driver 200 based on the input control signal CONT and supply the generated gate control signal GCS to the gate driver 200. The gate control signal GCS may include a vertical start signal and a gate clock signal. The signal controller 100 may generate a data control signal DCS for controlling the operation of the data driver 400 based on the input control signal CONT and supply the generated data control signal DCS to the data driver 400. The data control signal DCS may include a horizontal start signal, a data clock signal, a data load signal, a polarity control signal, and an output control signal.

The gate driver 200 generates gate signals for driving the plurality of gate lines GL1 to GLm based on the gate control signal GCS. The gate driver 200 may sequentially apply gate signals to the plurality of gate lines GL1 to GLm. Accordingly, the plurality of pixels PX may be sequentially driven in units of pixels connected to the same gate line (i.e., pixel row units).

The data driver 400 receives the data control signal DCS and the image data signal R ' G ' B ' from the signal controller 100. The data driver 400 generates an analog data voltage based on the data control signal DCS and the digital image data signal R ' G ' B '. The data driver 400 may sequentially apply the data voltages to the plurality of data lines DL1 to DLn.

According to an embodiment, the gate driver 200 and/or the data driver 400 are mounted on the display panel 500 in the form of a chip, or may be connected to the display panel 500 in the form of a Tape Carrier Package (TCP) or a Chip On Film (COF). According to this embodiment, the gate driver 200 and/or the data driver 400 may be integrated in the display panel 500.

The gate driver 200 is disposed on one or both sides of the display panel 500 to sequentially apply gate signals to the gate lines GL1 to GLm. Fig. 1 illustrates a structure in which the gate driver 200 is connected to one ends of the gate lines GL1 to GLm on the display panel 500 side. However, the present disclosure is not limited thereto, and the display device 1000 may have a dual gate structure in which the gate driver 200 is connected to both sides of the gate lines GL1 to GLm.

Fig. 2 is a plan view of a display device according to an embodiment of the present disclosure.

Referring to fig. 2, in a display device 1000 according to an embodiment of the present disclosure, a gate driver 200 includes a first gate driving circuit 210 and a second gate driving circuit 220. The first gate driving circuit 210 is connected to a first end of each of the gate lines GL1 through GLm, and the second gate driving circuit 220 is connected to a second end of each of the gate lines GL1 through GLm.

Each of the first and second gate driving circuits 210 and 220 may include a shift register that sequentially outputs gate signals. The first gate driving circuit 210 and the second gate driving circuit 220 may operate simultaneously to output gate signals to the same gate line at the same time. Accordingly, each of the gate lines GL1 to GLm may receive gate signals from the first and second gate driving circuits 210 and 220 through the first and second terminals.

Here, the gate signal output from the first gate driving circuit 210 may be delayed toward the center from a first end of each of the gate lines GL1 to GLm, and the gate signal output from the second gate driving circuit 220 may be delayed toward the center from a second end of each of the gate lines GL1 to GLm. Specifically, a difference occurs between a time point at which the gate signal reaches the pixel adjacent to the first end of each gate line and a time point (hereinafter, on time point) at which the gate signal reaches the pixel adjacent to the center (for example, the (j +1) th pixel PXj + 1).

For example, a point of time at which a pixel (hereinafter, the first pixel PX1) connected to the first gate line GL1 and the first data line DL1 is turned on in response to the first gate signal may be different from a point of time at which a pixel (hereinafter, the (j +1) th pixel PXj +1) connected to the first gate line GL1 and the (j +1) th data line DLj +1 is turned on in response to the first gate signal. That is, the turn-on time point of the (j +1) th pixel PXj +1 may be delayed from the turn-on time point of the first pixel PX1 by a predetermined time. The delay time of the gate signal may vary according to the line resistance of each gate line.

As described above, the on time between pixels may be deviated according to the position according to the line resistance of each gate line. Further, when a deviation occurs in the turn-on time between pixels included in the same pixel row, there may occur a problem that the charging rate of the pixels that are turned on relatively slowly is lowered.

In order to improve the charging rate reduction problem, the data driver 400 may adjust a time point at which the data voltage is output in consideration of a line resistance of each gate line.

Referring to fig. 2, the data driver 400 may include a first data integrated circuit 410 and a second data integrated circuit 420. In fig. 2, the data driver 400 is illustrated to have a structure including two data integrated circuits 410 and 420, but the present disclosure is not limited thereto. That is, the data driver 400 may include three or more data integrated circuits or one data integrated circuit.

According to an embodiment, the display device 1000 may further include flexible circuit boards 310 and 320 and a printed circuit board 370 electrically connected to the flexible circuit boards 310 and 320, and the data integrated circuits 410 and 420 are mounted in the flexible circuit boards 310 and 320 in a TCP manner. Specifically, the display device 1000 includes a first flexible circuit board 310 on which a first data integrated circuit 410 is mounted and a second flexible circuit board 320 on which a second data integrated circuit 420 is mounted.

The first and second flexible circuit boards 310 and 320 electrically connect the display panel 500 and the printed circuit board 370 and are disposed between the display panel 500 and the printed circuit board 370. Specifically, one end of each of the first and second flexible circuit boards 310 and 320 may be coupled to the printed circuit board 370, and the other end of each of the first and second flexible circuit boards 310 and 320 may be coupled to the display panel 500.

The display panel 500 includes a display area DA displaying an image and a non-display area NDA adjacent to a periphery of the display area DA.

The display panel 500 may include a plurality of pixels PX1 to PXj +1 disposed in the display area DA. In addition, the display panel 500 includes gate lines GL1 to GLm and data lines DL1 to DLj and DLj +1 to DLn insulated from the gate lines GL1 to GLm and intersecting the gate lines GL1 to GLm.

In this case, the first and second flexible circuit boards 310 and 320 may be connected to a portion of the non-display area NDA of the display panel 500 adjacent to the printed circuit board 370. Although not shown in the drawings, the data integrated circuits 410 and 420 may be directly mounted on the non-display area NDA of the display panel 500 in a Chip On Glass (COG) method.

The first data integrated circuit 410 may be connected to a first group of data lines DL1 to DLj among the data lines DL1 to DLj and DLj +1 to DLn, and the second data integrated circuit 420 may be connected to a second group of data lines DLj +1 to DLn among the data lines DL1 to DLj and DLj +1 to DLn. Here, j may be a number 1/2 corresponding to n. Here, the display region DA may include a first driving region DDA1 and a second driving region DDA2, the first group of data lines DL1 to DLj being disposed in the first driving region DDA1, and the second group of data lines DLj +1 to DLn being disposed in the second driving region DDA 2. The pixels disposed in the first driving region DDA1 may be driven by the first data integrated circuit 410, and the pixels disposed in the second driving region DDA2 may be driven by the second data integrated circuit 420.

Fig. 3 is an enlarged plan view of the first data integrated circuit and the display panel of part a1 in fig. 2. Fig. 4 is an internal block diagram of the first data integrated circuit shown in fig. 3.

Referring to fig. 3, the first driving region DDA1 in which a first group of data lines DL1 through DLj (hereinafter, a first data line group) is disposed may be divided into a plurality of block regions. As an example of the present disclosure, the first driving region DDA1 may include four block regions (hereinafter, a first block region BA1, a second block region BA2, a third block region BA3, and a fourth block region BA 4). However, the number of block regions included in the first driving region DDA1 is not limited thereto. For example, the first driving region DDA1 may include three or more block regions.

The first data line group DL1 to DLj may be divided into a plurality of blocks arranged to correspond to a plurality of block regions, respectively. As an example of the present disclosure, the first data line group DL1 to DLj includes data lines of a first block (hereinafter, first data line blocks DLa1 to DLak), data lines of a second block (hereinafter, second data line blocks DLb1 to DLbk), data lines of a third block (hereinafter, third data line blocks DLc1 to DLck), and data lines of a fourth block (hereinafter, fourth data line blocks DLd1 to DLdk). The first data line blocks DLa1 to DLak are disposed in the first block area BA1, and the second data line blocks DLb1 to DLbk are disposed in the second block area BA 2. The third data line blocks DLc1 to DLck are disposed in the third block area BA3, and the fourth data line blocks DLd1 to DLdk are disposed in the fourth block area BA 4.

The first data line group DL1 to DLj is connected to the first data integrated circuit 410 through a first group of fan-out lines FL1 to FLj (hereinafter, referred to as a first fan-out line group). As an example of the present disclosure, the first fan-out line groups FL1 to FLj may have different line resistances. Therefore, even if the data voltages are simultaneously output from the first data integrated circuits 410, the time points at which the data voltages arrive at the first data line group DL1 to DLj may be different from each other while passing through the first fan-out line groups FL1 to FLj having different line resistances.

As described above, when the first fan-out line groups FL1 to FLj have different line resistances, the first data integrated circuit 410 may adjust a time point at which the data voltage is output in consideration of the line resistance of each gate line and the line resistance of each of the first fan-out line groups FL1 to FLj.

Referring to fig. 4, the first data integrated circuit 410 includes a shift register 411, a latch unit 412, a digital-to-analog converter 413, and an output buffer unit 415.

The shift register 411 sequentially activates the plurality of latch clock signals CK1 through CKn based on the horizontal start signal STH and the data clock signal DCK. The horizontal start signal STH and the data clock signal DCK may be signals included in the data control signal DCS (shown in fig. 1) supplied from the signal controller 100 (shown in fig. 1).

The latch unit 412 latches the image data signal R ' G ' B ' in response to the latch clock signals CK1 to CKn supplied from the shift register 411. According to an embodiment, the latch unit 412 may simultaneously output the latched image data signals R 'G' B 'to the digital-to-analog converter 413 based on the data load signal TP, or may supply the latched image data signals R' G 'B' to the digital-to-analog converter 413 with a predetermined time difference. The data load signal TP may be a signal included in the data control signal DCS. According to an embodiment, the latched image data signals R ' G ' B ' are defined as digital image signals D _ D1 to D _ Dn.

The digital-to-analog converter 413 receives the digital image signals D _ D1 to D _ Dn from the latch unit 412. The digital-to-analog converter 413 converts the received digital image signals D _ D1 to D _ Dn into data voltages D _ a1 to D _ An having An analog form. Further, although not shown in the drawings, a plurality of gamma voltages from an external source may be supplied to the digital-to-analog converter 413. The digital-to-analog converter 413 may output data voltages D _ a1 to D _ An corresponding to the digital image signals D _ D1 to D _ Dn based on the gamma voltages. The data voltages D _ a1 to D _ An may have a positive polarity or a negative polarity by the polarity control signal POL supplied to the digital-to-analog converter 413. The polarity control signal POL may be a signal included in the data control signal DCS. Here, the data voltage having the positive polarity may be a voltage having a level higher than the reference voltage, and the data voltage having the negative polarity may be a voltage having a level lower than the reference voltage.

The data voltages D _ a1 to D _ An generated from the digital-to-analog converter 413 are supplied to the output buffer unit 415. The output buffer unit 415 may be divided into a plurality of output blocks including one or more output buffers. As an example of the present disclosure, the output buffer unit 415 may include four output blocks (hereinafter, referred to as a first output block 415a, a second output block 415b, a third output block 415c, and a fourth output block 415 d). However, the number of output blocks included in the output buffer unit 415 is not limited thereto. For example, the output buffer unit 415 may include less or more than four output blocks.

The first data integrated circuit 410 may further include a delay clock generation unit 416. The delay clock generation unit 416 may generate a plurality of delay clocks DCLKa, DCLKb, DCLKc, and DCLKd by reflecting delay information of each of the plurality of output blocks 415a, 415b, 415c, and 415d in the preset reference clock RCLK. Here, the plurality of delay clocks DCLKa, DCLKb, DCLKc, and DCLKd include a delay clock DCLKa (hereinafter, referred to as a first delay clock block) provided to the first block of the first output block 415a, a delay clock DCLKb (hereinafter, referred to as a second delay clock block) provided to the second block of the second output block 415b, a delay clock DCLKc (hereinafter, referred to as a third delay clock block) provided to the third block of the third output block 415c, and a delay clock DCLKd (hereinafter, referred to as a fourth delay clock block) provided to the fourth block of the fourth output block 415 d.

The delay information of each of the first, second, third, and fourth output blocks 415a, 415b, 415c, and 415d may be stored in the delay clock generation unit 416 or may be provided from an external circuit such as the signal controller 100.

The output buffer unit 415 receives the first delay clock block DCLKa, the second delay clock block DCLKb, the third delay clock block DCLKc, and the fourth delay clock block DCLKd from the delay clock generation unit 416. Specifically, the first output block 415a outputs the data voltages Da1 to Dak of the first block to the first data line blocks DLa1 to DLak (see fig. 3) in synchronization with the first delay clock block DCLKa. The second output block 415b outputs the data voltages Db1 through Dbk of the second block to the second data line blocks DLb1 through DLbk (see fig. 3) in synchronization with the second delay clock block DCLKb. The third output block 415c outputs the data voltages Dc1 to Dck of the third block to the third data line blocks DLc1 to DLck (see fig. 3) in synchronization with the third delay clock block DCLKc. The fourth output block 415d outputs the data voltages Dd1 to Ddk of the fourth block to the fourth data line blocks DLd1 to DLdk (see fig. 3) in synchronization with the fourth delay clock block DCLKd.

Each of the first to fourth output blocks 415a to 415d includes first to k-th channels CH1 to CHk and outputs a corresponding data voltage through the first to k-th channels CH1 to CHk. That is, each of the output blocks 415a to 415d may determine a point of time at which the data voltage is output from the first channel CH1 to the k-th channel CHk, respectively, in response to the corresponding delay clock block.

Fig. 5 is a block diagram specifically illustrating the delay clock generating unit and the output buffer unit shown in fig. 4. Fig. 6A is a waveform diagram illustrating first to fourth reference clocks and first to fourth delay clock blocks shown in fig. 5, and fig. 6B is a waveform diagram illustrating output time points of data voltages of the first to fourth blocks shown in fig. 5.

Referring to fig. 5, the signal controller 100 (shown in fig. 1) may include a reference clock generation unit 110. The reference clock generation unit 110 reflects the delay information of each of the output blocks 415a to 415d in the data clock signal DCK (shown in fig. 4) to generate reference clocks RCLK1, RCLK2, RCLK3, and RCLK4 for controlling delay values of the data voltages Dd1 to Ddk output from each of the output blocks 415a to 415 d. The reference clocks RCLK shown in fig. 4 may include the above-described reference clocks RCLK1, RCLK2, RCLK3, and RCLK 4.

When the first data integrated circuit 410 (shown in fig. 4) includes the first, second, third and fourth output blocks 415a, 415b, 415c and 415d, the reference clock generating unit 110 may generate and provide the first, second, third and fourth reference clocks RCLK1, 2, 3 and 4 to the first data integrated circuit 410. The first data integrated circuit 410 may independently control delay values of the first, second, third, and fourth output blocks 415a, 415b, 415c, and 415d based on the first, second, third, and fourth reference clocks RCLK1, RCLK2, RCLK3, and RCLK 4.

In fig. 5, a structure in which the reference clock generating unit 110 is included in the signal controller 100 is shown, but the present disclosure is not limited thereto. For example, the reference clock generating unit 110 may be provided in each of the data integrated circuits 410 and 420 (shown in fig. 2) provided in the display device 1000.

When the output buffer unit 415 of the first data integrated circuit 410 (shown in fig. 4) includes the first output block 415a, the second output block 415b, the third output block 415c, and the fourth output block 415d, the delay clock generation unit 416 may include a first delay clock generation unit 416a, a second delay clock generation unit 416b, a third delay clock generation unit 416c, and a fourth delay clock generation unit 416 d. The first delayed clock generation unit 416a receives the first reference clock RCLK1 from the reference clock generation unit 110. The first delay clock generation unit 416a may generate the first delay clock blocks DCLKa _1 to DCLKa _ k by reflecting delay information of each channel of the first output block 415a in the first reference clock RCLK 1. The first delay clock blocks DCLKa _1 to DCLKa _ k may include first to kth delay clock signals DCLKa _1 to DCLKa _ k in which delay information of the first to kth channels CH1 to CHk of the first output block 415a is reflected, respectively.

As shown in fig. 5, 6A and 6B, the first reference clock RCLK1 may be activated from a fourth time point t4 to a fifth time point t5, the fourth time point t4 being delayed by a fourth time from a reference time point t0, the fifth time point t5 being delayed by a fifth time from a reference time point t 0. That is, the first reference clock RCLK1 may be activated at a fourth time point t4 during the first time period 1 t. The kth delayed clock signal DCLKa _ k of the first to kth delayed clock signals DCLKa _1 to DCLKa _ k may be first activated at a rising time point of the first reference clock RCLK 1. That is, the first to k-th delayed clock signals DCLKa _1 to DCLKa _ k may be sequentially activated from the k-th to first delayed clock signals DCLKa _ k to DCLKa _ 1. The first to k-th delayed clock signals DCLKa _1 to DCLKa _ k may have a first phase difference from each other. Specifically, the kth delayed clock signal DCLKa _ k and the (k-1) th delayed clock signal DCLKa _ k-1 adjacent to each other have a phase difference obtained by dividing the first time period 1t by the number of channels k. That is, "1 t/k" may be defined as the first phase difference.

The first output block 415a receives a first group of data voltages D _ Aa1 to D _ Aak among the data voltages D _ a1 to D _ An generated from the digital-to-analog converter 413. The first output block 415a reflects delay information in the first group of data voltages D _ Aa1 through D _ Aak based on the first through k-th delayed clock signals DCLKa _1 through DCLKa _ k to output the data voltages Da1 through Dak of the first block.

Referring to fig. 5, 6A, and 6B, the second delayed clock generation unit 416B receives the second reference clock RCLK2 from the reference clock generation unit 110. The second delay clock generating unit 416b may generate the second delay clock blocks DCLKb _1 to DCLKb _ k by reflecting delay information of each channel of the second output block 415b in the second reference clock RCLK 2. The second delay clock blocks DCLKb _1 to DCLKb _ k may include first to kth delay clock signals DCLKb _1 to DCLKb _ k in which delay information of the first to kth channels CH1 to CHk of the second output block 415b is reflected, respectively.

The second reference clock RCLK2 may be activated from a first time point t1 to a fourth time point t4, the first time point t1 being delayed by a first time from a reference time point t 0. That is, the second reference clock RCLK2 may be activated at the first time point t1 during the second time period 3 t. The kth delayed clock signal DCLKb _ k of the first to kth delayed clock signals DCLKb _1 to DCLKb _ k may be first activated at a rising time point of the second reference clock RCLK 2. That is, the first to k-th delayed clock signals DCLKb _1 to DCLKb _ k may be sequentially activated from the k-th to first delayed clock signals DCLKb _ k to DCLKb _ 1. The first to k-th delayed clock signals DCLKb _1 to DCLKb _ k may have a second phase difference from each other. Specifically, the kth delayed clock signal DCLKb _ k and the (k-1) th delayed clock signal DCLKb _ k-1 adjacent to each other have a phase difference obtained by dividing the second time period 3t by the channel number k. That is, "3 t/k" may be defined as the second phase difference.

The second output block 415b receives the second group of data voltages D _ Ab1 to D _ Abk among the data voltages D _ a1 to D _ An generated from the digital-to-analog converter 413. The second output block 415b reflects delay information in the second group data voltages D _ Ab1 through D _ Abk based on the first through k-th delayed clock signals DCLKb _1 through DCLKb _ k to output the data voltages Db1 through Dbk of the second block.

Still referring to fig. 5, 6A, and 6B, the third delayed clock generation unit 416c receives the third reference clock RCLK3 from the reference clock generation unit 110. The third delay clock generating unit 416c may generate the third delay clock blocks DCLKc _1 to DCLKc _ k by reflecting the delay information of each channel of the third output block 415c in the third reference clock RCLK 3. The third delay clock blocks DCLKc _1 to DCLKc _ k may include first to kth delay clock signals DCLKc _1 to DCLKc _ k in which delay information of the first to kth channels CH1 to CHk of the third output block 415c is reflected, respectively.

The third reference clock RCLK3 may be activated from the first time point t1 to a second time point t2, the second time point t2 being delayed from the reference time point t0 by a second time. That is, the third reference clock RCLK3 may be activated at the first time point t1 during the third time period 1 t. The first delayed clock signal DCLKc _1 of the first to k-th delayed clock signals DCLKc _1 to DCLKc _ k may be first activated at a rising time point of the third reference clock RCLK 3. That is, the first to k-th delayed clock signals DCLKc _1 to DCLKc _ k may be sequentially activated from the first to k-th delayed clock signals DCLKc _1 to DCLKc _ k. The first to k-th delayed clock signals DCLKc _1 to DCLKc _ k may have a third phase difference from each other. Specifically, the first delayed clock signal DCLKc _1 and the second delayed clock signal DCLKc _2 adjacent to each other have a phase difference obtained by dividing the third time period 1t by the channel number k. That is, "1 t/k" may be defined as the third phase difference.

The third output block 415c receives the third group of data voltages D _ Ac1 to D _ Ack among the data voltages D _ a1 to D _ An generated from the digital-to-analog converter 413. The third output block 415c reflects delay information in the third group of data voltages D _ Ac1 through D _ Ack based on the first through k-th delayed clock signals DCLKc _1 through DCLKc _ k to output the data voltages Dc1 through Dck of the third block.

Still referring to fig. 5, 6A, and 6B, the fourth delayed clock generation unit 416d receives the fourth reference clock RCLK4 from the reference clock generation unit 110. The fourth delay clock generating unit 416d may generate the fourth delay clock blocks DCLKd _1 to DCLKd _ k by reflecting the delay information of each channel of the fourth output block 415d in the fourth reference clock RCLK 4. The fourth delay clock blocks DCLKd _1 to DCLKd _ k may include first to kth delay clock signals DCLKd _1 to DCLKd _ k in which delay information of the first to kth channels CH1 to CHk of the fourth output block 415d is reflected, respectively.

The fourth reference clock RCLK4 may be activated from a second time point t2 to a fifth time point t5, the second time point t2 being delayed from the reference time point t0 by a second time. That is, the fourth reference clock RCLK4 may be activated at the second time point t2 during the fourth time period 3 t. The first delayed clock signal DCLKd _1 of the first to k-th delayed clock signals DCLKd _1 to DCLKd _ k may be first activated at a rising time point of the fourth reference clock RCLK 4. That is, the first to k-th delayed clock signals DCLKd _1 to DCLKd _ k may be sequentially activated from the first to k-th delayed clock signals DCLKd _1 to DCLKd _ k. The first to k-th delayed clock signals DCLKd _1 to DCLKd _ k may have a fourth phase difference from each other. Specifically, the first delayed clock signal DCLKd _1 and the second delayed clock signal DCLKd _2 adjacent to each other have a phase difference obtained by dividing the fourth time period 3t by the channel number k. That is, "3 t/k" may be defined as the fourth phase difference.

The fourth output block 415D receives fourth group data voltages D _ Ad1 to D _ ack among the data voltages D _ a1 to D _ An generated from the digital-to-analog converter 413. The fourth output block 415D reflects delay information in the fourth group of data voltages D _ Ad1 through D _ ack based on the first through k-th delayed clock signals DCLKd _1 through DCLKd _ k to output the data voltages Dd1 through Ddk of the fourth block.

As shown in fig. 3, 4, 6A, and 6B, the data voltages Da1 through Dak of the first block, which are respectively output from the first channel CH1 through the k-th channel CHk of the first output block 415a, are supplied to the first data line blocks DLa1 through DLak disposed in the first block area BA 1. The data voltages Db1 to Dbk of the second block, which are output from the first channel CH1 to the k-th channel CHk of the second output block 415b, are supplied to the second data line blocks DLb1 to DLbk disposed in the second block area BA 2. Here, the data voltages Da1 to Dak of the first block have a first time difference (1t/k) at the fourth time point t4, and are sequentially delayed from the k-th data voltage Dak to the first data voltage Da 1. On the other hand, the data voltages Db1 to Dbk of the second block have a second time difference (3t/k) at the first time point t1, and are sequentially delayed from the kth data voltage Dbk to the first data voltage Db 1.

Also, the data voltages Dc1 to Dck of the third block, which are output from the first to k-th channels CH1 to CHk of the third output block 415c, are supplied to the third data line blocks DLc1 to DLck provided in the third block area BA 3. The data voltages Dd1 to Ddk of the fourth block, which are output from the first channel CH1 to the k-th channel CHk of the fourth output block 415d, are supplied to the fourth data line blocks DLd1 to DLdk arranged in the fourth block area BA 4. Here, the data voltages Dc1 to Dck of the third block have a third time difference (1t/k) at the first time point t1, and are sequentially delayed from the first data voltage Dc1 to the kth data voltage Dck. On the other hand, the data voltages Dd1 through Ddk of the fourth block have a fourth time difference (3t/k) at the second time point t2, and are sequentially delayed from the first data voltage Dd1 through the k-th data voltage Ddk.

Thus, the delay value of the data voltage output from one data integrated circuit may be different for each block. That is, the delay value of the data line is not determined by one variable but is determined by reflecting all relevant design factors such as a length difference of the fanout line, a distance from the gate driving circuit, and the number and position of the gate driving circuits. Therefore, there may be a case where the delay value of the data voltage must be set differently for each block. As described above, by controlling the delay value of the data voltage in units of blocks, the delay value can be finely adjusted. As a result, the deviation of the charging rate between the pixels can be effectively reduced.

Fig. 6B illustrates that the output waveforms of the data voltage of the first block to the data voltage of the fourth block have an inverted V shape as an example of the present disclosure. For example, due to the length difference between the first fan-out line groups FL1 to FLj (shown in fig. 3), the degree to which the data voltages are delayed is large, and when the degree to which the gate signals are delayed is relatively small, the delay values of the data voltages output from the data integrated circuits 410 and 420 may be set according to the length difference between the first fan-out line groups FL1 to FLj. That is, the output waveforms of the data voltages of the first to fourth blocks may be set in an inverted V shape in which the delay values of the data voltages decrease toward the centers of the first fan-out line groups FL1 to FLj. However, the shapes of the output waveforms of the data voltages of the first to fourth blocks are not limited thereto. That is, the shapes of the output waveforms of the data voltages of the first to fourth blocks may be varied in various forms according to the mounting positions of the data integrated circuits 410 and 420, the types of the first fan-out line groups FL1 to FLj, or the delay degrees of the gate signals.

Fig. 6C is a waveform diagram illustrating output time points of data voltages of first to fourth blocks according to another embodiment of the present disclosure.

Referring to fig. 3, 4, 5, and 6C, the data voltages Da1 through Dak of the first block, which are output from the first channel CH1 through the k-th channel CHk of the first output block 415a, are supplied to the first data line blocks DLa1 through DLak disposed in the first block area BA 1. The data voltages Db1 to Dbk of the second block, which are output from the first channel CH1 to the k-th channel CHk of the second output block 415b, are supplied to the second data line blocks DLb1 to DLbk disposed in the second block area BA 2. Here, the data voltages Da1 to Dak of the first block have a first time difference (1t/k) at a first time point t1, and are sequentially delayed from the first data voltage Da1 to the kth data voltage Dak. On the other hand, the data voltages Db1 to Dbk of the second block have a second time difference (3t/k) at a second time point t2, and are sequentially delayed from the first data voltage Db1 to the kth data voltage Dbk.

Also, the data voltages Dc1 to Dck of the third block, which are output from the first to k-th channels CH1 to CHk of the third output block 415c, are supplied to the third data line blocks DLc1 to DLck provided in the third block area BA 3. The data voltages Dd1 to Ddk of the fourth block, which are output from the first channel CH1 to the k-th channel CHk of the fourth output block 415d, are supplied to the fourth data line blocks DLd1 to DLdk arranged in the fourth block area BA 4. Here, the data voltages Dc1 to Dck of the third block have a third time difference (1t/k) at a fourth time point t4, and are sequentially delayed from the kth data voltage Dck to the first data voltage Dc 1. On the other hand, the data voltages Dd1 to Ddk of the fourth block have a fourth time difference (3t/k) at the first time point t1, and are sequentially delayed from the k-th data voltage Ddk to the first data voltage Dd 1.

Fig. 6C illustrates that the output waveforms of the data voltage of the first block to the data voltage of the fourth block have a V shape as an example of the present disclosure. For example, when the first fan-out line groups FL1 to FLj (shown in fig. 3) have the same length, the degree of delay of the data voltage due to the length difference between the fan-out lines may be negligibly small. At this time, if the first and second gate driving circuits are respectively disposed at both ends of the gate lines, the output waveforms of the data voltage of the first to fourth blocks of the data integrated circuits of any one of the data integrated circuits may be disposed in a V shape in which the delay value of the data voltage increases as it goes toward the center of the first fan-out line groups FL1 to FLj.

Fig. 7 is a plan view of a display device according to an embodiment of the present disclosure. Fig. 8 is an enlarged plan view of the first data integrated circuit and the display panel shown in part a2 of fig. 7, and fig. 9 is a waveform diagram showing output time points of data voltages of the first block to the fourth block, which are applied to data lines of the first block to data lines of the fourth block shown in fig. 8. Fig. 10 is an enlarged plan view of the fourth data integrated circuit and the display panel shown in part a3 of fig. 7, and fig. 11 is a waveform diagram showing output time points of data voltages of the first block to the fourth block, which are applied to the data lines of the first block to the data lines of the fourth block shown in fig. 10.

Referring to fig. 7, the data driver 400 (referring to fig. 1) may include a first data integrated circuit 410, a second data integrated circuit 420, a third data integrated circuit 430, and a fourth data integrated circuit 440. In fig. 7, the data driver 400 is shown to have a structure including four data integrated circuits 410 to 440, but the present disclosure is not limited thereto.

According to an embodiment, the display device 1000 may further include flexible circuit boards 310 to 340 and a printed circuit board 370 electrically connected to the flexible circuit boards 310 to 340, and the data integrated circuits 410 to 440 are mounted in the flexible circuit boards 310 to 340 in a TCP (tape carrier package) manner. Specifically, the display device 1000 may include a first flexible circuit board 310 on which a first data integrated circuit 410 is mounted, a second flexible circuit board 320 on which a second data integrated circuit 420 is mounted, a third flexible circuit board 330 on which a third data integrated circuit 430 is mounted, and a fourth flexible circuit board 340 on which a fourth data integrated circuit 440 is mounted.

The first to fourth flexible circuit boards 310 to 340 electrically connect the display panel 500 and the printed circuit board 370 and are disposed between the display panel 500 and the printed circuit board 370.

The first data integrated circuit 410 may be connected to a first group of data lines among the data lines DL1 through DLn, and the second data integrated circuit 420 may be connected to a second group of data lines among the data lines DL1 through DLn. The third data integrated circuit 430 may be connected to a third group of the data lines DL1 through DLn, and the fourth data integrated circuit 440 may be connected to a fourth group of the data lines DL1 through DLn.

Here, the display area DA may include first to fourth driving areas DDA1 to DDA4 driven by the first to fourth data integrated circuits 410 to 440, respectively. The first group of data lines is disposed in the first driving region DDA1, and the second group of data lines is disposed in the second driving region DDA 2. Further, a third group of data lines is disposed in the third driving region DDA3, and a fourth group of data lines is disposed in the fourth driving region DDA 4.

Referring to fig. 8 and 9, the first driving region DDA1 in which a first group of data lines DL1 through DLj (hereinafter, a first data line group) is disposed may be divided into a plurality of block regions. As an example of the present disclosure, the first driving region DDA1 may include four block regions (hereinafter, a first block region BA1, a second block region BA2, a third block region BA3, and a fourth block region BA 4).

The first data line group DL1 to DLj may be divided into a plurality of blocks arranged to correspond to a plurality of block regions, respectively. As an example of the present disclosure, the first data line group DL1 to DLj includes first data line blocks DLa1 to DLak, second data line blocks DLb1 to DLbk, third data line blocks DLc1 to DLck, and fourth data line blocks DLd1 to DLdk. The first data line blocks DLa1 to DLak are disposed in the first block area BA1, and the second data line blocks DLb1 to DLbk are disposed in the second block area BA 2. The third data line blocks DLc1 to DLck are disposed in the third block area BA3, and the fourth data line blocks DLd1 to DLdk are disposed in the fourth block area BA 4.

The first data line group DL1 to DLj is connected to the first data integrated circuit 410 through the first fan-out line groups FL1 to FLj. As an example of the present disclosure, the fanout lines of the first fanout line group FL1 to FLj may have different line resistances. Therefore, even if the data voltages are simultaneously output from the first data integrated circuits 410, the time points at which the data voltages arrive at the first data line group DL1 to DLj may be different from each other while passing through the first fan-out line groups FL1 to FLj having different line resistances.

As described above, when the first fan-out line groups FL1 to FLj have different line resistances, a time point at which the data voltage is output may be adjusted in consideration of the line resistance of each of the first fan-out line groups FL1 to FLj.

Further, the gate signal output from the first gate driving circuit 210 may be delayed from the first end of each of the gate lines GL1 to GLm (shown in fig. 7) toward the center. Specifically, a difference occurs between a point of time when the gate signal reaches a pixel connected to the first data line DL1 in the first data line group DL1 to DLj and a point of time when the gate signal reaches a pixel connected to the last data line DLj (hereinafter, on-time point).

For example, a point of time at which a pixel (hereinafter, a first pixel) connected to the first gate line GL1 and the first data line DL1 is turned on in response to a first gate signal may be different from a point of time at which a pixel (hereinafter, a jth pixel) connected to the first gate line GL1 and the jth data line DLj is turned on in response to a first gate signal. That is, the turn-on time point of the jth pixel may be delayed from the turn-on time point of the first pixel by a predetermined time. The delay time of the gate signal may vary according to the line resistance of each gate line.

As described above, the on time between pixels may be deviated according to the position according to the line resistance of each gate line. Further, when a deviation occurs in the turn-on time between pixels included in the same pixel row, there may occur a problem that the charging rate of the pixels that are turned on relatively slowly is lowered.

In order to improve the charging rate reduction problem, the first data integrated circuit 410 may adjust a time point of outputting the data voltage in consideration of a line resistance of each gate line.

The data voltages Da1 to Dak of the first block are supplied to the first data line blocks DLa1 to DLak disposed in the first block area BA 1. The data voltages Db1 to Dbk of the second blocks are supplied to the second data line blocks DLb1 to DLbk disposed in the second block area BA 2. Here, the data voltages Da1 to Dak of the first block have a first time difference (1t/k) at a first time point t1, and are sequentially delayed from the first data voltage Da1 to the kth data voltage Dak. On the other hand, the data voltages Db1 to Dbk of the second block have a second time difference (2t/k) at a second time point t2, and are sequentially delayed from the first data voltage Db1 to the kth data voltage Dbk.

In addition, the data voltages Dc1 to Dck of the third block are supplied to the third data line blocks DLc1 to DLck disposed in the third block area BA 3. The data voltages Dd1 to Ddk of the fourth block are supplied to the fourth data line blocks DLd1 to DLdk arranged in the fourth block area BA 4. Here, the data voltages Dc1 through Dck of the third block have a third time difference (0.5t/k) at a fourth time point t4, and are sequentially delayed from the first data voltage Dc1 through the kth data voltage Dck. On the other hand, the data voltages Dd1 through Ddk of the fourth block have a fourth time difference (1.5t/k) at the 4.5 th time point t4.5, and are sequentially delayed from the first data voltage Dd1 to the k-th data voltage Ddk.

Referring to fig. 10 and 11, the fourth driving region DDA4 in which the fourth group of data lines DL3j +1 to DLn (hereinafter, a fourth data line group) is disposed may be divided into a plurality of block regions. As an example of the present disclosure, the fourth driving area DDA4 may include four block areas (hereinafter, a first block area BA1, a second block area BA2, a third block area BA3, and a fourth block area BA 4). Fig. 10 shows that the fourth driving region DDA4 includes the same number of block regions as the first driving region DDA1, but the present disclosure is not limited thereto. That is, the fourth drive region DDA4 may include a different number of block regions from the number of block regions included in the first drive region DDA 1. It is also possible that the fourth drive region DDA4 includes three block regions, for example.

The fourth data line group DL3j +1 to DLn may be divided into a plurality of blocks arranged to correspond to a plurality of block regions, respectively. As an example of the present disclosure, the fourth data line group DL3j +1 to DLn includes first data line blocks DLa1 to DLak, second data line blocks DLb1 to DLbk, third data line blocks DLc1 to DLck, and fourth data line blocks DLd1 to DLdk. The first data line blocks DLa1 to DLak are disposed in the first block area BA1, and the second data line blocks DLb1 to DLbk are disposed in the second block area BA 2. The third data line blocks DLc1 to DLck are disposed in the third block area BA3, and the fourth data line blocks DLd1 to DLdk are disposed in the fourth block area BA 4.

Further, the gate signal output from the second gate driving circuit 220 may be delayed from the second end of each of the gate lines GL1 to GLm (shown in fig. 7) toward the center. Specifically, a difference occurs between a point of time when the gate signal reaches a pixel connected to the (3j +1) th data line DL3j +1 in the fourth data line group DL3j +1 to DLn and a point of time when the gate signal reaches a pixel connected to the last data line DLn (hereinafter, an on-time point).

For example, a point of time at which a pixel connected to the first gate line GL1 and the (3j +1) th data line DL3j +1 (hereinafter, the (3j +1) th pixel) is turned on in response to a first gate signal may be different from a point of time at which a pixel connected to the first gate line GL1 and the n-th data line DLn (hereinafter, the n-th pixel) is turned on in response to a first gate signal. That is, the turn-on time point of the (3j +1) th pixel may be delayed from the turn-on time point of the nth pixel by a predetermined time. The delay time of the gate signal may vary according to the line resistance of each gate line.

As described above, the on time between pixels may be deviated according to the position according to the line resistance of each gate line. Further, when a deviation occurs in the turn-on time between pixels included in the same pixel row, there may occur a problem that the charging rate of the pixels that are turned on relatively slowly is lowered.

In order to improve the charging rate reduction problem, the fourth data integrated circuit 440 may adjust a time point of outputting the data voltage in consideration of a line resistance of each gate line.

As shown in fig. 10 and 11, the data voltages Da1 through Dak of the first block are supplied to the first data line blocks DLa1 through DLak disposed in the first block area BA 1. The data voltages Db1 to Dbk of the second blocks are supplied to the second data line blocks DLb1 to DLbk disposed in the second block area BA 2. Here, the data voltages Da1 to Dak of the first block have a first time difference (1.5t/k) at the 4.5 time point t4.5, and are sequentially delayed from the kth data voltage Dak to the first data voltage Da 1. On the other hand, the data voltages Db1 to Dbk of the second block have a second time difference (0.5t/k) at the fourth time point t4, and are sequentially delayed from the k-th data voltage Dbk to the first data voltage Db 1.

In addition, the data voltages Dc1 to Dck of the third block are supplied to the third data line blocks DLc1 to DLck disposed in the third block area BA 3. The data voltages Dd1 to Ddk of the fourth block are supplied to the fourth data line blocks DLd1 to DLdk arranged in the fourth block area BA 4. Here, the data voltages Dc1 to Dck of the third block have a third time difference (2t/k) at the second time point t2, and are sequentially delayed from the kth data voltage Dck to the first data voltage Dc 1. On the other hand, the data voltages Dd1 to Ddk of the fourth block have a fourth time difference (1t/k) at the first time point t1, and are sequentially delayed from the k-th data voltage Ddk to the first data voltage Dd 1.

As described above, since the first data integrated circuit 410 and the fourth data integrated circuit 440 are disposed at different positions, the output time point of the data voltage may be controlled with different delay patterns. In addition, since each of the first and fourth data integrated circuits 410 and 440 includes a plurality of output blocks, the delay value of the data voltage may be adjusted in units of blocks.

Fig. 12 is a plan view of a display device according to an example embodiment of the present disclosure. Fig. 13 is an enlarged plan view of the second to fourth data integrated circuits and the display panel shown in part a4 of fig. 12. Fig. 14 is a waveform diagram illustrating output time points of data voltages applied to data lines disposed in the second to fourth driving regions illustrated in fig. 13.

Referring to fig. 12, the data driver 400 (referring to fig. 1) may include a first data integrated circuit 410, a second data integrated circuit 420, a third data integrated circuit 430, a fourth data integrated circuit 440, and a fifth data integrated circuit 450. In fig. 12, the data driver 400 is shown to have a structure including five data integrated circuits 410 to 450, but the present disclosure is not limited thereto.

According to an embodiment, the display device 1000 may further include flexible circuit boards 310 to 350 and a printed circuit board 370 electrically connected to the flexible circuit boards 310 to 350, and the data integrated circuits 410 to 450 are mounted in the flexible circuit boards 310 to 350 in a TCP manner. Specifically, the display device 1000 may include a first flexible circuit board 310 on which a first data integrated circuit 410 is mounted, a second flexible circuit board 320 on which a second data integrated circuit 420 is mounted, a third flexible circuit board 330 on which a third data integrated circuit 430 is mounted, a fourth flexible circuit board 340 on which a fourth data integrated circuit 440 is mounted, and a fifth flexible circuit board 350 on which a fifth data integrated circuit 450 is mounted.

The first to fifth flexible circuit boards 310 to 350 electrically connect the display panel 500 and the printed circuit board 370 and are disposed between the display panel 500 and the printed circuit board 370.

The first data integrated circuit 410 may be connected to a first group of data lines among the data lines DL1 through DLn, and the second data integrated circuit 420 may be connected to a second group of data lines among the data lines DL1 through DLn. The third data integrated circuit 430 may be connected to a third group of the data lines DL1 through DLn, and the fourth data integrated circuit 440 may be connected to a fourth group of the data lines DL1 through DLn, and the fifth data integrated circuit 450 may be connected to a fifth group of the data lines DL1 through DLn.

Here, the display area DA may include first to fifth driving areas DDA1 to DDA5 driven by the first to fifth data integrated circuits 410 to 450, respectively. The first group of data lines is disposed in the first driving region DDA1, and the second group of data lines is disposed in the second driving region DDA 2. Further, a third group of data lines is disposed in the third driving region DDA3, and a fourth group of data lines is disposed in the fourth driving region DDA 4. The fifth group of data lines is disposed in the fifth driving region DDA 5.

Referring to fig. 12 and 13, the second data integrated circuit 420 is connected to the second group of data lines DLa1, DLag, DLah, DLai and DLaj disposed in the second driving region DDA 2. The third data integrated circuit 430 is connected to the third group of data lines DLb1, DLbg, DLbh, DLbi, and DLbj arranged in the third driving region DDA 3. The fourth data integrated circuit 440 is connected to the fourth set of data lines DLc1, DLcg, DLch, DLci, and DLcj disposed in the fourth driving region DDA 4. The second to fourth drive regions DDA 2-DDA 4 are disposed between the first and fifth drive regions DDA1, DDA 5.

Each of the second, third and fourth driving regions DDA2, DDA3 and DDA4 may be divided into a plurality of block regions. As an example of the present disclosure, each of the second, third and fourth driving regions DDA2, DDA3 and DDA4 may include four block regions. The second driving area DDA2 includes a first block area BA1a, a second block area BA2a, a third block area BA3a, and a fourth block area BA4a, and the third driving area DDA3 includes a first block area BA1b, a second block area BA2b, a third block area BA3b, and a fourth block area BA4b, and the fourth driving area DDA4 includes a first block area BA1c, a second block area BA2c, a third block area BA3c, and a fourth block area BA4 c. The second, third and fourth driving regions DDA2, DDA3 and DDA4 may have a small delay difference for a gate signal of each block region, compared to the first and fifth driving regions DDA1 and DDA 5.

The second data integrated circuit 420 is connected to the second group data lines DLa1, DLag, DLah, DLai and DLaj through the second group fanout lines FLa _1, FLa _ g, FLa _ h, FLa _ i and FLa _ j. Here, the second group fanout lines FLa _1, FLa _ g, FLa _ h, FLa _ i, and FLa _ j may have the same line resistance.

As shown in fig. 14, the second group fanout lines FLa _1, FLa _ g, FLa _ h, FLa _ i, and FLa _ j have the same line resistance, and the second driving region DDA2 may include a flat period when a delay difference between gate signals between block regions in the second driving region DDA2 is small (or delay is constant). Here, the flat period may be defined as a period in which delay values of the data voltages are the same. The flat period provided in the second driving region DDA2 may be referred to as a first flat period FMP 1. As an example of the present disclosure, the first flat period FMP1 may be formed in the second block area BA2a and the third block area BA3 a. Here, a case including a flat period in which the fan-out lines have an equal resistance structure and the delay difference between the gate signals is minute (or the delay is constant) is described as an example, but the present disclosure is not limited thereto. That is, when the delay values of the gate signals are designed to be the same, there may be a flat period even in a portion where the delay difference caused by the fanout line is minute (or the delay is constant).

Also, the third group fanout lines FLb _1, FLb _ g, FLb _ h, FLb _ i, and FLb _ j have the same line resistance, and the third driving region DDA3 may include a flat period when a delay difference of gate signals between block regions in the third driving region DDA3 is small. Here, the flat period provided in the third driving region DDA3 may be referred to as a second flat period FMP 2. As an example of the present disclosure, the second flat period FMP2 may be formed in the second block area BA2b and the third block area BA3 b.

Finally, the fourth group of fanout lines FLc _1, FLc _ g, FLc _ h, FLc _ i, and FLc _ j have the same line resistance, and the fourth driving region DDA4 may include a flat period when a delay difference of gate signals between block regions in the fourth driving region DDA4 is small. Here, the flat period provided in the fourth driving region DDA4 may be referred to as a third flat period FMP 3. As an example of the present disclosure, the third flat period FMP3 may be formed in the second block area BA2c and the third block area BA3 c.

In the first flat period FMP1, the output time points of the data voltages Dag and Dah may be maintained at the 3.5 time point t3.5, and in the second flat period FMP2, the output time points of the data voltages Dbg and Dbh may be maintained at the 4.5 time point t 4.5. In order to prevent the boundary from being seen in the display region due to the delay difference between the first and second flat periods FMP1 and FMP2, a non-flat period in which the delay value of the data voltage is not the same may be provided between the first and second flat periods FMP1 and FMP 2. A non-flat period between the first and second flat periods FMP1 and FMP2 may be provided in the fourth block area BA4a of the second driving region DDA2 and the first block area BA1b of the third driving region DDA 3. The data voltages Dai to Daj supplied to the fourth block of the fourth block area BA4a of the second driving area DDA2 have a first time difference (0.5t/(j-i)) at the 3.5 time point t3.5 and may be sequentially delayed from the ith to jth data voltages Dai to Daj. The data voltages Db1 to Dbg-1 supplied to the first block of the first block area BA1b of the third driving area DDA3 may also have a first time difference (0.5t/(j-i)) and may be sequentially delayed from the first data voltage Db1 to the (g-1) th data voltage Dbg-1.

The output time points of the data voltages Dcg and Dch in the third flat period FMP3 may be maintained at the 3.5 time point t 3.5. In this case, in order to prevent the boundary from being seen in the display region due to the delay difference between the second and third flat periods FMP2 and FMP3, non-flat periods in which the delay values of the data voltages are not the same may be provided between the second and third flat periods FMP2 and FMP 3. A non-flat period between the second and third flat periods FMP2 and FMP3 may be provided in the fourth block area BA4b of the third driving region DDA3 and the first block area BA1c of the fourth driving region DDA 4. The data voltages Dbi to Dbj supplied to the fourth block of the fourth block area BA4b of the third driving area DDA3 have a second time difference (0.5t/(j-i)) at the 4.5 th time point t4.5 and may be sequentially delayed from the j-th data voltage Dbj to the i-th data voltage Dbi. The data voltages Dc1 to Dcg-1 supplied to the first blocks of the first block area BA1c of the fourth driving area DDA4 also have a second time difference (0.5t/(j-i)) and may be sequentially delayed from the (g-1) th data voltage Dcg-1 to the first data voltage Dc 1. Further, the data voltages Dci to Dcj supplied to the fourth block of the fourth block area BA4c of the fourth driving area DDA4 have a first time difference (0.5t/(j-i)) at the third time point t3 and may be sequentially delayed from the j-th data voltage Dcj to the i-th data voltage Dci.

In this way, when each of the driving regions DDA2, DDA3, and DDA4 includes the flat period FMP1, FMP2, and FMP3, a block region reflecting a delay value corresponding to a delay deviation between the flat periods FMP1, FMP2, and FMP3 may be disposed between the flat periods FMP1, FMP2, and FMP 3. Therefore, the boundaries between the flat periods FMP1, FMP2, and FMP3 can be prevented from being identified.

Fig. 15 is an enlarged plan view of a first data integrated circuit and a display panel according to another embodiment of part a1 of fig. 2, and fig. 16 is a waveform diagram illustrating output time points of data voltages of a first block to an eighth block applied to data lines of the first block to data lines of the eighth block shown in fig. 15.

Referring to fig. 15, the first driving region DDA1 in which the first data line group DL1 through DLj is disposed may be divided into a plurality of block regions. As an example of the present disclosure, the first driving area DDA1 may include eight block areas (hereinafter, a first block area BA1, a second block area BA2, a third block area BA3, a fourth block area BA4, a fifth block area BA5, a sixth block area BA6, a seventh block area BA7, and an eighth block area BA 8). However, the number of block regions included in the first driving region DDA1 is not limited thereto. For example, the first driving region DDA1 may include 5 to 7 block regions.

The first data line group DL1 to DLj may be divided into a plurality of blocks arranged to correspond to a plurality of block regions, respectively. As an example of the present disclosure, the first data line group DL1 to DLj includes first data line blocks DLa1 to DLak, second data line blocks DLb1 to DLbk, third data line blocks DLc1 to DLck, fourth data line blocks DLd1 to DLdk, fifth data line blocks DLe1 to DLek, sixth data line blocks DLf1 to DLfk, seventh data line blocks DLg1 to DLgk, and eighth data line blocks DLh1 to DLhk.

The first data line blocks DLa1 to DLak are disposed in the first block area BA1, and the second data line blocks DLb1 to DLbk are disposed in the second block area BA2, and the third data line blocks DLc1 to DLck are disposed in the third block area BA3, and the fourth data line blocks DLd1 to DLdk are disposed in the fourth block area BA 4. The fifth data line blocks DLe1 through DLek are disposed in the fifth block area BA5, and the sixth data line blocks DLf1 through DLfk are disposed in the sixth block area BA6, and the seventh data line blocks DLg1 through DLgk are disposed in the seventh block area BA7, and the eighth data line blocks DLh1 through DLhk are disposed in the eighth block area BA 8.

The data voltages Da1 to Dak of the first block are supplied to the first data line blocks DLa1 to DLak disposed in the first block area BA 1. The data voltages Db1 to Dbk of the second blocks are supplied to the second data line blocks DLb1 to DLbk disposed in the second block area BA 2. Here, the data voltages Da1 through Dak of the first block have a first time difference (0.5t/k) at the reference time point t0, and are sequentially delayed from the first data voltage Da1 through the kth data voltage Dak. On the other hand, the data voltages Db1 to Dbk of the second block have a second time difference (2t/k) at the first time point t1, and are sequentially delayed from the first data voltage Db1 to the kth data voltage Dbk.

In addition, the data voltages Dc1 to Dck of the third block are supplied to the third data line blocks DLc1 to DLck disposed in the third block area BA 3. The data voltages Dd1 to Ddk of the fourth block are supplied to the fourth data line blocks DLd1 to DLdk arranged in the fourth block area BA 4. Here, the data voltages Dc1 to Dck of the third block are delayed by the same delay value (i.e., almost the 2.5 th time (t2.5-t0)) during the first flat period FMP 1. On the other hand, the data voltages Dd1 through Ddk of the fourth block have a third time difference (0.5t/k) at the 2.5 time point t2.5, and are sequentially delayed from the first data voltage Dd1 to the k-th data voltage Ddk.

The data voltages De1 to Dek of the fifth block are supplied to the fifth data line blocks DLe1 to DLek disposed in the fifth block area BA 5. The data voltages Df1 through Dfk of the sixth block are supplied to the sixth data line blocks DLf1 through DLfk disposed in the sixth block area BA 6. The data voltages Dg1 through Dgk of the seventh block are supplied to the seventh data line blocks DLg1 through DLgk disposed in the seventh block area BA 7. The data voltages Dh1 to Dhk of the eighth block are supplied to the eighth data line blocks DLh1 to DLhk disposed in the eighth block area BA 8.

Here, the data voltages De1 to Dek of the fifth block have a fourth time difference (1t/k) at the third time point t3, and are sequentially delayed from the first data voltage De1 to the k-th data voltage Dek. The data voltages Df1 through Dfk of the sixth block and the data voltages Dg1 through Dgk of the seventh block are delayed by the same delay value (i.e., by a fourth time (t4-t0)) during the second flat period FMP 2. On the other hand, the data voltages Dh1 to Dhk of the eighth block have a fifth time difference (1t/k) at the fourth time point t4, and are sequentially delayed from the first data voltage Dh1 to the kth data voltage Dhk.

In this way, one data integrated circuit is divided into a larger number of output blocks, and the delay value of the data voltage output from one data integrated circuit can be controlled in units of output blocks. Therefore, the delay value of the data voltage can be finely adjusted, and as a result, the deviation of the charging rate between the pixels can be further reduced.

According to the data driver and the display device having the same of the present disclosure, by controlling the delay value of the data voltage output from one data integrated circuit in units of blocks, fine adjustment of the delay value can be achieved, so that the deviation of the charging rate between pixels can be reduced.

Although example embodiments of the present disclosure have been described, it is to be understood that the present disclosure should not be limited to these example embodiments, but various changes and modifications can be made by one of ordinary skill in the art within the spirit and scope of the present disclosure as hereinafter claimed.