1. The utility model provides a radio frequency energy collection system based on energy management, includes antenna and radio frequency front end, the output port of antenna with the input of radio frequency front end is connected which characterized in that: the antenna is a non-50 ohm impedance antenna and is cooperatively coupled with the radio frequency front end; the radio frequency energy acquisition system also comprises an impedance self-adaptive adjusting module, a load isolation and charge-discharge control module, a linear voltage stabilizing module, a switch K, a detection capacitor C11 and an energy storage capacitor C12; the capacitance value of the detection capacitor C11 is smaller than that of the energy storage capacitor C12; the output end of the radio frequency front end is connected with the input end of the impedance self-adaptive adjusting module, and the output end of the impedance self-adaptive adjusting module is connected with the radio frequency front end; the output end of the radio frequency front end is also connected with one end of the detection capacitor C11, and the other end of the detection capacitor C11 is grounded; the output end of the radio frequency front end is also connected with one end of the energy storage capacitor C12 and the load isolation and charge and discharge control module through the switch K, the other end of the energy storage capacitor C12 is grounded, the switch K is controlled by the impedance self-adaptive adjustment module, and the linear voltage stabilization module is connected to the output end of the load isolation and charge and discharge control module;

the antenna is used for capturing radio frequency signals and sending the captured radio frequency signals to the radio frequency front end;

the radio frequency front end is used for rectifying a radio frequency signal sent by the antenna and outputting a rectified output signal Vrect;

the detection capacitor C11 is used for being charged under the driving of a rectification output signal Vrect output by the radio frequency front end and supplying power to the impedance self-adaptive adjusting module;

the impedance self-adaptive adjusting module is used for self-adaptively adjusting the impedance of the radio frequency front end according to a rectified output signal Vrect output by the radio frequency front end so as to enable the impedance of the radio frequency front end to be in optimal conjugate matching with the impedance of the antenna;

the impedance self-adaptive adjusting module is further configured to control the switch K to be turned on in a power-on process, so that the energy storage capacitor C12 is precharged by a rectified output signal Vrect output by the radio frequency front end; the switch K is also used for controlling the switch K to be closed in the self-adaptive impedance adjustment process, so that the energy storage capacitor C12 is in a pre-charging state; the controller is also used for controlling the switch K to be opened after the impedance self-adaptive adjustment is finished, so that the energy storage capacitor C12 is continuously charged by a rectification output signal Vrect output by the radio frequency front end;

the load isolation and charge-discharge control module is used for isolating a load and keeping the load of the load isolation and charge-discharge control module consistent with the load of the impedance self-adaptive adjustment module; the energy storage capacitor C12 is used for managing the charging and discharging process of the energy storage capacitor C12 and outputting power supply voltage after the energy storage voltage value of the energy storage capacitor C12 reaches a set voltage value;

and the linear voltage stabilizing module is used for stabilizing the power supply voltage output by the load isolation and charge-discharge control module and outputting stable power supply voltage.

2. The energy management based radio frequency energy harvesting system of claim 1, wherein: the load isolation and charge-discharge control module comprises a first reference voltage unit, a voltage division unit, a continuous comparator and an inversion unit;

the first reference voltage unit is used for generating a reference voltage insensitive to the energy storage voltage and the temperature under the driving of the energy storage voltage output by the energy storage capacitor C12 and outputting the reference voltage to the continuous comparator;

the voltage dividing unit is used for dividing the energy storage voltage output by the energy storage capacitor C12 to generate two divided voltages with different proportions, and selecting one divided voltage to output to the continuous comparator;

the continuous comparator is used for comparing the reference voltage output by the first reference voltage unit with the divided voltage output by the voltage dividing unit and outputting a comparison result; the comparison result is used for representing whether the energy storage voltage value of the energy storage capacitor C12 reaches a preset value or not;

and the inverting unit is used for managing the charging and discharging processes of the energy storage capacitor C12 according to the comparison result output by the continuous comparator and outputting a power supply voltage.

3. The energy management based radio frequency energy harvesting system of claim 2, wherein: the voltage division unit comprises a voltage division network and a data selector, and the phase inversion unit comprises a dynamic leakage suppressor, an inverter and a transistor M;

the input end of the first reference voltage unit and the input end of the voltage division network are connected with the charging and discharging end of the energy storage capacitor C12, the output end of the first reference voltage unit is connected with the reverse input end of the continuous comparator, the output end of the voltage division network is connected with the forward input end of the continuous comparator through the data selector, the output end of the continuous comparator sequentially passes through the dynamic leakage suppressor and the phase inverter and is connected with the grid electrode of the transistor M, the output end of the dynamic leakage suppressor is connected on the selection signal input end of the data selector, the source electrode of the transistor M is connected on the charging and discharging end of the energy storage capacitor C12, and the drain electrode of the transistor outputs the power supply voltage.

4. The energy management based radio frequency energy harvesting system of claim 1, wherein: the linear voltage stabilizing module comprises a second reference voltage unit, an error amplifying unit, an adjusting tube and a feedback network;

the second reference voltage unit is used for generating a reference voltage insensitive to the power supply voltage and the temperature under the driving of the power supply voltage output by the load isolation and charge-discharge control module and outputting the reference voltage to the error amplification unit;

the error amplifying unit is used for comparing the reference voltage output by the second reference voltage unit with the feedback voltage output by the feedback network to obtain an error signal and controlling the conduction degree of the adjusting tube according to the error signal;

the adjusting tube is used for outputting stable power supply voltage under the control of the error amplifying unit;

the feedback network is used for obtaining the feedback voltage according to the voltage division ratio of the power supply voltage output by the adjusting tube by a resistance voltage division method.

5. The energy management based radio frequency energy harvesting system of claim 4, wherein: the feedback network comprises a resistor R1 and a resistor R2;

the input end of the second reference voltage unit is connected to the output end of the load isolation and charge-discharge control module, the output end of the second reference voltage unit is connected to the forward input end of the error amplification unit, the voltage output end of the error amplification unit is connected to the voltage input end of the adjustment tube, the error signal output end of the error amplification unit is connected to the controlled end of the adjustment tube, the output end of the adjustment tube outputs the power voltage, the output end of the adjustment tube is grounded sequentially through the resistor R1 and the resistor R2, and the common connection end of the resistor R1 and the resistor R2 is connected to the reverse input end of the error amplification unit.

6. A radio frequency energy harvesting system based on energy management according to any of claims 1-5, characterized by: the antenna is specifically a differential antenna, and the radio frequency front end comprises a differential rectifier and a CTC structure switch capacitor array; the two output ports of the differential antenna are connected with the input end of the differential rectifier, the two output ports of the differential antenna are also connected with the CTC structure switch capacitor array, the input end of the impedance self-adaptive adjusting module is connected with the output end of the differential rectifier, and the output end of the impedance self-adaptive adjusting module is connected with the CTC structure switch capacitor array.

7. The energy management based radio frequency energy harvesting system of claim 6, wherein: the differential rectifier comprises a plurality of stages of four-tube differential pairs, and each stage of the four-tube differential pairs is connected with two output ports of the differential antenna; any stage of the four-tube differential pair comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C13 and a second capacitor C14; in any stage of the four-transistor differential pair, the drain of the first transistor M1, the drain of the third transistor M3, the gate of the second transistor M2, and the gate of the fourth transistor M4 are connected together and then connected to one output port of the differential antenna through the first capacitor C13, and the gate of the first transistor M1, the gate of the third transistor M3, the drain of the second transistor M2, and the drain of the fourth transistor M4 are connected together and then connected to the other output port of the differential antenna through the second capacitor C14; in two adjacent four-tube differential pairs, the source electrode of the third transistor M3 and the source electrode of the fourth transistor M4 in the four-tube differential pair at the previous stage are connected together, and the source electrode of the first transistor M1 and the source electrode of the second transistor M2 in the four-tube differential pair at the next stage are connected together; in the four-tube differential pair of the first stage, the source electrode of the first transistor M1 and the source electrode of the second transistor M2 are grounded; in the last stage of the four-transistor differential pair, the source of the third transistor M3 and the source of the fourth transistor M4 output the rectified output signal Vrect in common.

8. The energy management based radio frequency energy harvesting system of claim 6, wherein: the CTC structure switch capacitor array comprises a plurality of stages of CTC structure switch capacitors, and each stage of the CTC structure switch capacitors comprises a first unit capacitor, a second unit capacitor and a switch tube; in any stage of the CTC structure switched capacitor, one end of the first unit capacitor is connected to one output port of the differential antenna, the other end of the first unit capacitor is connected to a drain of the switching tube, a source of the switching tube is connected to one end of the second unit capacitor, the other end of the second unit capacitor is connected to the other output port of the differential antenna, and a gate of the switching tube is connected to the impedance adaptive adjustment module.

9. A radio frequency energy harvesting system based on energy management according to any of claims 1-5, 7-8, characterized by: the impedance self-adaptive adjusting module comprises a clock generating unit, a starting unit, a time sequence adjusting unit, a comparison adjusting unit and a counting output unit;

the clock generation unit is used for generating a reference clock signal CLK and a clock stabilization enabling signal VENO delayed relative to the rectified output signal Vrect under the driving of the rectified output signal Vrect output by the differential rectifier;

the starting unit is used for judging whether the power-on process is finished or not by sampling and comparing a rectification output signal Vrect output by the differential rectifier at the starting time and the ending time of one clock cycle based on the reference clock signal CLK and the clock stabilization enabling signal VENO in the power-on process, and generating and outputting a power-on completion enabling signal VEN1 when the power-on process is finished;

the timing adjusting unit is used for converting the reference clock signal CLK into two sample-hold clock signals CLK2 and comparison clock signals CLK2A with the same frequency and preset delay and a counting enable signal VEN2 based on the rectified output signal Vrect and the power-up completion enable signal VEN 1;

the comparison and adjustment unit is used for performing sampling, holding and comparison judgment on a rectified output signal Vrect output by the differential rectifier based on the power-on completion enable signal VEN1, the sampling and holding clock signal CLK2 and the comparison clock signal CLK2A, outputting a counting signal Vcount, and generating an adjustment completion enable signal VEN3 and a potential signal VDD 2; the clock generation unit is also used for controlling the clock generation unit to be closed according to the potential signal VDD 2;

the counting output unit is used for carrying out frequency division processing on the counting signal Vcount based on the counting enable signal VEN2 and the rectification output signal Vrect to obtain a multi-bit binary control signal, outputting the multi-bit binary control signal to the CTC structure switch capacitor array, and controlling the on-off of a switch tube in each stage of the CTC structure switch capacitor through the multi-bit binary control signal to determine the number of unit capacitors added into the CTC structure switch capacitor array, so that the self-adaptive impedance adjustment of a radio frequency front end is completed, and the impedance of the radio frequency front end is in conjugate matching with the impedance of the antenna; wherein the number of bits of the binary control signal is equal to the number of stages of the CTC-configured switched capacitors in the CTC-configured switched capacitor array;

the switch K is controlled by the power-up completion enable signal VEN1 and the adjustment end enable signal VEN 3.

10. A passive radio frequency tag, characterized by: the radio frequency energy harvesting system based on energy management comprising any one of claims 1 to 9, the passive radio frequency tag further comprising an analog front end, an EEPROM, and a digital baseband;

the output of the linear voltage stabilizing module is connected with the analog front end, the analog front end is respectively connected with the EEPROM and the digital baseband, and the EEPROM is connected with the digital baseband;

the analog front end is used for providing stable power output, reference output, clock signals and reset signals for the EEPROM and the digital baseband under the driving of the power voltage output by the linear voltage stabilizing module; the antenna is also used for receiving the RF signal transmitted by the antenna, demodulating the RF signal transmitted by the antenna to generate a baseband signal and sending the baseband signal to a digital baseband;

the digital baseband is used for carrying out command analysis on the baseband signal to generate a corresponding instruction and a corresponding parameter;

the EEPROM is used for providing corresponding data read-write operation for the digital baseband according to the instruction and the parameter and returning corresponding read-write operation data to the digital baseband according to the instruction and the parameter;

the digital baseband is also used for transmitting the read-write operation data and/or the internal data of the digital baseband returned by the EEPROM to an analog front end;

the analog front end is further configured to modulate the read-write operation data and/or the internal data of the digital baseband transmitted by the digital baseband, and send the modulated read-write operation data and/or the internal data of the digital baseband to an antenna.

Background

With the continuous development and interaction of network communication technology, big data technology, sensing technology and integrated circuit technology, passive internet of things node technology without power supply or battery power supply is receiving more and more attention, and passive tag technology formed by combining a passive chip of an internet of things node and an antenna becomes a key and hot problem for research and application. With the continuous development of system technology, chip technology and antenna integration technology, the applicable scene of the passive tag for the internet of things node is continuously expanded, and from the recent logistics field, anti-counterfeiting traceability field and intelligent transportation field, along with the further integration of communication technology, data technology and sensing technology, the application in the fields of smart farms, smart homes, environment monitoring, medical health and the like is gradually developed. With the demand of passive node communication extension, especially the integration into the current communication base station, wireless hotspot and other basic systems, the multi-mode passive or semi-active auxiliary communication with long distance and low power consumption is realized, the node is required to have extremely high energy activation sensitivity, and simultaneously, higher requirements are provided for the power consumption of a node chip and the acquisition, management and utilization of energy.

At present, researches on the aspect of obtaining the energy of the passive tag chip need to be improved, particularly on the aspect of utilizing radio frequency energy, various types of matching networks need to be added to the traditional 50-ohm matching impedance to achieve the highest power transmission, and the added matching networks can increase great loss. In addition, at present, there is also an antenna with conjugate impedance designed directly through chip impedance, so that energy loss caused by matching network is avoided, but impedance cannot be accurately matched, chip impedance is easily affected by environmental factors, process manufacturing factors and the like, especially for a high-sensitivity passive tag, the difference between the impedance and the antenna impedance determines the working performance of the tag, and for a large number of tags, it is time-consuming and labor-consuming to perform impedance matching.

At present, there are related art inventions, such as: in the adjusting technology mentioned in the RFID antenna impedance self-adaptive adjusting method (application number 201610482611.3) under the severe working condition, 50 ohm matching is not suitable for high-sensitivity specific impedance antenna matching, in addition, the measuring phase difference is complex, the power consumption in the adjusting process is large, and the requirement of a clock on an FPGA (field programmable gate array) for providing a clock is not easy to integrate on a chip is high; in a radio frequency energy acquisition system (application No. 201610163509.7) based on a dynamic impedance matching technology, the radio frequency energy acquisition system also aims at a 50 ohm matching network to adjust and has higher requirement on a clock; in an ultrahigh frequency RFID read-write module (application number 201210505064.8) based on an antenna adaptive tuning technology, a central processing unit is needed, and the ultrahigh frequency RFID read-write module also comprises two crystal oscillators for generating clocks, so that the ultrahigh frequency RFID read-write module is not suitable for high-sensitivity labels, and is not easy to integrate due to the existence of the crystal oscillators; the resonant wireless power transmission system capable of self-tuning impedance and the control method (application number 201910201498.0) aim at 50 ohm matching design, are not high in adjustment precision, are not suitable for specific impedance and high-sensitivity label adjustment; in a pi-type impedance automatic matching system and a method (application number 201710267102.3) in a radio frequency energy acquisition circuit, impedance adjustment is carried out by adjusting a pi-type network, and the system has complex circuit structure and algorithm and higher power consumption; in a passive ultrahigh frequency radio frequency identification tag (application number 201710267093.8) with an automatic impedance matching function, an additional auxiliary voltage-multiplying rectifying unit is added to specially supply power for an automatic impedance matching network, the additional rectifying unit reduces the sensitivity of the tag, and the system collaborative design framework is not complete enough.

With the development of communication technologies, such as 5G communication and new generation communication technologies, narrow-band communication for nodes of the internet of things is an important component, and within a certain narrow-band frequency range divided by international communication standards, due to differences in regions, industries and processes, for example, passive RFID frequency bands, different sub-bands within the range of 860MHz to 960MHz in the united states, europe, japan and china are provided, and in addition, the impedance parameters of the radio frequency interface of the antenna and the chip are affected by unavoidable discreteness of processing parameters in the manufacturing and packaging processes of the radio frequency antenna and the radio frequency chip circuit, and by changes of actual factors such as changes of application environments of products, mismatch of a certain degree is caused, and the performance or cost of the product is affected. Impedance adjusting functions are added in products M730 and M750 series and Monza R6 series of American passive tag company, but only five impedance states are stored, large-granularity active impedance adjustment is adopted to adapt to the feedback problem in processing and application, impedance adjustment of five states under different scenes is carried out, and the current impedance adjusting precision is not high. In addition, for impedance adjustment, foreign academic circles also study, but all the techniques are adjusted based on an off-chip clock, so that the logic function is complex, the power consumption is high, the test experiment process is simplified and idealized too, the practicability is poor, and the high-sensitivity and high-precision tuning for the passive node cannot be realized by the above techniques.

Therefore, if the passive self-power supply chip can be integrated on a green energy node passive self-power supply chip without battery power supply without being limited by 50-ohm radio frequency matching during impedance self-tuning and can be realized with high precision and low power consumption, the passive self-power supply chip is favorable for solving the radio frequency interface mismatch and the adaptability of complex application scenes caused by frequency change or discreteness in the product manufacturing process and is used as an adjustable interface of a radio frequency antenna and a radio frequency front end, the application range not only comprises a passive tag chip, but also covers a passive sensing node chip and a passive internet of things node chip, and the passive self-power supply chip has a wide application market and a wide application prospect.

Disclosure of Invention

The invention aims to solve the technical problem of providing a radio frequency energy acquisition system and a passive radio frequency tag based on energy management, wherein standard 50-ohm matching is removed, a best matching effect is obtained by adopting conjugate matching, and the best matching state is still ensured after state switching through load isolation; and stable power supply voltage is output in a pre-charging and voltage-stabilizing mode, so that the follow-up circuit work is guaranteed.

The technical scheme for solving the technical problems is as follows: a radio frequency energy acquisition system based on energy management comprises an antenna and a radio frequency front end, wherein an output port of the antenna is connected with an input end of the radio frequency front end, the antenna is a non-50-ohm impedance antenna, and the antenna is cooperatively coupled with the radio frequency front end; the radio frequency energy acquisition system also comprises an impedance self-adaptive adjusting module, a load isolation and charge-discharge control module, a linear voltage stabilizing module, a switch K, a detection capacitor C11 and an energy storage capacitor C12; the capacitance value of the detection capacitor C11 is smaller than that of the energy storage capacitor C12; the output end of the radio frequency front end is connected with the input end of the impedance self-adaptive adjusting module, and the output end of the impedance self-adaptive adjusting module is connected with the radio frequency front end; the output end of the radio frequency front end is also connected with one end of the detection capacitor C11, and the other end of the detection capacitor C11 is grounded; the output end of the radio frequency front end is also connected with one end of the energy storage capacitor C12 and the load isolation and charge and discharge control module through the switch K, the other end of the energy storage capacitor C12 is grounded, the switch K is controlled by the impedance self-adaptive adjustment module, and the linear voltage stabilization module is connected to the output end of the load isolation and charge and discharge control module;

the antenna is used for capturing radio frequency signals and sending the captured radio frequency signals to the radio frequency front end;

the radio frequency front end is used for rectifying a radio frequency signal sent by the antenna and outputting a rectified output signal Vrect;

the detection capacitor C11 is used for being charged under the driving of a rectification output signal Vrect output by the radio frequency front end and supplying power to the impedance self-adaptive adjusting module;

the impedance self-adaptive adjusting module is used for self-adaptively adjusting the impedance of the radio frequency front end according to a rectified output signal Vrect output by the radio frequency front end so as to enable the impedance of the radio frequency front end to be in optimal conjugate matching with the impedance of the antenna;

the impedance self-adaptive adjusting module is further configured to control the switch K to be turned on in a power-on process, so that the energy storage capacitor C12 is precharged by a rectified output signal Vrect output by the radio frequency front end; the switch K is also used for controlling the switch K to be closed in the self-adaptive impedance adjustment process, so that the energy storage capacitor C12 is in a pre-charging state; the controller is also used for controlling the switch K to be opened after the impedance self-adaptive adjustment is finished, so that the energy storage capacitor C12 is continuously charged by a rectification output signal Vrect output by the radio frequency front end;

the load isolation and charge-discharge control module is used for isolating a load and keeping the load of the load isolation and charge-discharge control module consistent with the load of the impedance self-adaptive adjustment module; the energy storage capacitor C12 is used for managing the charging and discharging process of the energy storage capacitor C12 and outputting power supply voltage after the energy storage voltage value of the energy storage capacitor C12 reaches a set voltage value;

and the linear voltage stabilizing module is used for stabilizing the power supply voltage output by the load isolation and charge-discharge control module and outputting stable power supply voltage.

Based on the radio frequency energy acquisition system based on energy management, the invention also provides a passive radio frequency tag.

A passive radio frequency tag comprises the radio frequency energy acquisition system based on energy management, and further comprises an analog front end, an EEPROM (electrically erasable programmable read-only memory) and a digital baseband;

the output of the linear voltage stabilizing module is connected with the analog front end, the analog front end is respectively connected with the EEPROM and the digital baseband, and the EEPROM is connected with the digital baseband;

the analog front end is used for providing stable power output, reference output, clock signals and reset signals for the EEPROM and the digital baseband under the driving of the power voltage output by the linear voltage stabilizing module; the antenna is also used for receiving the RF signal transmitted by the antenna, demodulating the RF signal transmitted by the antenna to generate a baseband signal and sending the baseband signal to a digital baseband;

the digital baseband is used for carrying out command analysis on the baseband signal to generate a corresponding instruction and a corresponding parameter;

the EEPROM is used for providing corresponding data read-write operation for the digital baseband according to the instruction and the parameter and returning corresponding read-write operation data to the digital baseband according to the instruction and the parameter;

the digital baseband is also used for transmitting the read-write operation data and/or the internal data of the digital baseband returned by the EEPROM to an analog front end;

the analog front end is further configured to modulate the read-write operation data and/or the internal data of the digital baseband transmitted by the digital baseband, and send the modulated read-write operation data and/or the internal data of the digital baseband to an antenna.

The invention has the beneficial effects that: the radio frequency energy acquisition system based on energy management and the passive radio frequency tag carry out conjugate matching on the antenna and the radio frequency front end in a cooperative coupling mode, and the antenna and the radio frequency front end are directly coupled and matched to reach the optimal matching point or nearby, so that standard 50-ohm matching is not needed, and energy loss is reduced; due to the existence of the load isolation and charge-discharge control module, the load can be isolated, the load of the load isolation and charge-discharge control module is basically consistent with the load of the impedance self-adaptive adjustment module, the antenna and the radio frequency front end are still in the optimal matching state after state conversion is carried out through the switch K, the energy storage capacitor C12 is rapidly charged, and the energy storage time is saved; the energy storage capacitor C12 adopts a pre-charging mode, so that the influence of unstable power supply in the switching process of the switch K is avoided, and stable power supply voltage can be provided for a subsequent circuit under the voltage stabilization of the linear voltage stabilization module; the capacitance value of the detection capacitor C11 is smaller than that of the energy storage capacitor C12, the impedance self-adaptive adjusting module can work alone when the detection capacitor C11 is charged to a certain degree, adjustment and matching are achieved, the energy storage capacitor C12 can be charged with higher efficiency, the impedance self-adaptive adjusting module is not limited by the charging degree of the energy storage capacitor C12, and therefore the working starting time can be shortened, in addition, the capacitance value of the detection capacitor C11 is set to be smaller, and the change of the rectification output signal can be detected conveniently in a short time. Therefore, the invention can solve the impedance mismatch condition under the influence of factors such as process, environment and the like in a certain impedance range, adaptively adjust the impedance of the circuit to achieve the conjugate matching with the antenna, does not need additional inductance elements, is beneficial to the integration in a chip, realizes the maximum power collection and the energy utilization, and improves the sensitivity and the working distance of the passive tag.

Drawings

FIG. 1 is a block diagram of an overall architecture of a radio frequency energy harvesting system based on energy management according to the present invention;

FIG. 2 is a schematic diagram of a circuit structure of a differential rectifier in an energy management-based RF energy harvesting system according to the present invention;

FIG. 3 is a schematic structural diagram of a CTC-structured switched capacitor array in an energy management-based RF energy harvesting system according to the present invention;

FIG. 4 is a schematic diagram of an embodiment of an RF energy harvesting system based on energy management according to the present invention;

FIG. 5 is a schematic structural diagram of a load isolation and charge-discharge control module in a radio frequency energy collection system based on energy management according to the present invention;

FIG. 6 is a schematic structural diagram of a linear voltage stabilization module in a radio frequency energy harvesting system based on energy management according to the present invention;

FIG. 7 is a graph showing the variation trend of the output voltage of the differential rectifier when the CTC structure switch capacitor array in the RF energy collection system based on energy management is sequentially changed;

FIG. 8 is a graph showing the variation trend of the resonant point of the CTC switched capacitor array with the number of the CTC switched capacitors in the RF energy collection system based on energy management according to the present invention;

FIG. 9 is a flow chart of an adaptive impedance adjustment algorithm in a radio frequency energy harvesting system based on energy management according to the present invention;

FIG. 10 is a timing diagram of signals in an RF energy harvesting system based on energy management according to the present invention;

FIG. 11 is a schematic diagram of an overall structure of a passive RF tag according to the present invention;

fig. 12 is a schematic diagram of a specific structure of a passive rf tag according to the present invention.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.

As shown in fig. 1, a radio frequency energy collection system based on energy management includes an antenna and a radio frequency front end, an output port of the antenna is connected to an input end of the radio frequency front end, the antenna is a non-50 ohm impedance antenna, and the antenna is cooperatively coupled with the radio frequency front end; the radio frequency energy acquisition system also comprises an impedance self-adaptive adjusting module, a load isolation and charge-discharge control module, a linear voltage stabilizing module, a switch K, a detection capacitor C11 and an energy storage capacitor C12; the capacitance value of the detection capacitor C11 is smaller than that of the energy storage capacitor C12; the output end of the radio frequency front end is connected with the input end of the impedance self-adaptive adjusting module, and the output end of the impedance self-adaptive adjusting module is connected with the radio frequency front end; the output end of the radio frequency front end is also connected with one end of the detection capacitor C11, and the other end of the detection capacitor C11 is grounded; the output end of the radio frequency front end is also connected with one end of the energy storage capacitor C12 and the load isolation and charge and discharge control module through the switch K, the other end of the energy storage capacitor C12 is grounded, the switch K is controlled by the impedance self-adaptive adjustment module, and the linear voltage stabilization module is connected to the output end of the load isolation and charge and discharge control module;

the antenna is used for capturing radio frequency signals and sending the captured radio frequency signals to the radio frequency front end;

the radio frequency front end is used for rectifying a radio frequency signal sent by the antenna and outputting a rectified output signal Vrect;

the detection capacitor C11 is used for being charged under the driving of a rectification output signal Vrect output by the radio frequency front end and supplying power to the impedance self-adaptive adjusting module;

the impedance self-adaptive adjusting module is used for self-adaptively adjusting the impedance of the radio frequency front end according to a rectified output signal Vrect output by the radio frequency front end so as to enable the impedance of the radio frequency front end to be in optimal conjugate matching with the impedance of the antenna;

the impedance self-adaptive adjusting module is further configured to control the switch K to be turned on in a power-on process, so that the energy storage capacitor C12 is precharged by a rectified output signal Vrect output by the radio frequency front end; the switch K is also used for controlling the switch K to be closed in the self-adaptive impedance adjustment process, so that the energy storage capacitor C12 is in a pre-charging state; the controller is also used for controlling the switch K to be opened after the impedance self-adaptive adjustment is finished, so that the energy storage capacitor C12 is continuously charged by a rectification output signal Vrect output by the radio frequency front end;

the load isolation and charge-discharge control module is used for isolating a load and keeping the load of the load isolation and charge-discharge control module consistent with the load of the impedance self-adaptive adjustment module; the energy storage capacitor C12 is used for managing the charging and discharging process of the energy storage capacitor C12 and outputting power supply voltage after the energy storage voltage value of the energy storage capacitor C12 reaches a set voltage value;

and the linear voltage stabilizing module is used for stabilizing the power supply voltage output by the load isolation and charge-discharge control module and outputting stable power supply voltage.

The following describes the antenna, the radio frequency front end, the impedance adaptive adjustment module, the load isolation and charge-discharge control module, and the linear voltage stabilization module in detail.

An antenna:

in the present invention, the antenna is specifically a dipole differential antenna, and is configured to capture a radio frequency signal and send the captured radio frequency signal to the radio frequency front end as two alternating current signals with equal amplitude and opposite phases. The differential antenna is specifically a standard antenna with specific high Q value and non-50 ohms, and is directly in conjugate matching with the impedance of the radio frequency front end, so that a standard 50-ohm impedance matching network is omitted, and the loss of matching 50 ohms is reduced.

A radio frequency front end:

the radio frequency front end includes a differential rectifier and a CTC architecture switched capacitor array.

In the present invention, the differential rectifier is configured to convert two ac signals sent by the differential antenna into a dc signal and output a rectified output signal Vrect. The differential rectifier is specifically a four-tube differential rectifier, which mainly comprises two PMOS tubes and two NMOS tubes, and mainly adopts the principle that the differential rectifier is composed of multi-stage four-tube differential pairs, and each stage of the four-tube differential pairs forms a structure similar to diode rectification.

Specifically, as shown in fig. 2, the differential rectifier includes a plurality of stages of four-tube differential pairs, and each stage of the four-tube differential pairs is connected to two output ports of the differential antenna; any stage of the four-tube differential pair comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C13 and a second capacitor C14; in any stage of the four-transistor differential pair, the drain of the first transistor M1, the drain of the third transistor M3, the gate of the second transistor M2, and the gate of the fourth transistor M4 are connected together and then connected to one output port of the differential antenna through the first capacitor C13, and the gate of the first transistor M1, the gate of the third transistor M3, the drain of the second transistor M2, and the drain of the fourth transistor M4 are connected together and then connected to the other output port of the differential antenna through the second capacitor C14; in two adjacent four-tube differential pairs, the source electrode of the third transistor M3 and the source electrode of the fourth transistor M4 in the four-tube differential pair at the previous stage are connected together, and the source electrode of the first transistor M1 and the source electrode of the second transistor M2 in the four-tube differential pair at the next stage are connected together; in the four-tube differential pair of the first stage, the source electrode of the first transistor M1 and the source electrode of the second transistor M2 are grounded; in the last stage of the four-transistor differential pair, the source of the third transistor M3 and the source of the fourth transistor M4 output the rectified output signal Vrect in common. In fig. 2, ANT1 and ANT2 are used to connect to two output ports of a differential antenna, respectively.

More specifically, in any stage of the four-transistor differential pair, the capacitance values of the first capacitor C13 and the second capacitor C14 are equal and are both the capacitance value of one unit capacitor. In any stage of the four-transistor differential pair, the first transistor M1 and the second transistor M2 are both NMOS transistors, and the third transistor M3 and the fourth transistor M4 are both PMOS transistors. In this embodiment, the four-tube differential pair of the differential rectifier has five stages, and in other embodiments, the four-tube differential pair may have six stages, seven stages, and the like, which are reasonably arranged as required.

In the invention, the CTC structure switched capacitor array is used for determining the number of unit capacitors to be added according to the on/off of a switching tube, adjusting the impedance of the radio frequency front end by using the number of the unit capacitors to be added, and realizing conjugate matching between the impedance of the radio frequency front end and the impedance of the differential antenna. The main principle of the CTC structure switch capacitor array is that a capacitor-switch tube-capacitor with a symmetrical structure forms the capacitor array with the CTC structure, the switch signal applied to the grid electrode of the switch tube controls the switch tube to be opened and closed, and then whether the capacitor is added into a circuit is controlled, so that the circuit impedance is changed.

Specifically, the CTC structure switched capacitor array includes a plurality of stages of CTC structure switched capacitors, and each stage of the CTC structure switched capacitor includes a first unit capacitor, a second unit capacitor, and a switching tube; in any stage of the CTC structure switched capacitor, one end of the first unit capacitor is connected to one output port of the differential antenna, the other end of the first unit capacitor is connected to a drain of the switching tube, a source of the switching tube is connected to one end of the second unit capacitor, the other end of the second unit capacitor is connected to the other output port of the differential antenna, and a gate of the switching tube is connected to the impedance adaptive adjustment module.

Preferably, each stage of the CTC structure switched capacitor further includes a bleeder tube, and in any stage of the CTC structure switched capacitor, a gate of the switching tube is connected to the impedance adaptive adjustment module through the bleeder tube; specifically, in any stage of the CTC structure switched capacitor, a gate of the switching tube is connected to a source of the discharging tube, a drain of the discharging tube is grounded, and the gate of the discharging tube is connected to the impedance adaptive adjustment module;

preferably, each stage of the CTC structure switched capacitor further includes a first bias tube and a second bias tube, in any stage of the CTC structure switched capacitor, a gate of the switch tube is connected to a gate of the first bias tube and a gate of the second bias tube, a drain of the first bias tube and a drain of the second bias tube are correspondingly connected to a source and a drain of the switch tube, and a source of the first bias tube and a source of the second bias tube are both grounded.

Further specifically, the first unit capacitor and the second unit capacitor are both MOM capacitors, the switching tubes are NMOS switching tubes, the first bias tube and the second bias tube are both NMOS bias tubes, and the drain tube is a PMOS drain tube. The bias tube is used for balancing the voltage of the source and the drain of the switch tube, keeping the direct current levels of the two ends consistent and playing a role in balancing voltage for the floating differential structure; the bleeder tube is used for relieving the voltage coupled with the grid electrode of the switch tube, so that all switches are closed in the electrifying process. The CTC structure switch capacitor in the CTC structure switch capacitor array is provided with multiple stages, the frequency of impedance adjustment is adjustable, the adjustment frequency is multiple, the adjustment precision is high, and the adjustable range is large.

The PMOS bleeder tube is mainly used for ensuring that alternating voltage cannot be coupled on a grid of the CTC structure switch capacitor array in the electrifying process, and is closed when the impedance adaptive adjusting module starts to work, namely a reference enabling signal arrives, so that the CTC structure switch capacitor array is controlled by the impedance adaptive adjusting module (specifically, controlled by a counting output unit in the impedance adaptive adjusting module).

In a specific embodiment, as shown in fig. 3, the CTC structure switched capacitor array includes five stages of CTC structure switched capacitors (in other embodiments, the number of stages of CTC structure switched capacitors in the CTC structure switched capacitor array may be set to a numerical value, such as six stages, seven stages, etc., which are reasonably set according to actual needs). In the first stage CTC structure switched capacitor: the first unit capacitor and the second unit capacitor are both Cap, the switch tube is M11, the first bias tube is M12, the second bias tube is M13, and the discharge tube is M14. In the second stage CTC structure switched capacitor: the first unit capacitor and the second unit capacitor are both 2-Cap, the switching tube is M21, the first bias tube is M22, the second bias tube is M23, and the discharge tube is M24. In the third stage CTC structure switched capacitor: the first unit capacitor and the second unit capacitor are both 4-Cap, the switching tube is M31, the first bias tube is M32, the second bias tube is M33, and the discharge tube is M34. In the fourth stage CTC structure switched capacitor: the first unit capacitor and the second unit capacitor are both 8-Cap, the switching tube is M41, the first bias tube is M42, the second bias tube is M43, and the discharge tube is M44. In the fifth stage CTC structure switched capacitor: the first unit capacitor and the second unit capacitor are both 16-Cap, the switching tube is M51, the first bias tube is M52, the second bias tube is M53, and the discharge tube is M54. In fig. 3, ANT1 and ANT2 are used to connect to two output ports of a differential antenna, respectively.

The first unit capacitor and the second unit capacitor are MOM capacitors with the same-layer metal inserted finger type structure, can be very small and are suitable for high-precision adjustment of high-sensitivity labels; according to the invention, analysis is carried out according to the adjustment range of the system impedance, and finally the capacitance value of the unit capacitor is determined to be 5fF, namely the capacitance of the Cap in FIG. 3 is 5fF, and the capacitance value of each other stage is increased in a binary manner, namely 1 × Cap, 2 × Cap, 4 × Cap, 8 × Cap and 16 × Cap are sequentially shown in FIG. 3, so that five-bit binary adjustment can be met, and the five-bit binary adjustment can be carried out for 32 times; the unit capacitance is designed to be binary weighted to minimize the number of branches. With binary weighted unit capacitors, in order to maintain the same Q factor, the gate widths of the switching and bias transistors also need to be binary weighted to maintain a constant switching speed. The W/L sizes of the switch tube and the bias tube (including the first bias tube and the second bias tube) are doubled step by step, for the size of the switch tube, for the impedance adjustment of the high-Q collator, the first stage finger of the size of the switch tube is 6, the highest stage finger is 96, the problem of overlarge size exists, the half size is tried to be reduced, the CTC structure switch capacitor of the first stage is simulated independently, and the Q value when the first stage is opened is found to be reduced, which is about 50. And finally, the first stage finger can be replaced by 4, the size of the last stage is reduced as much as possible, and the phenomenon that the Q value is too low to cause large insertion loss on the effect of the differential rectifier is avoided.

The drain tube mainly ensures that the grid potential of the CTC structure switch capacitor array is maintained in a low-point state in the system electrifying process, namely all switch tubes and bias tubes are closed, all unit capacitors are not added into a circuit, the problem of floating gate stress of the unit capacitors is mainly solved, and through a large amount of simulation analysis, the MOS tube is found to have a circuit with a similar rectification effect, so that when an alternating current signal is accessed, voltage can be accumulated on the grid electrode of the NMOS switch tube, the voltage on the grid electrode of the NMOS switch tube cannot be drained, and the voltage is increased all the time. Because the output end of the counting output unit is connected with the grid electrode and the output is the output of the phase inverter of the standard MOS tube, the input and the power supply voltage of the phase inverter are very low in the system starting stage, and the voltage on the grid electrode cannot be leaked by the phase inverter of the standard MOS tube when the circuit is started. Based on the above analysis, the gate of the multi-stage CTC structure switch capacitor array is connected to the source of the PMOS bleeder tube, the drain of the PMOS bleeder tube is grounded, the gate of the PMOS bleeder tube is connected to an enable signal of the counter output unit in the impedance adaptive adjustment module (see the specific description of the impedance adaptive adjustment module below), before the counter output unit works, the voltage on the gate is pulled down to the ground through the PMOS bleeder tube, when the enable signal is inverted to a high level, the counter output unit starts to work, and the voltage on the gate of the NMOS switch tube can be charged and discharged through the inverter of the counter output unit, thereby completing the adjustment of the unit capacitor array.

The impedance self-adaptive adjusting module comprises:

in the invention, the impedance self-adaptive adjusting module is used for controlling the on-off of a switch tube in the CTC structure switch capacitor array according to a rectified output signal Vrect output by the differential rectifier. Because the impedance Q value of the passive low-power-consumption tag chip with the self-adaptive impedance adjusting function is larger, even the Q value of the passive low-power-consumption tag chip can be larger than 100, the differential antenna is required to reach the corresponding impedance value and Q value, and the requirements of a high-sensitivity and long-distance tag can be met; in addition, for impedance with a higher Q value, the impedance matching degree of the differential antenna and the radio frequency front end is more sensitive, particularly for the imaginary part of the impedance, the change of the imaginary part by about 1% can cause the change of the rectified output voltage by about 10%, and the requirement on impedance matching is more strict, so that an impedance self-adaptive adjusting module is required to adjust, impedance mismatching caused by factors such as environmental process and the like is corrected, the maximum power acquisition of energy is realized, and the performance requirement on a high-sensitivity and ultra-far distance tag is further completed.

Specifically, as shown in fig. 4, an energy storage capacitor C12 is connected to an output end of the differential rectifier, and a rectified output signal Vrect output by the differential rectifier is used for charging the energy storage capacitor and outputting Vrect to the impedance adaptive adjustment module to supply power to the impedance adaptive adjustment module; the charging process of the energy storage capacitor is called as a power-on process; the impedance self-adaptive adjusting module comprises a clock generating unit, a starting unit, a time sequence adjusting unit, a comparison adjusting unit and a counting output unit. In addition, the input terminals ANT1 and ANT2 of the differential rectifier are respectively connected to two output ports of the differential antenna, and the input terminals ANT1 and ANT2 of the five-bit binary CTC structure switched capacitor array are also respectively connected to two output ports of the differential antenna.

Further concretely:

the clock generation unit is used for generating a reference clock signal CLK and a clock stabilization enabling signal VENO delayed relative to the rectified output signal Vrect under the driving of the rectified output signal Vrect output by the differential rectifier. Specifically, the clock generation unit comprises a current reference circuit and an oscillating circuit; the current reference circuit is used for generating a current reference under the drive of the rectified output signal Vrect; the oscillation circuit is used for charging and discharging a capacitor under the driving of the current reference to generate a clock oscillation signal; the clock oscillation signal includes the reference clock signal CLK and the clock stabilization enable signal VENO.

The starting unit is used for judging whether the power-on process is finished or not by sampling and comparing a rectification output signal Vrect output by the differential rectifier at the starting time and the ending time of one clock cycle based on the reference clock signal CLK and the clock stabilization enabling signal VENO in the power-on process, and generating and outputting a power-on completion enabling signal VEN1 when the power-on process is finished; specifically, the starting unit comprises a first sample-and-hold circuit, a first clocked error comparison circuit and a first RS latch circuit; the first sampling and holding circuit is used for sampling a rectified output signal Vrect output by the differential rectifier under the excitation of the reference clock signal CLK and the clock stabilization enable signal VENO, holding the sampled rectified output signal Vrect for one clock period to obtain a sampling and holding signal Vsh, and outputting the sampling and holding signal Vsh to the first clocked error comparison circuit; the first clocked error comparison circuit is configured to compare the rectified output signal Vrect output by the differential rectifier in the current clock cycle with the sample-and-hold signal Vsh output by the first sample-and-hold circuit in the previous clock cycle, and output a voltage reversal signal when a difference between the rectified output signal Vrect output by the differential rectifier in the current clock cycle and the sample-and-hold signal Vsh output by the first sample-and-hold circuit in the previous clock cycle is within a preset range; the first RS latch circuit is used for latching the voltage turnover signal output by the first clock control error comparison circuit and generating a power-on completion enable signal VEN 1.

The timing adjusting unit is used for converting the reference clock signal CLK into two sample-hold clock signals CLK2 and comparison clock signals CLK2A with the same frequency and preset delay and a counting enable signal VEN2 based on the rectified output signal Vrect and the power-up completion enable signal VEN 1; specifically, the timing adjustment unit includes a latch delay circuit; the latch delay circuit is used for delaying the reference clock signal CLK under the driving of the rectified output signal Vrect, delaying the reference clock signal CLK until the power-on completion enable signal VEN1, generating two sample hold clock signals CLK2 and comparison clock signals CLK2A which have the same frequency and are delayed by one clock period, and generating a count enable signal VEN 2; wherein the comparison clock signal CLK2A is one clock cycle ahead of the sample and hold clock signal CLK2, but all after the power-up completion enable signal VEN1 is generated.

The comparison and adjustment unit is used for performing sampling, holding and comparison judgment on a rectified output signal Vrect output by the differential rectifier based on the power-on completion enable signal VEN1, the sampling and holding clock signal CLK2 and the comparison clock signal CLK2A, outputting a counting signal Vcount, and generating an adjustment completion enable signal VEN3 and a potential signal VDD 2; the clock generation unit is also used for controlling the clock generation unit to be closed according to the potential signal VDD 2; specifically, the comparison adjustment unit includes a second sample-and-hold circuit, a second clocked error comparison circuit, a second RS latch circuit, and an inverting logic circuit; the second sample-and-hold circuit is used for sampling a rectified output signal Vrect output by the differential rectifier under the excitation of the sample-and-hold clock signal CLK2 and the power-up completion enable signal VEN1, holding the sampled rectified output signal Vrect for one clock cycle to obtain a sample-and-hold signal Vsh, and outputting the sample-and-hold signal Vsh to the second clocked error comparison circuit; the second clocked error comparing circuit is used for comparing a rectified output signal Vrect output by the differential rectifier in the current clock period with a sample-and-hold signal Vsh output by the second sample-and-hold circuit in the previous clock period under the excitation of the comparison clock signal CLK2A to generate a count signal Vcount; when the rectified output signal Vrect output by the differential rectifier in the present clock cycle is higher than the sample hold signal Vsh output by the second sample hold circuit in the previous clock cycle, the count signal Vcount is inverted once; when the rectified output signal Vrect output by the differential rectifier in the current clock period is lower than the sample hold signal Vsh output by the second sample hold circuit in the previous clock period, the count signal Vcount is not inverted; the second RS latch circuit is configured to generate an adjustment end enable signal VEN3 for turning off the adaptive adjustment module and a potential signal VDD2 for turning off the clock generation unit when the rectified output signal Vrect output by the differential rectifier in the present clock cycle is first lower than the sample hold signal Vsh output by the second sample hold circuit in the previous clock cycle, and latch the adjustment end enable signal VEN3 and the potential signal VDD 2; the inverting logic circuit is configured to perform inverse logic processing on the count signal Vcount generated by the second clocking error comparing circuit, delay the count signal Vcount after the inverse logic processing by half a clock period with respect to the sample-and-hold clock signal CLK2, and output the count signal Vcount after the inverse logic processing to the count output unit.

The counting output unit is used for carrying out frequency division processing on the counting signal Vcount based on the counting enable signal VEN2 and the rectification output signal Vrect to obtain a multi-bit binary control signal, outputting the multi-bit binary control signal to the CTC structure switch capacitor array, and controlling the on-off of a switch tube in each stage of the CTC structure switch capacitor through the multi-bit binary control signal to determine the number of unit capacitors added into the CTC structure switch capacitor array, so that the self-adaptive impedance adjustment of a radio frequency front end is completed, and the impedance of the radio frequency front end is in conjugate matching with the impedance of the differential antenna; wherein the number of bits of the binary control signal is equal to the number of stages of the CTC-configured switched capacitors in the CTC-configured switched capacitor array; specifically, the counting output unit comprises a logic circuit and a frequency dividing circuit; the logic circuit is used for generating a multi-bit frequency division enable signal; the frequency division circuit is used for performing frequency division processing on the counting signal Vcount under the driving of the counting enable signal VEN2 and the rectification output signal Vrect and with the assistance of a multi-bit frequency division enable signal to obtain a multi-bit binary control signal, outputting the multi-bit binary control signal to the CTC structure switch capacitor array, and controlling the on-off of a switch tube in each stage of the CTC structure switch capacitor through the multi-bit binary control signal to determine the number of unit capacitors added in the CTC structure switch capacitor array, so that the self-adaptive impedance adjustment of a radio frequency front end is completed, and the impedance of the radio frequency front end and the impedance of the differential antenna realize conjugate matching.

The working process of the impedance self-adaptive adjusting module is as follows: the clock generation unit is driven by the rectification output signal Vrect to form oscillation through the charge and discharge of a capacitor with symmetrical current reference, so that a reference clock signal CLK and a clock stabilization enabling signal VEN0 are generated; the starting module samples and compares a rectification output signal Vrect at the previous moment T-T (T is a clock period) and a rectification output signal Vrect at the T moment after the clock period in the label electrifying process, judges that the electrification reaches a stable value when the rectification output signals Vrect at two times are close to or the same, and then generates an electrifying completion enabling signal VEN1 after the electrification is completed; the timing sequence adjusting unit is used for facilitating the mutual noninterference of clock signals of subsequent comparison adjusting units and finishing logic interpretation, and converting a reference clock signal CLK into two sampling holding clock signals CLK2 and a comparison clock signal CLK2A which have the same frequency and certain delay and a counting enabling signal VEN2 in a logic delay processing mode; the comparison adjusting unit finishes the sampling holding and comparison judgment of a rectification output signal Vrect output by the differential rectifier under the action of a sampling holding clock signal CLK2 and a comparison clock signal CLK2A generated by the timing sequence adjusting unit, outputs a judgment result through a counting signal Vcount, and generates an adjustment end enabling signal VEN3 and a potential signal VDD2, when the adjustment is finished, the potential of the potential signal VDD2 is pulled to the ground, the clock generating unit is closed, the whole impedance adaptive adjusting module only stores data by the counting output unit, and the power consumption is greatly reduced; the counting output unit performs frequency division processing on the counting signal Vcount generated by the logic frequency division comparison and adjustment unit under a certain logic, converts the counting signal Vcount into a five-bit binary control signal (in the embodiment, a five-stage CTC structure switch capacitor array is adopted, so the five-bit binary control signal is adopted, specifically, if the CTC structure switch capacitor array is n-stage, the five-bit binary control signal is converted into the n-bit binary control signal), the low-bit to high-bit positions are respectively C1, C2, C3, C4 and C5, and the five-bit binary control signal is respectively connected to the grids of the switch tubes of all stages in the CTC structure switch capacitor array, so that the switch tubes are controlled to be opened and closed, and the self-adaptive impedance adjustment of the radio frequency front end is completed.

In the invention, the working voltage of the impedance self-adaptive adjusting module is very low, the impedance self-adaptive adjusting module can start to work at very low voltage for adjustment, the impedance self-adaptive adjusting module is better adapted to the working environment of a high-sensitivity and long-distance tag, has the characteristics of simple logic but not rigorousness, has extremely low power consumption on the premise of meeting the function, can adjust the impedance of the tag to be optimal by only one adjustment process, and after the adjustment is finished, the self-adaptive module is closed, only the output data of a counter is reserved, the power consumption of the tag work is greatly reduced, and the power consumption and the difference loss are extremely low and far lower than the difference loss of a matching network.

In the present invention, the switch K is controlled by the power-up completion enable signal VEN1 and the adjustment end enable signal VEN 3. Specifically, in the period from the generation of the clock stable enable signal VENO to the generation of the power-on complete enable signal VEN1, the switch K is controlled to be opened, so that the rectified output signal Vrect output by the radio frequency front end precharges the energy storage capacitor C12; during the period from the generation of the power-on completion enable signal VEN1 to the generation of the adjustment end enable signal VEN3, the switch K is controlled to be closed, so that the energy storage capacitor C12 is in a pre-charging state; after the adjustment end enable signal VEN3 is generated, the switch K is controlled to be opened, so that the rectified output signal Vrect output by the radio frequency front end can continuously charge the energy storage capacitor C12 in a pre-charging state. That is, the power-up completion enable signal VEN1 and the adjustment end enable signal VEN3 are trigger conditions of the switch K.

The impedance self-adaptive regulating circuit has extremely low power consumption and is powered by a rectification output signal Vrect output by a radio frequency front end; the detection capacitor C11 independently supplies power to the impedance self-adaptive adjusting circuit, and the capacitance value of the detection capacitor C11 is smaller than that of the energy storage capacitor C12, so that the change of the rectified output voltage can be conveniently detected in a short time. A switch K is arranged on a charging path of the energy storage capacitor C12 by the rectification output signal Vrect, the switch state of the switch K is controlled by the impedance self-adaptive adjusting module, that is, after the circuit starts to be powered on, the switch K is turned on, the radio frequency front end starts to charge the detection capacitor C11 and the energy storage capacitor C12 (the energy storage capacitor C12 is pre-charged), when the charging reaches dynamic balance, the rectification output signal Vrect of the radio frequency front end does not change any more, the impedance self-adaptive adjusting module starts to work, the switch K is turned off, the energy storage capacitor C12 is kept in a pre-charged state, and the charging of the energy storage capacitor C12 is cut off to facilitate the sampling comparison of the impedance self-adaptive adjusting module and adjust the impedance of the radio frequency front end; after the impedance of the radio frequency front end is adjusted, the impedance self-adaptive adjusting module stops working, the current optimal matching state is locked, an enabling signal is output, and a switch K between a rectification output signal Vrect and an energy storage signal is opened again, at the moment, a potential difference exists between two capacitors (a detection capacitor C11 and an energy storage capacitor C12), and a charge transfer process also exists; because the energy storage capacitor C12 has a pre-charging process, the power supply voltage of the impedance self-adaptive adjusting module (the voltage output by the detection capacitor C11) can still support the latch work, and the best matching state is kept.

Load isolation and charge-discharge control module

In the present invention, as shown in fig. 5, the load isolation and charge-discharge control module includes a first reference voltage unit, a voltage division unit, a continuous comparator, and an inversion unit;

the first reference voltage unit is used for generating a reference voltage insensitive to the energy storage voltage and the temperature under the driving of the energy storage voltage output by the energy storage capacitor C12 and outputting the reference voltage to the continuous comparator; the first reference voltage unit adopts a low-voltage low-power consumption reference circuit, and the main principle is that a reference voltage insensitive to the power supply voltage and the temperature is generated by a current insensitive to the power supply voltage or insensitive to the power supply voltage and then performing temperature coefficient compensation through an output circuit.

The voltage dividing unit is used for dividing the energy storage voltage output by the energy storage capacitor C12 to generate two divided voltages with different proportions, and selecting one divided voltage to output to the continuous comparator; the voltage division unit mainly adopts a resistor voltage division form to generate two voltage division values with different proportions for selection of a subsequent continuous comparator.

The continuous comparator is used for comparing the reference voltage output by the first reference voltage unit with the divided voltage output by the voltage dividing unit and outputting a comparison result; the comparison result is used for representing whether the energy storage voltage value of the energy storage capacitor C12 reaches a preset value or not; the continuous comparator adopts a pseudo-differential structure, the reference voltage output by the first reference voltage unit is the bias voltage of the first reference voltage unit, and the reference voltage is compared with the energy storage voltage for voltage division output to judge whether the energy storage voltage reaches a preset value.

The inverting unit is used for managing the charging and discharging process of the energy storage capacitor C12 according to the comparison result output by the continuous comparator and outputting a power supply voltage; the main principle of the phase inversion unit is that in the process of slow charging (pre-charging) of the energy storage capacitor, the conduction current of the phase inverter is reduced (the charging process is long, the phase inverter is in a conduction state for a long time), the upper NMOS and the lower PMOS are in a super-cutoff state when the input of the phase inversion unit is high or low, and the continuous comparator output is prevented from having large-amplitude conduction current in the rising stage (the overturning leakage is controlled to be in the pA level).

Specifically, as shown in fig. 5, the voltage dividing unit includes a voltage dividing network and a data selector, and the inverting unit includes a dynamic leakage suppressor, an inverter and a transistor M; the input end of the first reference voltage unit and the input end of the voltage division network are connected with the charging and discharging end of the energy storage capacitor C12, the output end of the first reference voltage unit is connected with the reverse input end of the continuous comparator, the output end of the voltage division network is connected with the forward input end of the continuous comparator through the data selector, the output end of the continuous comparator sequentially passes through the dynamic leakage suppressor and the phase inverter and is connected with the grid electrode of the transistor M, the output end of the dynamic leakage suppressor is connected on the selection signal input end of the data selector, the source electrode of the transistor M is connected on the charging and discharging end of the energy storage capacitor C12, and the drain electrode of the transistor outputs the power supply voltage.

In order to reduce power consumption and circuit complexity, the continuous comparator adopts a pseudo-differential structure, and adopts reference voltage Vref output by a first reference voltage circuit as bias voltage; one end of the continuous comparator is connected with the reference voltage Vref, the other end of the continuous comparator is connected with the divided voltage of the energy storage voltage, and then comparison is carried out to judge whether the energy storage voltage value of the energy storage capacitor C12 reaches the level for the subsequent circuit to work; when the divided voltage value of the energy storage voltage is higher than the reference voltage Vref, the energy storage voltage is turned over strongly, the control signal EN jumps to 0, the transistor M is turned on, and the post-stage circuit starts to work to complete the work of one period; when the energy storage voltage value of the energy storage capacitor C12 is reduced to a certain value, the continuous comparator is turned over again, the EN signal is pulled high, the transistor M is turned off, and the energy storage capacitor C12 returns to the charging state of the next period.

In the invention, the system architecture of the load isolation and charge-discharge control module and the impedance adaptive adjustment module is reasonably designed, the detection capacitor C11 is connected with the impedance adaptive adjustment module, the energy storage capacitor C12 and the rectification output signal Vrect are controlled by a switch signal, and the energy storage capacitor C12 adopts a pre-charging mode, so that the influence of unstable power supply in the switching process of a switch K is avoided. The impedance self-adaptive adjusting module and the load isolating and charging and discharging control module are switched in state, the load circuit is isolated through the load isolating and charging and discharging control module, the load of the load isolating and charging and discharging control module is basically consistent with the load of the impedance self-adaptive adjusting module, and after the state is switched, the whole circuit is still in the best matching state.

Linear voltage stabilization module

In the present invention, as shown in fig. 6, the linear voltage stabilizing module includes a second reference voltage unit, an error amplifying unit, an adjusting tube and a feedback network;

the second reference voltage unit is used for generating a reference voltage insensitive to the power supply voltage and the temperature under the driving of the power supply voltage output by the load isolation and charge-discharge control module and outputting the reference voltage to the error amplification unit; the principle of the second reference voltage unit is the same as that of the first reference voltage unit.

The error amplifying unit is used for comparing the reference voltage output by the second reference voltage unit with the feedback voltage output by the feedback network to obtain an error signal and controlling the conduction degree of the adjusting tube according to the error signal; the main principle of the error amplification unit is that the operational amplifier with a negative resistance structure is used for improving loop gain and realizing high precision; stabilizing the system by using ESR resistance compensation; meanwhile, a phase advance network is used to provide a pole and a lower frequency zero to provide a phase margin, so that the phase margin of the system is improved.

The adjusting tube is used for outputting stable power supply voltage under the control of the error amplifying unit; the main principle of the adjusting tube is that the conduction degree of the adjusting tube is controlled by an output signal generated by the error amplifying unit, so that stable power supply voltage is ensured to be obtained.

The feedback network is used for obtaining the feedback voltage according to the voltage division ratio of the power supply voltage output by the adjusting tube by a resistance voltage division method.

Specifically, as shown in fig. 6, the feedback network includes a resistor R1 and a resistor R2; the input end of the second reference voltage unit is connected to the output end of the load isolation and charge-discharge control module, the output end of the second reference voltage unit is connected to the forward input end of the error amplification unit, the voltage output end of the error amplification unit is connected to the voltage input end of the adjustment tube, the error signal output end of the error amplification unit is connected to the controlled end of the adjustment tube, the output end of the adjustment tube outputs the power voltage, the output end of the adjustment tube is grounded sequentially through the resistor R1 and the resistor R2, and the common connection end of the resistor R1 and the resistor R2 is connected to the reverse input end of the error amplification unit.

Further, the linear voltage stabilizing module further comprises a reference current unit, wherein the reference current unit is used for generating a stable reference current by adopting a positive and negative temperature coefficient compensation method under the driving of the power supply voltage output by the load isolation and charge-discharge control module, and providing a current reference for the error amplifying unit; the reference current unit mainly comprises a starting circuit, a positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit and a current summation output circuit; the reference current with zero temperature coefficient is generated by adopting a positive and negative temperature coefficient compensation method.

In the invention, because the load isolation and charge-discharge control module is arranged, the load circuit is isolated, and the radio frequency front end and the differential antenna are still in the best matching state at the moment, so that the energy storage capacitor C12 is rapidly charged; the load isolation and charge and discharge control module monitors the energy storage voltage value of the energy storage capacitor C12, when the energy storage voltage value of the energy storage capacitor C12 reaches a set voltage value, a rear-stage circuit is started, the energy storage capacitor C12 discharges to provide energy for the rear-stage circuit, when the rear-stage circuit completes one function, the load isolation and charge and discharge control module closes a discharge path, the energy storage capacitor C12 starts to charge, and the cycle is repeated; because the energy storage capacitor C12 is in a working mode of charging and discharging through the load isolation and charging and discharging control module, and the output voltage of the load isolation and charging and discharging control module is unstable, the linear voltage stabilizing module is adopted to stabilize the power supply voltage output from the load isolation and charging and discharging control module, so as to provide stable power supply voltage for subsequent circuits and digital baseband.

Based on the above specific explanation, the following simulation description is performed on the rf energy harvesting system based on energy management according to the present invention.

The simulation result of the pre-simulation of the radio frequency energy acquisition system based on energy management is shown in fig. 7, the abscissa in fig. 7 is the number of open unit capacitors in the CTC structure switch capacitor array, the ordinate is the rectification output voltage, the rectification output is 400mv when the CTC structure switch capacitor array is fully closed, the CTC structure switch capacitor array is sequentially and manually adjusted, namely the impedance of the radio frequency front end gradually approaches the conjugate impedance of the differential antenna, the rectification output voltage is gradually increased from 0.4V to about 1.07V, the matching degree with the differential antenna is reduced along with the change of the impedance of the radio frequency front end again, the rectification output is reduced, and the rectification output voltage is shown to be a single-peak change according to theoretical analysis and simulation results, namely only one maximum value point exists. In addition, the loss of the CTC structure switch capacitor array is simulated, the difference loss of the CTC structure switch capacitor array is 0.5084dBm, and the difference loss of the CTC structure switch capacitor array is 0.1345 dBm. In addition, under the mismatching of the differential antenna and the radio frequency front end impedance, the trend of adjusting the change of the resonance points of the CTC structure switched capacitor array along with the number of the CTC structure switched capacitors is shown in fig. 8, wherein the state of 00000 is that all the CTC structure switched capacitors in the CTC structure switched capacitor array are not added into the circuit, the resonance points are not in 922.5MHz, and the resonance points gradually approach to 922.5MHz in sequence along with the change of the number of the CTC structure switched capacitors; and obtaining the feasibility of the impedance self-adaptive adjusting module based on the simulation.

In the radio frequency energy acquisition system based on energy management of the invention, a brief flow of an impedance adjustment algorithm is shown in fig. 9, firstly, the output voltage of a differential rectifier is detected, because in the power-on process of the system, an energy storage capacitor C12 needs to be charged, the process is to detect that the rectified output voltage reaches a stable state, after the rectified output voltage is detected to be stable, counting and adding one, keeping the rectified voltage value at the time T, a CTC structure switch capacitor array opens a first-stage switch tube, a first-stage unit capacitor is added, the impedance of the radio frequency front end is adjusted, then the rectified output voltage generates corresponding change, the rectified output voltage at the time T + T (where T is a clock cycle) is detected, namely, the rectified output voltage after the adjustment switch is compared with the rectified output voltage before the adjustment, when the rectified output voltage at the time T + T is judged to be larger than the rectified output voltage at the time T after the adjustment, counting and continuing to increase by one, and circulating the process; and when the rectified output voltage at the T + T moment after adjustment is judged to be smaller than the rectified output voltage at the T moment when the rectified output voltage is not adjusted, a next instruction is made, the impedance self-adaptive adjusting module is closed, the counting output unit data is locked and kept, the adjustment is finished, the whole impedance adjusting process is completed, and the optimal matching point is reached.

The operation of the present invention will be explained in detail based on the structure shown in fig. 4.

Firstly, the differential antenna collects radio frequency signals, then the differential rectifier converts the radio frequency signals collected by the differential antenna into direct current signals and outputs a rectified output signal Vrect, namely the rectified output signal Vrect shown in fig. 4; the rectification output signal Vrect is used for charging the detection capacitor C1 and the energy storage capacitor C12, so the system has a power-on process, the detection capacitor C11 and the energy storage capacitor C12 are stable, and the system can work under the action of the rectification output signal Vrect in the power-on process because the working voltage of the impedance self-adaptive adjusting module is low. Firstly, a clock generating unit generates a reference clock signal CLK, detects a rectification output signal Vrect under the reference clock signal CLK, judges whether the rectification output signal Vrect is stable through sampling and holding, and prevents a post comparison adjusting unit from misjudging in the power-on process of a system; once the rectified output signal Vrect is detected to be stable, the power-on completion enable signal VEN1 is generated, the switch K is closed, and the change of the rectified output signal Vrect is conveniently detected, the timing adjustment unit generates a pair of a sampling holding clock signal CLK2 and a comparison clock signal CLK2A which are mutually delayed by one clock period; the sample-and-hold clock signal CLK2 is the subsequent sampling clock, and the comparison clock signal CLK2A is the subsequent comparison clock, i.e., the comparison clock is one clock cycle earlier than the sampling clock; however, the counting input signal is generated after the counting enable signal VEN2, even if the comparison sampling is performed, the counter does not work at this time, the output of the counter is still kept at zero, the unit capacitors in the five-bit binary CTC structure switch capacitor array are all closed and are not added with circuits, when the counting enable signal VEN2 comes and starts to change, the counting signal Vcount is added with one for the first time, the rectified output signal Vrect before and after the addition of one for the counting signal Vcount is sampled and compared, the process is circulated until the rectified output signal Vrect is detected to be reduced, the adjustment end enable signal VEN3 for closing the impedance adaptive adjusting module is generated, data is latched, the switch k is opened again, the energy storage capacitor C12 is continuously charged, the impedance end adjusting process is performed, and at this time, the radio frequency front end and the differential antenna complete the optimal energy transmission.

FIG. 10 is a timing diagram of signals in an RF energy harvesting system based on energy management according to the present invention; specifically, the VEN1 is an enable signal for stable system power-on, that is, a power-on completion enable signal; the VEN2 is an enabling signal of the working of the counter, namely a counting enabling signal, and is used for driving a PMOS (P-channel metal oxide semiconductor) discharge tube in a 5-bit binary CTC (cell-to-cell) structure switch capacitor array to ensure that the grid voltage of an NMOS (N-channel metal oxide semiconductor) switch tube cannot be accumulated in the power-on process; CLK2A is the comparison clock signal; CLK2 is a sample-and-hold clock signal; vcoun is a counting signal after the output result of the comparator in the comparison and adjustment unit is processed by an enabling signal, the counting signal Vcount is output to the counting output unit, C1 is the output result of a first-bit counter in the counting output unit (the upper bits C2, C3, C4 and C5 are ignored here, and the five-bit binary control signals are respectively connected to the gates of the switch tubes of the five-stage CTC structure switch capacitor array so as to control the switching of the switch tubes), logic frequency division processing is carried out through the counting signal Vcount, VEN3 is an adjustment end enabling signal, Vrect is a rectification output signal, and Vsh is a sampling and holding signal. After the power-on completion enable signal VEN1 is inverted to a high level, which indicates that the rectified output is stable, the subsequent adjustment is started, and a subsequent comparison clock signal CLK2A and a sample-and-hold clock signal CLK2 are generated, the rectified output signal Vrect and the sample-and-hold signal Vsh are compared at the rising edge of the comparison clock signal CLK2A, because the sample-and-hold clock signal CLK2 is one clock cycle later than the comparison clock signal CLK2A, the rectified output signal Vrect at the time of T0 is certainly higher than the sample-and-hold signal Vsh, the comparison result is that the counter is first added, the count signal Vcount starts to be inverted and output, the count signal Vcount is delayed by half a clock cycle through logic processing, the inversion happens just at the low level of the sample-and-hold clock signal CLK2, namely, the sample-and-hold clock signal CLK2 samples at a high level, the output result of the clock low level counter, the switching tube is adjusted, and the sample-and hold and adjustment switching tube are placed in different time periods to be completed, cross errors are avoided; sampling a rectified output signal Vrect output by a differential rectifier at the stage of T0-T1, wherein the five-bit binary control signal of the sampled rectified output signal Vrect corresponding to the CTC structure switch capacitor array is 00000; in a stage T1-T2, a sample hold signal is Vsh (00000 state), and in the stage, a unit capacitor is opened, the impedance of the radio frequency front end changes, the output of the differential rectifier starts to be adjusted, and finally, a rectified output signal Vrect (00001 state) of the CTC structure switch capacitor array in a 00001 state is achieved; at time T2, the sample-and-hold signal Vsh (00000 state) is compared with the rectified output signal Vrect (00001 state), and a decision is made to count the output of the signal Vcount, the C1 signal flips on the falling edge of the sample-and-hold clock signal CLK 2; at the stage T2-T3, the output of the differential rectifier is sampled, and the sample hold signal Vsh is in a 00001 state; at stages T3-T4, the output of the differential rectifier is adjusted to be a rectified output signal Vrect (00010 state); at time T4, the sample-and-hold signal Vsh (00000 state) is compared with the rectified output signal Vrect (00001 state), and a determination is made to count the output of the signal Vcount; the following phases cycle the above processes in sequence, that is, at time T6, the sample hold signal Vsh (00010 state) is compared with the rectified output signal Vrect (00011 state); at time T8, sample-and-hold signal Vsh (00011 state) is compared to rectified output signal Vrect (00100 state); at time T10, sample-and-hold signal Vsh (00100 state) is compared to rectified output signal Vrect (00101 state); at time T12, sample-and-hold signal Vsh (00101 state) is compared to rectified output voltage Vrect (00110 state). At the time of T12, the sample hold signal Vsh (00101 state) is higher than the rectified output signal Vrect (00110 state), it is determined that the output of the differential rectifier decreases, the count signal Vcount stops flipping, and an adjustment end enable signal VEN3 is generated, the impedance adaptive adjustment module is turned off, only the output signal (five-bit binary control signal) of the five-bit counter is retained, the adjustment of the CTC structure switched capacitor array is completed, and the optimal rectified output voltage is achieved.

Until now, the energy transmission reaches the optimal state, the following is the continuous charging process of the subsequent energy storage capacitor C12, and as the load circuit is isolated by the load isolation and charge-discharge control module, the load of the load isolation and charge-discharge control module is basically consistent with the load of the impedance self-adaptive adjusting module at this moment, the influence of the load change on the previous optimal matching effect is little, so that the switching state after the switch k is opened is ensured, and the matching effect locked by the impedance self-adaptive adjusting module is still at the optimal matching point; then under the control of an enabling signal of the impedance self-adaptive adjusting module, the rectification output signal Vrect is used for rapidly charging the energy storage capacitor C12, the load isolation and charging and discharging control module monitors the energy storage voltage value of the energy storage capacitor C12, and after the energy storage voltage value reaches a set voltage value, a rear-stage circuit is started to generate an output voltage VDC which is provided for the low-voltage-difference linear voltage stabilizing module; under the drive of the voltage VDC, the current reference and the voltage reference in the linear voltage stabilizing module respectively generate reference current and reference voltage which are not changed by power supply voltage and temperature, the reference current and the reference voltage are supplied to a subsequent error amplification unit, stable power supply output Vout is generated through an adjusting tube and a feedback network, the reasonable utilization of the acquired energy is completed, the acquired energy is utilized to the maximum extent, and stable power supply voltage VDD is generated.

In the radio frequency energy acquisition system based on energy management, the impedance self-adaption impedance adjusting process comprises the steps of detecting the output voltage of a differential rectifier and then adjusting the impedance of a radio frequency front end; maximum energy transmission of the differential antenna and the radio frequency front end is realized; in addition, the antenna impedance and the radio frequency front end impedance are cooperatively designed by adopting a direct impedance conjugation mode aiming at the tag chip with high sensitivity and high Q value, so that a matching network for additionally matching a 50 omega antenna is reduced; because the impedance Q value of the tag chip is higher, the impedance change of the tag chip is more sensitive to the output of the differential rectifier, and the tag chip is subjected to self-adaptive adjustment under the external influences of process, temperature, environment and the like, so that the impedance of the antenna and the radio frequency front end is ensured to be in the optimal matching state. It is also required to explain that the invention effectively manages the collected energy, and isolates the load of the rear-stage circuit by adding the load isolation and charge-discharge control module, and the load change and state switching process avoid the problem of matching failure caused by the load change, thereby ensuring the switching state after the switch k is opened, and the matching effect of the impedance self-adaptive adjustment module locking is still at the optimal matching point; because the energy storage capacitor adopts the working mode of energy management charging and discharging, the invention also needs a linear voltage stabilizing circuit to generate stable power output. The invention relates to a radio frequency front end which is the most basic and key part of a passive tag, supplies energy to the whole tag system and is the premise and key for realizing a remote passive tag.

By the above explanation, the advantages of the present invention are summarized as follows:

1. the antenna impedance and the radio frequency front end impedance are cooperatively designed in a direct impedance conjugation mode, an extra matching network which is matched with 50 omega is removed, and the difference loss during matching is reduced.

2. The self-adaptive impedance adjusting circuit has the characteristics of simple logic and no strict loss, has extremely low power consumption on the premise of meeting the function, can adjust the impedance of the tag to be optimal only by one adjusting process, and can close the impedance self-adaptive adjusting module after the adjustment is finished, only the output data of the counter is reserved, and the power consumption of the tag work is greatly reduced.

3. The impedance self-adaptive adjusting module has low working voltage, can start to work at low voltage for adjustment, and is better suitable for the working environment of high-sensitivity and long-distance labels.

4. The invention has the advantages of adjustable impedance adjusting times, more adjusting times, high adjusting precision and large adjustable range.

5. According to the invention, the impedance self-adaptive adjusting module and the load isolation and charge-discharge control module are reasonably designed to be linked, and the load isolation and charge-discharge control module is used for isolating the heavy current load of the rear-stage circuit, so that the impedance of the circuit is always in the best matching state. The method comprises the steps of carrying out pre-charging operation by reasonably controlling the opening time of a switch K, solving the problem of unstable voltage when a circuit is switched, adjusting the radio frequency front end and an antenna to the optimal transmission efficiency, and continuously charging a rear-stage energy storage capacitor C12, so that the charging speed is increased, and the high-efficiency utilization of the obtained energy is realized;

6. all circuits of the invention use the standard CMOS process, realize all integrated on the circuit chip, reduce the production cost, produce in batches.

Based on the radio frequency energy acquisition system based on energy management, the invention also provides a passive radio frequency tag.

As shown in fig. 11, a passive rf tag includes the rf energy collection system based on energy management as described above, and the passive rf tag further includes an analog front end, an EEPROM, and a digital baseband;

the output of the linear voltage stabilizing module is connected with the analog front end, the analog front end is respectively connected with the EEPROM and the digital baseband, and the EEPROM is connected with the digital baseband;

the analog front end is used for providing stable power output, reference output, clock signals and reset signals for the EEPROM and the digital baseband under the driving of the power voltage output by the linear voltage stabilizing module; the antenna is also used for receiving the RF signal transmitted by the antenna, demodulating the RF signal transmitted by the antenna to generate a baseband signal and sending the baseband signal to a digital baseband;

the digital baseband is used for carrying out command analysis on the baseband signal to generate a corresponding instruction and a corresponding parameter;

the EEPROM is used for providing corresponding data read-write operation for the digital baseband according to the instruction and the parameter and returning corresponding read-write operation data to the digital baseband according to the instruction and the parameter;

the digital baseband is also used for transmitting the read-write operation data and/or the internal data of the digital baseband returned by the EEPROM to an analog front end;

the analog front end is further configured to modulate the read-write operation data and/or the internal data of the digital baseband transmitted by the digital baseband, and send the modulated read-write operation data and/or the internal data of the digital baseband to an antenna.

Specifically, as shown in fig. 12, the digital baseband includes a power consumption management module, a decoding module, an initialization module, an MTP control module, a frequency division module, a random number generation module, a command parsing module, a main state machine module, and an output control module. The subsequent analog front end generates corresponding clock signal, reset signal, power voltage and data input signal under the power voltage output by the linear voltage stabilizing module, and provides the clock signal, reset signal, power voltage and data input signal to the digital baseband, data exchange and instruction operation are carried out through EEPORM, the information processed by the digital baseband is transmitted to the analog front end, and information transmission is carried out through a modulation circuit of the analog front end.

Specifically, the functions of each part of the digital baseband are explained as follows: the decoding module analyzes the PIE code, identifies a frame header and data, extracts length information of an RTcal parameter and a TRcal parameter in the frame header, decodes the data and distinguishes data 0 and data 1; the command parsing module parses out 0 and 1 from the decoding module to identify the command type and the parameters carried by the command in the data stream, and completes the CRC check of the command. For the SELECT command, memory read operation is required to be carried out to complete the matching of MASK; the host state module completes state skip, the turning of the inventory flag and the updating of random numbers according to the current state of the tag and the received command, and also provides output type coding information required by returned data; the MTP control module completes the time sequence control of the related interface signals according to the requirement of reading and writing the memory by the command and the specification of the MTP document; the output control module prepares data to be returned according to the output type coding information given by the label main state machine module, and carries out FM0 or Miller coding output on the data; the power consumption management module is a control core of the whole baseband, controls the opening and closing of the work of different modules according to the processing flow needs, generates an enabling signal corresponding to the work of the modules, generates a gated clock corresponding to the work of the modules and reduces the whole power consumption; the frequency division module divides the frequency of a 1.92MHz main clock provided by the analog front end to generate a required global clock DOUB _ BLF, an MTP write control clock 60kHz and a data _ clk clock for controlling the return rate; after the label is powered on, the initialization module completes a series of initialization operations, such as reading EPC to calculate CRC16, reading a label status word and the like; the random number generation module is seeded with a power-up computed CRC16, shifting the pseudo-random number required by the generation protocol.

The passive radio frequency tag carries out conjugate matching on the antenna and the radio frequency front end in a cooperative coupling mode, and directly couples and matches the antenna and the radio frequency front end to enable the antenna and the radio frequency front end to reach an optimal matching point or nearby, standard 50-ohm matching is not needed, and energy loss is reduced; due to the existence of the load isolation and charge-discharge control module, the load can be isolated, the load of the load isolation and charge-discharge control module is basically consistent with the load of the impedance self-adaptive adjustment module, the antenna and the radio frequency front end are still in the optimal matching state after state conversion is carried out through the switch K, the energy storage capacitor C12 is rapidly charged, and the energy storage time is saved; the energy storage capacitor C12 adopts a pre-charging mode, so that the influence of unstable power supply in the switching process of the switch K is avoided, and stable power supply voltage can be provided for a subsequent circuit under the voltage stabilization of the linear voltage stabilization module; the capacitance value of the detection capacitor C11 is smaller than that of the energy storage capacitor C12, the impedance self-adaptive adjusting module can work alone when the detection capacitor C11 is charged to a certain degree, adjustment and matching are achieved, the energy storage capacitor C12 can be charged with higher efficiency, the impedance self-adaptive adjusting module is not limited by the charging degree of the energy storage capacitor C12, and therefore the working starting time can be shortened, in addition, the capacitance value of the detection capacitor C11 is set to be smaller, and the change of the rectification output signal can be detected conveniently in a short time. Therefore, the invention can solve the impedance mismatch condition under the influence of factors such as process, environment and the like in a certain impedance range, adaptively adjust the impedance of the circuit to achieve the conjugate matching with the antenna, does not need additional inductance elements, is beneficial to the integration in a chip, realizes the maximum power collection and the energy utilization, and improves the sensitivity and the working distance of the passive tag.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.